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8086 & 8088 Microprocessors

Course Code:EE2323 Microprocessors & Computer Architecture Spring-2014, M.A.J.U Islamabad 8086 Microprocessor (1978) 16-bit microprocessor 20-bit Address Bus 16-bit Data Bus 6-byte instruction queue Separate Data & Segment Registers 8088 Microprocessor (1979) 16-bit microprocessor 20-bit Address Bus 8-bit Data Bus 4-byte instruction queue Separate Data & Segment Registers
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Lecture 4: Microprocessors & Computer Architecture 8086/8088 Microprocessors

8086/8088 Processor Microarchitecture

Micro-architecture is internal architecture of a processor 8086/8088 microprocessors have pipelined micro architecture that employ parallel processing Micro-architecture of 8086/8088 microprocessors consist of two independent processing units
Bus interface Unit (BIU) Execution Unit (EU)

8086/8088 Processor Microarchitecture

BIU & EU make fetch & execution of instructions independent operations Both units execute in parallel and result in efficient use of system bus and higher performance

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Bus Interface Unit (BIU)

BIU is 8086/8088 interface to the outside world BIU is responsible for performing all external bus operations such as instruction fetching, reading/writing of data to memory and address generation BIU is composed of system bus, segment registers, instruction pointer, address generation unit and instruction queue System bus include bidirectional data bus, 20 bit address bus and control bus Instruction queue is a FIFO queue where program instructions are prefetched in sequential order and fed into the execution unit
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Execution Unit (EU)

Execution unit is responsible for decoding & execution of program instructions Execution unit is composed of general purpose registers, ALU, control flags & temporary operand registers EU accesses instructions from instruction queue, decodes them, reads operands from registers/memory and performs the operation specified by instruction ALU performs arithmetic, logic, shift operations and may update control flags EU may also request BIU to perform read/write operations on memory or I/O devices If instruction queue is empty, EU waits for the instruction to be fetched
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Memory Address Space

Memory in an 8086 microprocessor is byte addressable With 20-bit address bus an 8086 P can address 1M ( 220) distinct memory locations Memory space is organized as consecutive byte locations over the address range 00000H to FFFFFH 8086 microprocessor can access data in memory as a byte (8-bits), word (16-bits) and double word (32-bits) 16 bit & 32 bit data occupy multiple byte locations in memory
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Byte Ordering (Endianness)

Multiple byte data can be stored in memory in two formats Little Endian
Least significant byte goes to low memory location & most significant byte goes to high memory location

Big Endian
Most significant byte goes to low memory location & least significant byte goes to high memory location 8086/8088 based processors memory in little endian format access
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Byte Ordering (Endianness) : Example

Example : Store 16-bit words 1234H and 5678H at Memory Addresses 0x10000H & 0x10002H in Little Endian & Big Endian Format

Byte Ordering (Endianness) : Example

Example : Store 8-bit data 12H, 39H, 85H, 48H at Memory Addresses 0x10000H to 0x10003H in Little Endian & Big Endian Format

Endianness does not matter for 8bit

Big Endian

Little Endian
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Big Endian

Little Endian
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Memory Alignment
For storage of multi-byte data elements such as 16-bit, 32-bit , 64-bit data memory address is either aligned or misaligned An aligned address for an n-byte data element is an address that is multiple of n
For 2 byte data, aligned address should be multiple of 2 For 4 byte data, aligned address should be multiple of 4 For 8 byte data, aligned address should be multiple of 8

Memory Alignment : Word Data

Word data is composed of two bytes For word size data an aligned memory address should be a multiple of 2 A word data stored at an even address is said to be aligned word A word data stored at an odd address is said to be a misaligned word

If the address of an n-byte data in memory is not multiple of n it is said to be misaligned/unaligned x86 processors can handle both aligned and misaligned memory addresses

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Memory Alignment : Word Data

Memory Alignment Double word Data

Double word data is composed of four bytes

Address
0008H 0007H 0006H 0005H 0004H 0003H 0002H 0001H 0000H

Physical Memory
Byte 8 Byte7
Word 6

Misaligned Words

An aligned double word is stored at a memory address that is a multiple of 4 If a double word is stored at an address that is not a multiple of 4 it is said to be a misaligned double word

Byte 6 Byte 5 Byte 4 Byte 3

Word 2 Word 4 Word 3

Aligned Words
Word 1

Byte 2 Byte 1 Byte 0

Word 0

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Memory Alignment Double word Data

Aligned Double Words Address
0008H 0007H 0006H 0005H 0004H 0003H 0002H 0001H 0000H

Memory Alignment of Data

Physical Memory
Byte 8 Byte7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
Double Word 0 Double Word 1 Double Word 4 Double Word 3 Double Word 2 Double Word 5

Not Aligned Double Words

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Data Types
Data formats supported by 8086/8088 P are :

Data Types
BCD Data
BCD data is processed either in unpacked or packed form in 8086/8088 microprocessors In unpacked form one BCD digit is stored in 4 least significant bits of a byte while upper 4 bits are set to zero In packed form two BCD digits are stored in a byte

Integer Data
Integer data may exist as :
Byte (8-bits) Word (16-bits) Double Word (32-bits)

Integer data is processed by 8086/8088 as unsigned or signed data Negative numbers are stored and processed in 2s complement form

ASCII Data
Each ASCII character is stored in a byte in 8086/8088 microprocessors

8086/8088 P has specific instructions to handle BCD and ASCII Data

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8086/8088 P Software Model

Software model of a processor explain the internal CPU registers, their types and usage, their limitations, memory and I/O address space, address generation, control and status flags Software model helps software programmer understanding operation of the microprocessor in

8086/8088 P Software Model

8086 Memory Space (1M)

8086 Register File

8086 software model includes an instruction pointer (IP) register, 12 16-bit internal registers, a status/flag register and memory & I/O address spaces Software architecture of 8086 & 8088 microprocessors is same
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8086 I/O Space (64k)

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8086/8088 Register File

Data Register
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Accumulator AX Base BX Counter CX Data DX

Segment Register
0 7 AL BL CL DL 0 15
Code Segment CS Data Segment DS Extra Segment ES Stack Segment SS

AH BH CH DH

CS DS ES SS

Pointer Register
Stack Pointer Base Pointer

Flag Register
SP BP 0
Status and control flag

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Flag H

0 7

Flag L

Index Register
Source Index Destination Index

Instruction Pointer
SI DI 0
Instruction Pointer

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IP

* All 8086 Registers are 16 bits in size. 8086 data registers are further divided into two 8-bit halves
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