UNIT IV PIC MICROCONTROLLERS

OVERVIEW OF PIC MICROCONTROLLER PIC stands for Peripheral Interface Controller given by Microchip Technology to identify its single-chip microcontrollers. These devices have been very successful in 8-bit microcontrollers. The main reason is that Microchip Technology has continuously upgraded the device architecture and added needed peripherals to the microcontroller to suit customers' requirements. The architectures of various PIC microcontrollers can be divided as follo s. Low - end PIC Architectures: Microchip PIC microcontrollers are available in various types. !hen PIC microcontroller MC" as first available from #eneral Instruments in early $%8&'s' the microcontroller consisted of a simple processor e(ecuting $)-bit ide instructions ith basic I*+ functions. These devices are ,no n as lo -end architectures. They have limited program memory and are meant for applications requiring simple interface functions and small program - data memories. .ome of the lo -end device numbers are $)C/00 $1C/0 $1C/&/ Mid range PIC Architectures Mid range PIC architectures are built by upgrading lo -end architectures ith more number of peripherals' more number of registers and more data*program memory. .ome of the mid-range devices are $1C10 $1C20 $13820 Program memory type is indicated by an alphabet. C 4 5P6+M 3 4 3lash 6C 4 Mas, 6+M Popularity of the PIC microcontrollers is due to the follo ing factors. $. .peed7 8arvard 9rchitecture' 6I.C architecture' $ instruction cycle 4 : cloc, cycles. ). Instruction set simplicity7 The instruction set consists of ;ust </ instructions =as opposed to $$$ instructions for 8&/$>.

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<. Po er-on-reset and bro n-out reset. ?ro n-out-reset means hen the po er supply goes belo a specified voltage =say :@>' it causes PIC to resetA hence malfunction is avoided. 9 atch dog timer =user programmable> resets the processor if the soft are*program ever malfunctions and deviates from its normal operation. :. PIC microcontroller has four optional cloc, sources.
o o o o

Bo po er crystal Mid range crystal 8igh range crystal 6C oscillator =lo cost>.

/. Programmable timers and on-chip 9CC. 1. "p to $) independent interrupt sources. 2. Po erful output pin control =)/ m9 =ma(.> current sourcing capability per pin.> 8. 5P6+M*+TP*6+M*3lash memory option. %. I*+ port e(pansion capability. $&. 3ree assembler and simulator support from Microchip at CPU Architecture: The CP" uses 8arvard architecture ith separate Program and @ariable =data> memory interface. This facilitates instruction fetch and the operation on data*accessing of variables simultaneously. .microchip.com

3ig.:.$ CP" 9rchitecture of PIC microcontroller PIC Me or! Organi"ation: PIC microcontroller has $< bits of program memory address. 8ence it can address up to 8, of program memory. The program counter is $<-bit. PIC $1C10 or $1C20 program memory is ), or :,. !hile addressing ), of program memory' only $$- bits are required. 8ence t o most significant bits of the program counter are
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ignored. .imilarly' counter is ignored.

hile addressing :, of memory' $) bits are required. 8ence the M.? of the program

3ig:.). Program Memory map The program memory map of PIC$1C2:9 is sho n in 3ig :.). +n reset' the program counter is cleared and the program starts at &&8. 8ere a 'goto' instruction is required that ta,es the processor to the mainline program. !hen a peripheral interrupt' that is enabled' is received' the processor goes to &&:8. 9 suitable branching to the interrupt service routine =I.6> is ritten at &&:8. #ata e or! $Register %i&es':

Cata Memory is also ,no n as 6egister 3ile. 6egister 3ile consists of t o components. $. #eneral purpose register file =same as 69M>. ). .pecial purpose register file =similar to .36 in 8&/$>.

3ig :.< Cata Memory map The special purpose register file consists of input*output ports and control registers. 9ddressing from &&8 to 338 requires 8 bits of address. 8o ever' the instructions that use direct addressing modes in PIC to address these register files use 2 bits of instruction only. Therefore the register ban, select =6P&> bit in the .T9T". register is used to select one of the register ban,s.
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In indirect addressing 3.6 register is used as a pointer to any here from &&8 to 338 in the data memory.

(asic Architecture o) PIC Microcontro&&ers .pecifications of some popular PIC microcontrollers are as follo s7 #e*ice Progra #ata RAMI.O A#C Me or! $-!tes' Pins $+,-its' $1C2:9 :D 5P6+M $%) << 8 bits ( 8 channels $13822 8D 3lash <18 =69M> << $& bits ( )/1 =55P6+M> 8 channels Ti ers CCP /.+0 -its $P1M' )*$ )*$ ) ) USART SPI . I2C ".96T .PI * I)C ".96T .PI * I)C

#e*ice Interru3t Sources $1C2:9 $) $13822 $/ PIC Microcontro&&er C&oc4

Instruction Set </ </

Most of the PIC microcontrollers can operate upto )&M8E. +ne instructions cycle =machine cycle> consists of four cloc, cycles.

3ig :.: 6elation bet een instruction cycles and cloc, cycles for PIC microcontrollers Instructions that do not require modification of program counter content get e(ecuted in one instruction cycle. 9lthough the architectures of various mid range 8 - bit PIC microcontroller are not the same' the variation is mostly interns of addition of memory and peripherals. !e ill discuss here the architecture of a standard midrange PIC microcontroller' $1C2:9. "nless mentioned other ise' the information given here is for a PIC $1C2:9 microcontroller Chip. 9rchitecture of PIC$1C2:9

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3ig :./ ?asic 9rchitecture of PIC $1C2:9 The basic architecture of PIC$1C2:9 is sho n in fig :./. The architecture consists of Program memory' file registers and 69M' 9B" and CP" registers. It should be noted that the program Counter is $< bit and the program memory is organiEed as $: - bit ord. 8ence the program Memory capacity is 8, ( $: bit. 5ach instruction of PIC $1C2:9 is $: - bit long. The various CP" registers are discussed here. CPU registers $registers co on&! used -! the CPU'

!' the or,ing register' is used by many instructions as the source of an operand. This is similar to accumulator in 8&/$. It may also serve as the destination for the result of the instruction e(ecution. It is an 8 bit register.

3ig.:.1 ! 6egister STATUS Register The .T9T". register is a 8-bit register that stores the status of the processor. This also stores carry' Eero and digit carry bits.
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.T9T". - address &<8' 8<8

3ig :.2 .T9T". register C 4 Carry bit CC 4 Cigit carry =same as au(iliary carry> F 4 Fero bit G+THT+ and G+THPC - "sed in con;unction ith PIC's sleep mode 6P&- 6egister ban, select bit used in con;unction ith direct addressing mode. %SR Register =3ile .election 6egister' address 4 &:8' 8:8> 3.6 is an 8-bit register used as data memory address pointer. This is used in indirect addressing mode. IN#% Register =IGCirect through 3.6' address 4 &&8' 8&8> IGC3 is not a physical register. 9ccessing IGC3 access is the location pointed to by 3.6 in indirect addressing mode. PCL Register =Program Counter Bo ?yte' address 4 &)8' 8)8> PCB is actually the lo er 8-bits of the $<-bit program counter. This is a both readable and ritable register. PCLAT5 Register =Program Counter Batch' address 4 &98' 898> PCB9T8 is a 8-bit register hich can be used to decide the upper /bits of the program counter. ritten to ithout

PCB9T8 is not the upper /bits of the program counter. PCB9T8 can be read from or

affecting the program counter. The upper <bits of PCB9T8 remain Eero and they serve no purpose. !hen PCB is ritten to' the lo er /bits of PCB9T8 are automatically loaded to the upper /bits of the program counter' as sho n in the figure.

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3ig :.8 .chematic of ho PCB is loaded from PCB9T8 Progra Counter Stac4 9n independent 8-level stac, is used for the program counter. 9s the program counter is $<bit' the stac, is organiEed as 8($<bit registers. !hen an interrupt occurs' the program counter is pushed onto the stac,. !hen the interrupt is being serviced' other interrupts remain disabled. 8ence' other 2 registers of the stac, can be used for subroutine calls ithin an interrupt service routine or ithin the mainline program. Register %i&e Ma3 It can be noted that some of the special purpose registers are available both in ?an,-& and ?an,-$. These registers have the same value in both ban,s. Changing the register content in one ban, automatically changes its content in the other ban,.

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3ig :.% 6egister 3ile Map

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Port Structure and Pin Con)iguration o) PIC +0C6,A 9s mentioned earlier' there is a large variety of PIC microcontrollers. 8o ever' the midrange architectures are idely used. +ur discussion ill mainly confine to PIC$1C2:9 hose architecture has most of the required features of a mid-range PIC microcontroller. .tudy of any other mid-range PIC microcontroller ill not cause much variation from the basic architecture of PIC $1C2:9. PIC $1C2:9 has / I*+ Ports. 5ach port is a bidirectional I*+ port. In addition' they have the follo ing alternate functions.

In addition to I*+ pins' there is a Master clear pin =MCB6> hich is equivalent to reset in 8&/$. 8o ever' unli,e 8&/$' MCB6 should be pulled lo to reset the micro controller. .ince PIC$1C2:9has inherent po er-on reset' no special connection is required ith MCB6 pin to reset the micro controller on po er-on. There are t o @CC pins and t o @.. pins. There are t o pins =+.C$ and +.C)> for connecting the crystal oscillator* 6C oscillator. 8ence the total number of pins ith a $1C2:9 is <<I24:&. This IC is commonly available in a dual-in-pin =CIP> pac,age.

3ig :.$& Pin configuration of PIC $1C2:9

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INSTRUCTION SET 7uide&ines )ro Microchi3 Techno&og!

3or riting assembly language program Microchip Technology has suggested the follo ing guidelines. $. !rite instruction mnemonics in lo er case. =e.g.' mov f> ). !rite the special register names' 69M variable names and bit names in upper case. =e.g.' PCB' 6P&' etc.> <. !rite instructions and subroutine labels in mi(ed case. =e.g.' Mainline' BoopTime> Instruction Set: The instruction set for PIC$1C2:9 consists of only </ instructions. .ome of these instructions are byte oriented instructions and some are bit oriented instructions. The -!te oriented instructions that require t o parameters =3or e(ample' movf f' 3=!>> e(pect the f to be replaced by the name of a special purpose register =e.g.' P+6T9> or the name of a 69M variable =e.g.' G"M$>' hich serves as the source of the operand. 'f' stands for file register. The 3=!> parameter is the destination of the result of the operation. It should be replaced by7 3' if the destination is to be the source register. !' if the destination is to be the or,ing register =i.e.' 9ccumulator or ! register>. The -it oriented instructions also e(pect parameters =e.g.' btfsc f' b>. 8ere 'f' is to be replaced by the name of a special purpose register or the name of a 69M variable. The 'b' parameter is to be replaced by a bit number ranging from & to 2. 3or e(ample7 F equ ) btfsc .T9T".' F F has been equated to ). 8ere' the instruction instruction if F bit is clear. ill test the F bit of the .T9T". register and ill s,ip the ne(t

The &itera& instructions require an operand having a ,no n value =e.g.' &98> or a label that represents a ,no n value. 3or e(ample7 G"M equ &98 A movl G"M A 9ssigns &98 to the label G"M = a constant > ill move &98 to the ! register.

5very instruction fits in a single $:-bit ord. In addition' every instruction also e(ecutes in a single cycle' unless it changes the content of the Program Counter. These features are due to the fact that PIC micro controller has been designed on the principles of 6I.C =6educed Instruction .et Computer> architecture.

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Instruction set: Mnemonics bcf f' b bsf f' b clr clrf f movl , mov f f movf f' 3=!> s apf f' 3=!> andl , and f f' 3=!> and f f' 3=!> iorl , ior f f' 3=!> (orl , (or f f' 3=!> addl , add f f' 3=!> subl , sub f f' 3=!> rlf f' 3=!> rrf f' 3=!> btfsc f' b btfss f' b decfsE f' 3=!> incfcE f' 3=!> goto label call label retrun retl , Instruction Cycles Clear bit b of register f $ .et bit b of register f $ Clear or,ing register ! $ Clear f $ Move literal ',' to ! $ Move ! to f $ Move f to 3 or ! $ . ap nibbles of f' putting result in 3 or ! $ 9nd literal value into ! $ 9nd ! ith 3 and put the result in ! or 3 $ 9nd ! ith 3 and put the result in ! or 3 $ inclusive-+6 literal value into ! $ inclusive-+6 ! ith f and put the result in 3 or ! $ 5(clusive-+6 literal value into ! $ 5(clusive-+6 ! ith f and put the result in 3 or ! $ 9dd the literal value to ! and store the result in ! $ 9dd ! to f and store the result in 3 or ! $ .ubtract the literal value from ! and store the result in ! $ .ubtract f from ! and store the result in 3 or ! $ Copy f into 3 or !A rotate 3 or ! left through the carry $ bit Copy f into 3 or !A rotate 3 or ! right through the carry $ bit Test 'b' bit of the register f and s,ip the ne(t instruction if $*) bit is clear Test 'b' bit of the register f and s,ip the ne(t instruction if $*) bit is set Cecrement f and copy the result to 3 or !A s,ip the ne(t $*) instruction if the result is Eero Increment f and copy the result to 3 or !A s,ip the ne(t $*) instruction if the result is Eero #o to the instruction ith the label JlabelJ ) #o to the subroutine JlabelJ' push the Program Counter ) in the stac, 6eturn from the subroutine' P+P the Program Counter ) from the stac, 6etrun from the subroutine' P+P the Program Counter ) from the stac,A put , in ! Cescription
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retie clr dt sleep nop Encoding o) instruction:

6eturn from Interrupt .ervice 6outine and re-enable interrupt Clear !atch Cog Timer #o into sleep* stand by mode Go operation

) $ $ $

9s has been discussed' each instruction is of $:-bit long. These $:-bits contain both op-code and the operand. .ome e(amples of instruction encoding are sho n here. Example-1: -c) )8 +perands7 5ncoding7 Clear 'b' bit of register 'f' & K f K $)2 &KbK2

The instruction is e(ecuted in one instruction cycle' i.e.' : cloc, cycles. The activities in various cloc, cycles are as follo s.

Example-2: goto 9 +perand7 #o to label ',' instruction & K D K )&:2 =$$-bit address is specified> +peration7 PCB9T8 L:7<M PC L$)7$$M 5ncoding7 D PC L$&7&M

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.ince this instruction requires modification of program Counter' it ta,es t o instruction cycles for e(ecution. N-Cycle activities are sho n as follo s.

I.O Port Con)iguration #iscussion on I.O 3orts o) PIC+0C6,A: PIC$1C2:9 has five I*+ ports. Port-?' Port-C and Port-C have 8 pins each. Port-9 and Port-5 have 1 and < pins respectively. 5ach port has bidirectional digital I*+ capability. In addition' these I*+ ports are multiple(ed ith alternate functions for the peripheral devices on the microcontroller. In general' hen a peripheral is enabled' that pin may not be used as a general purpose I*+ pin. 5ach port latch has a corresponding T6I. =Tri-state 5nable> register for configuring the port either as an input or as an output. The port pins are designated by the alphabet 6' follo ed by the respective port =viE. 9' ?' C' C or 5> and the pin number. 3or e(ample' Port-9 pins are named as 69&' 69$' etc. Port-A Port-9 pins 69&-69< and 69/ are similar. These pins function =alternate function> as analog inputs to the analog-to-digital converter.

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3ig :.$$ 69&-69< and 69/ pin of Port-9 The structure of Port-9 pins 69&-69< and 69/ is sho n in the figure. T6I.9 register decides hether the port-pin is configured as an input or as an output =digital> pin. .etting a T6I.9 register bit puts the corresponding output driver in high impedance mode. In this mode' the pin can be used as a digital or analog input. Clearing a bit in the T6I.9 register puts the contents of the data latch on the selected pins' i.e.' the pin functions as a digital output. Pins 69&-69 and 69/ have current sourcing capability of )/m9. The alternate function of 69: pin is Timer-& cloc, input =T&CDI>. 69: pin is an open drain pin and hence requires e(ternal pull-up hen configured as output pin. It is sho n in the follo ing figure.

3ig :.$) 69: pin Configuration Configuration of Port-9 pins Example 7 .et 69&-69< as outputs and 69: - 69/ as inputs. bcf .T9T".' 6P& A clrf P+6T9 A .elect ?an,-& Clears the data latch
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bsf .T9T".' 6P& A movl <&8 A mov f T6I.9 A Port-(

.elect ?an,-$ ! &<8 = data direction > .et 69&-69< as outputs' 69:-69/ as inputs

Port-? is an 8-bit bidirectional I*+ port. The data direction in Port-? is controlled by T6I.? register. .etting a bit in T6I.? register puts the corresponding output in high impedance input mode. !hen a bit in T6I.? is made Eero' the corresponding pin in Port-? outputs the content of the latch =output mode>. 5ach port pin has a ea, internal pull-up that can be enabled by clearing bit of +PTI+G register =bit-2>. !hen a pin is configured in the output mode' the ea, pull-up is automatically turned off. Internal pull-up is used so that e can directly drive a device from the pins.

3ig :.$< Pins 6?&-6?< of Port-? Configuration of Port-? pins Example 7 .et 6?&-6?< as outputs' 6?:-6?/ as inputs' 6?2 as output.

bcf .T9T".' 6P& clrf P+6T? bsf .T9T".' 6P& movl 2&8 TIMER COMPARE AND CAPTURE MODE O*er*iew o) Ti er Modu&es7
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PIC $1C2:9 has three modules' viE.' Timer-&' Timer-$ and Timer-). Timer-& and Timer-) are 8-bit timers. Timer-$ is a $1-bit timer. 5ach timer module can generate an interrupt on timer overflo . Ti er-: O*er*iew: The timer-& module is a simple 8-bit "P counter. The cloc, source can be either the internal cloc, =f osc * :> or an e(ternal cloc,. !hen the cloc, source is e(ternal' the Timer-& module can be programmed to increment on either the rising or falling cloc, edge. Timer-& module has a programmable pre-scalar option. This pre-scalar can be assigned either to Timer-& or the !atch dog timer' but not to both. The Timer-& Counter sets a flag T&I3 =Timer-& Interrupt 3lag> hen it overflo s and can cause an interrupt at that time if that interrupt source has been enabled' =T&I5 4 $>' i.e.' timer-& interrupt enable bit 4 $. OPTION Register Con)iguration7 +ption 6egister =9ddr7 8$8> Controls the pre-scalar and Timer -& cloc, source. The follo ing +PTI+G register configuration is for cloc, source 4 fosc *: and no !atchdog timer.

Ti er-: use without 3re-sca&ar Internal cloc, source of f P+6T9>.

osc

*:. =5(ternal cloc, source' if selected' can be applied at 69:*T+CDI input at

The follo ing diagram sho s the timer use ithout the pre-scalar.

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3ig:.$: Timer - & operation ithout pre-scalar Ti er-: use with 3re-sca&ar: The pre-scalar can be used either ith the Timer-& module or ith the !atchdog timer. The pre-scalar

is available for Timer-& if the pre-scalar assignment bit P.9 in the +PTI+G register is &. Pre-scalar is a programmable divide by n counter that divides the available cloc, by a pre-specified number before applying to the Timer-& counter.

3ig :.$/ Timer - & ith pre-scalar

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Ti er - + Modu&e Timer $ module is a $1-bit timer*counter consisting of t o 8-bit registers =TM6$8 and TM6$B> hich are readable and ritable. The TM6$ register pair =TM6$87TM6$B> increments from &&&&8 to 33338 and rolls over to &&&&8. The TM6$ interrupt' if enabled' is generated on overflo ' hich sets the interrupt flag bit TM6$I3 =bit-& of PI6$ register>. This interrupt can be enabled*disabled by setting*clearing TM6$ interrupt enable bit TM6$I5 =bit-& of the PI5$ register>. The operating and control modes of Timer$ are determined by the special purpose register T$C+G. @arious bits of T$C+G register are given as follo s7-

3ig :.$1 T$C+G 6egister TM6$ +G7 Timer$ +G bit & 4 stops Timer $A $ 4 5nables Timer $ TM6$C. 7 $ 4 5(ternal Cloc, =6C+*T$+.+*T$CDI> & 4 Internal Cloc, = =@alid if TM6$C. 4 $> $ - Co not synchroniEe & - .ynchroniEe T$+.C5G7 > 7 Timer $ Cloc, source .elect ?it

Timer $ 5(ternal Cloc, Input .ynchroniEation ?it

+scillator enable control bit $ 4 +scillator is enabled & 4 +scillator is shut off

Timer $ Input Cloc, Pre-scalar Se&ect -its Pre-sca&ar Va&ue T+C9PS+ T+C9PS:
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$ $ & &

$ & $ &

$78 $7: $7) $7$

3ig :.$2 Timer $ can operate in one of the t o modes

+peration of Timer $

9s a timer =TM6$C. 4 &>. In the timer mode' Timer $ increments in every instruction cycle. The timer $ cloc, source is . .ince the internal cloc, is selected' the timer is al ays synchroniEed and there is no further need of synchroniEation. 9s a counter =TM6$C. 4 $>. In the counter mode' e(ternal cloc, input from the pin 6C+*T$CDI is selected.

Reading and writing Ti er + 6eading TM6$8 and TM6$B from Timer $' hen it is running from an e(ternal cloc, source' have to be done ith care. 6eading TM6$8 or TM6$B for independent 8 - bit values does not pose any problem. !hen the $1-bit value of the Timer is required' the high byte =TM6$8> is read first follo ed by the lo byte =T86$lB>. It should be ensured that TM6$B does not overflo =that is goes from 338 to &&8> since T86$8 as read. This condition is verified by reading TM6$8 once again and comparing ith previous value of TM6$8. E;a 3&e Progra 6eading $1bit of free running Timer $ movf TM6$8 mov f TMP8 movf TM6$B mov f TMPB A A A A read high byte store in TMP8 read lo byte store in TMPB
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movf TM6$8' ! A read high byte in ! sub f TMP8' ! A subtract $ st read ith ) nd read btfsc .T9T".' F A and chec, for equality goto ne(t A A if the high bytes differ' then there is an overflo A read the high byte again follo ed by the lo byte movf TM6$8' ! A read high byte mov f TMP8 movf TM6$B' ! A read lo byte mov f TMPB ne(t 7 nop Ti er 2 O*er*iew

3ig :.$8 .chematic diagram sho ing operation of Timer ) Timer ) is an 8 - bit timer ith a pre-scalar and a post-scalar. It can be used as the P!M time base for P!M mode of capture compare P!M =CCP> modules. The TM6) register is readable and ritable and is cleared on device reset. The input cloc, = fosc*:> has a pre-scalar option of $7$' $7: or $7$1 hich is selected by bit & and bit $ of T)C+G register respectively. The Timer ) module has an 8bit period register =P6)>. Timer-) increments from &&8 until it is equal to P6) and then resets to &&8 on the ne(t cloc, cycle. P6) is a readable and ritable register. P6) is initialiEed to 338 on reset. The output of TM6) goes through a :bit post-scalar =$7$' $7)' to $7$1> to generate a TM6) interrupt by setting TM6)I3.

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3ig :.$% The T)C+G 6egister Interru3t Logic in PIC +0C6,A

3ig :. )& .chematic diagram sho ing the interrupt logic for PIC PIC $1C2:9 microcontroller has one vectored interrupt location =i.e.' &&&:8> but has $) interrupt sources. There is no interrupt priority. +nly one interrupt is served at a time. 8o ever interrupts can be mas,ed. CCP Modu&es Ca3ture . Co 3are .P1M $CCP' Modu&es: PIC$1C2:9 has t o CCP Modules. 5ach CCP module contains a $1 bit register =t o 8-bit registers> and can operate in one of the three modes' viE.' $1-bit capture' $1-bit compare' or up to $&-bit Pulse !idth Modulation =P!M>. The details of the t o modules =CCP$ and CCP)> are given as follo s. CCP+ Modu&e:
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CCP$ Module consists of t o 8-bit registers' viE.' CCP6$B =lo CCP$C+G register controls the operation of CCP$ Module. CCP2 Modu&e: CCP) Module consists of t o 8 bit registers' viE.' CCP6)B =Bo CCP$C+G register controls the operation of CCP) Module. ?oth CCP$ and CCP) modules are identical in operation trigger.

byte> and CCP6$8 =high byte>. The

byte> and CCP6)8 =high byte>. The

ith the e(ception of the operation of special event

The follo ing table sho s the timer resources for the CCP Mode. CCP Mode Capture Compare P!M Timer "sed Timer $ Timer $ Timer )

CCP$C+G 6egister =9ddress $28 > CCP)C+G 6egister is e(actly similar to CCP$C+G register. CCP)C+G 6egister address is $C8. CCP$C+G controls CCP module$ here as CCP)C+G controls CCP Module).

?it /-:7 CCP$0 CCP$O7 P!M least significant bits. These bits are of no use in Capture mode. In P!M Mode' these bits are the t o B.?s of the P!M duty cycle. The eight M.?s are found in CCP6$B. Thus the P!M mode operates in $&-bit mode. CCP$0 CCP$O7 P!M least significant bits. These bits are of no use in Capture mode. In P!M Mode' these bits are the t o B.?s of the P!M duty cycle. The eight M.?s are found in CCP6$B. Thus the P!M mode operates in $&-bit mode. ?it <-&7 CCP$M<7CCP$M+ =CCP$ Mode select bits> &&&&4Capture*Compare*P!M Mode off &$&&4Capture mode' every falling edge &$&$4Capture mode' every rising edge
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&$$&4Capture mode' every : th rising edge &$$$4Capture mode' every $1 th rising edge $&&&4Compare mode' set output on match =CCP$I3 bit is set> $&&$4Compare mode' clear output on match =CCP$I3 bit is set> $&$&4Compare mode' generate soft are interrupt on match =CCP$I3 bit is set' CCP$ pin unaffected> $&$$4Compare mode' trigger special event =CCP$I3 bit is setACCP$ resets Tmr$A CCP) resets TM6$ and starts 9*C conversion if 9*C module is 5nabled> $$004P!M mode. CAPTURE MO#E $CCP+': Capture Mode captures the $1-bit value of TM6$ into CCP6$87CCP6$B register pair in response to an event occurring on 6C)*CCP$ pin. Capture Mode for CCP) is e(actly similar to that of CCP$. 9n event on 6C)*CCP$ pin is defined as follo s7

5very falling edge 5very rising edge. 5very : th rising edge. 5very $1 th rising edge.

9s mentioned earlier' this event is decided by bit <-& of CCP$C+G register.

3ig :.)$ Capture operation 6equired condition for capture mode7 $. 6C)*CCP$ pin should be configured as an input by setting T6I.C =bit )>. ). Timer $ should be operated from the internal cloc, =fosc*:>' i.e.' timer mode or in synchroniEed counter mode. Co 3are Mode $CCP+'
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Compare mode for CCP) is similar to that of CCP$' e(cept that in special event trigger mode' CCP$ resets TM6$ only' hereas CCP) resets TM6$ and starts 9*C conversion if 9*C module is enabled. In compare mode' the $1-bit CCP6$ register value is compared against TM6$ register pair =TM6$8 and TM6$B> value. !hen a match occurs' the 6C)*CCP$ pin is driven high or driven lo or remains unchanged as decided by CCP$C+GL<7&M bits.

3ig :.)) Compare +peration Re<uired conditions )or co 3are ode $. 6C)*CCP$ pin must be configured as an output by clearing T6I.CL)M bit. ). Timer-$ should be operated in timer mode =i.e.' internal cloc, source of fosc*:> or in synchroniEed counter mode. In soft are interrupt mode' CCP$I3 bit is set but CCP$ pin in unaffected. 9s sho n in the figure' in special event trigger mode' both CCP$ and CCP) initiates an 9*C conversion. P!M mode =CCP$> ?oth CCP$ and CCP) have similar operation in P!M mode. 8ere e ill discuss P!M ith respect to CCP$. In P!M mode' the CCP$ pin produces up to a $&-bit resolution Pulse !idth Modulation =P!M> output. 6C)*CCP$ pin should be configured in the output mode by clearing T6I.CL)M bit. The schematic bloc, diagram of CCP$ module in P!M mode is sho n in the figure.

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3ig :.)< P!M +peration It can be noted that P6) =Period 6egister' 8 bit> decides the P!M period here CCP6$B =8-bits> and

CCP$C+G L/7:M =)-bits> decide the P!M duty cycle. !hen TM6) equals P6)' the .6 latch is set and 6C)*CCP$ pin is pulled high. In the same time' TM6) is cleared and the duty cycle value available in CCP6$B is latched to CCP6$8. CCP6$8' CCP$C+G L/7:M decide the duty cycle and equals the TM6)I) pre-scalar or N-bits' the .6 latch is set and 6C)*CCP$ pin is driven lo . hen this $&-bit

WATCH DOG TIMER:

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R(PU - PORT( Pu&&-u3 ena-&e -it o $ - P+6T? pull-up resistors are disabledA and
o

& - P+6T? pins can be connected to pull-up resistors.

INTE#7 - Interru3t Edge Se&ect -it

o o

$ - Interrupt on rising edge of IGT pin =&-$>A and & - Interrupt on falling edge of IGT pin =$-&>.

T:CS - TMR: C&oc4 Se&ect -it

o o

$ - Pulses are brought to TM6& timer*counter input through the 69: pinA and & - Internal cycle cloc, =3osc*:>.

T:SE - TMR: Source Edge Se&ect -it

o o

$ - Increment on high-to-lo transition on TM6& pinA and & - Increment on lo -to-high transition on TM6& pin.

PSA = Pre-sca&ar Assign ent -it

o o

$ P Pre-scalar is assigned to the !CTA and & P Pre-scalar is assigned to the TM6& timer*counter.
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PS28 PS+8 PS: = Pre-sca&ar Rate Se&ect -it

o

Pre-scalar rate is ad;usted by combining these bits 9s seen in the table :-$' the same combination of bits gives different pre-scalar rate for the timer*counter and atch-dog timer respectively.

To se&ect

ode:

Timer mode is selected by the T&C. bit of the +PTI+GH65# register' =T&C.7 &4timer' $4counter>A !hen used' the pre-scalar should be assigned to the timer*counter by clearing the P.9 bit of the +PTI+GH65# register. The pre-scalar rate is set by using the P.)-P.& bits of the same registerA and

!hen using interrupt' the #I5 and TM6&I5 bits of the IGTC+G register should be set. easure ti e:

To

6eset the TM6& register or rite some ell-,no n value to itA 5lapsed time =in microseconds and hen using quartE :M8E> is measured by reading the TM6& registerA

The flag bit TM6&I3 of the IGTC+G register is automatically set every time the TM6& register overflo s. If enabled' an interrupt occurs.

To count 3u&ses:

The polarity of pulses are to be counted is selected on the 69: pin are selected by the T+.5 bit of the +PTI+G register =T&.57 &4positive' $4negative pulses>A and Gumber of pulses may be read from the TM6& register. The pre-scalar and interrupt are used in the same manner as in timer mode.

SYNCHRONOUS SERIAL PORT Most of mid range PIC microcontrollers include a .ynchronous .erial Port =..P> Module. The discussion in this section is relevant to PIC$1C2:9 only. ..P Module section can be configured in either of the follo ing t o modes.

.erial Peripheral Interface =.PI> Inter Integrated Circuit =I)C>

5ither of these modes can be used to interconnect t o or more PIC chips to each other using a minimal number of ires for communication. 9lternatively' either can be used to connect a PIC microcontroller to a
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peripheral chip. !hen I )C mode is selected' the peripheral chip must also have an I )C interface. +n the other hand' the .PI mode provides the cloc, and serial data lines for direct connection to shift registers. This leads to increased I*+ interface capability and an arbitrary number of I*+ devices can be connected to a PIC microcontroller. .PI can also achieve data rate significantly higher than I)C. ?oth the communication methods are synchronous' i.e.' the data transfer is synchroniEed ith an e(plicit cloc, signal. T o special purpose registers control the synchronous serial port =..P> operations. These registers are7

..PC+G =.ynchronous .erial Port Control 6egister>' 9ddress7 $:8 ..P.T9T=.ynchronous .erial Port status 6egister>' 9ddress7 %:8

Seria& Peri3hera& Inter)ace $SPI' Port-C three pins' viE.' 6C/*.C+' 6C:*.CI and 6C<*.CD*.CB are mainly used for .PI mode. In addition' one Port-9 pin' viE.' 69/* *9G: is used for slave select. The schematic bloc, diagram of .PI is sho n in the figure

3ig :.): .chematic diagram under .PI Mode The .PI port requires 6C<*.CD pin to be an output that generates the cloc, signal used by the e(ternal shift registers. !hen .PI is configured in the slave mode' 6C<*.CD pin or,s as the input for the cloc,. !hen a byte is ritten to ..P?"3 register' it is shifted out of 6C/*.C+ pin in synchronous rite to ..P?"3 also initiates the 8 bit data reception into ..P?"3 of ith the hatever

emitted cloc, pulses on 6C<*.CD pin. The M.? of ..P?"3 is the first bit to appear on 6C/*.C+ pin. .imultaneously' the same appears on 6C:*.CI pin at the time of rising edges of the cloc, on .CD pin. 8ence shifting-in and shifting-out of data occur simultaneously.

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3ig :.)/ .PI Master * .lave Connection The schematic diagram of .PI Master*.lave connection is sho n in the figure. Ti ing diagra )or data trans)er in >Master ode>7

..PI3 interrupt flag is cleared by the user soft are if already in the set mode. The interrupt is enabled. 9ny rite to ..P?"3 initiates the data transfer' i.e.' transmission and reception. The cloc, pulses =8 cloc, pulses> are output through .CD pin. The data is received through .CI. !hen CDP4$ =..PC+GL:M>' data changes at .C+ at negative cloc, transition and is read through .CI at positive cloc, transition. The idle state of cloc, is high. If CDP4&' data appears at .C+ at positive cloc, transition and is read through .CI at negative cloc, transition. The idle state of the cloc, is lo . These are sho n in the follo ing diagrams.

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=i> Timing diagram for CDP4$

=ii> Timing diagram for CDP4& 3ig :.)1 Timing Ciagram under .PI mode

SERIAL PERIPHERAL INTERFACE

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I.O Port E;3ansion using Seria& Peri3hera& Inter)ace $SPI' Though .PI is a serial communication interface' it can be used to realiEe multiple output parallel ports and multiple input parallel ports. !e separately. Parallel +utput Port 6ealiEation 9 parallel 8-bit output port can be realiEed through .PI ith the help of a shift register chip =2:8C/%/> as sho n in 3ig )/.$. 6C/*.C& pin outputs serial data register data to the output pins of the shift register. 8ence 6C: is configured as an output pin. hile 6C<*.CD in outputs the serial cloc,. .ince input data transfer is not required' port pin 6C:*.CI is used to latch the shift ill consider this realiEation of an output parallel port and an input port

3ig :.)2 PIC connection =in .PI mode> !hen an 8-bit data is

ith a shift register

ritten to ..P?"3' the data is shifted out of 6C/*.C& pin. !ith CDP 4 $' the

data is stable at the positive transition but changes at the negative transition. The shift shifts the data at the positive cloc, transition. 9fter 8 cloc, pulses' all 8-bits are shifted in the shift register. The completion of data transfer is indicated by ..PI3 interrupt flag becoming ' $' . The interrupt service routine ma,e 6C: ' $' ' thus latching the 8-bit data to the output of the shift register. The configuration of various registers are sho n in 3ig :.)8

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Port con)igurations

3ig :.)8 @arious 6egister Configurations Para&&e& In3ut Port Rea&i"ation 9 shift register =2:8C$1/> is connected to the PIC microcontroller as sho n in 3ig :.)%. Pin 6C2 is configured as an output and is used to load 8-bit data to the shift register. 9 dummy rite to ..P?"3 initiates data transfer. Cata bit is read into 6C:*.CI at the negative cloc, transition =CDP 4 &> here the data bit is stable. Cata is shifted in the shift register at the position cloc, transition as sho n in the timing diagram. 9fter the completion of data transfer' ..PI3 interrupt flag goes high. Thereafter the 8-bit data can be read by reading ..P?"3.

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3ig :.)% 6ealiEation of an 8-bit parallel input port ith PIC in .PI mode. Port con)igurations 3ig :.<& gives the configurations various registers for inputs parallel port realiEation.

3ig :.<& Configurations of various registers for parallel input port

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I2C BUS OPERATION . I )C stands for Inter-Integrated circuit. I )C communication is a t o connecting one or more master processors =.erial Cloc,>. The reason for open drain connection is that the data transfer is bi-directional and any of the devices connected to the I )C bus can drive the data line =.C9>. The serial cloc, line =.CB> is usually driven by the master. .ince .C9 and .CB pins are open drain pins' e(ternal pull-up resistances are required for operation of I )C bus. 9 typical I)C bus sho ing the connection of multi-master and multi-slave configuration is sho n in the follo ing figure. ire bi-directional interface for

ith one or more slave devices' such as an 55P6+M' 9CC' 69M'

BCC display' C9C' etc. I )C interface requires t o open drain I*+ pins' viE. .C9 =.erial Cata> and .CB

3ig :.<$ Multimaster Multislave Connection .ome conventions are follo ed in I)C communication. Bet us assume that there is one master and one slave and 8-data bits are sent. !e ill initially assume that the master is the transmitter and the slave is the =&>. The follo ing diagram sho s the data receiver. The cloc, is driven by the master. +n receiving 8-bits' an ac,no ledgement bit is driven by the receiver on .C9 line. The ac,no ledgement bit is usually Bo communication pattern having 8 data bits and one ac,no ledgement bit.

3ig :.<) Timing diagram for data transfer The follo ing features are to be noted $. .C9 line transmits* receives data bits. M.? is sent first.
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). Cata in .C9 line is stable during cloc, =.CB> high. 9 ne transition after a specified hold time. <. .erial cloc, =.CB> is driven by the master.

bit is initiated at the negative cloc,

:. 9n ac,no ledgement bit =&> is driven by the receiver after the end of reception. If the receiver does not ac,no ledge' .C9 line remains high =$>. I)C bus transfer consists of a number of byte transfers .T96T condition or a .T+P condition. Curing the idle state it pulls .C9 lo processor ithin a .T96T condition and either another hen no data transfer is ta,ing place' both .C9 hen the

and .CB lines are released by all the devices and remains high. !hen a master ants to initiate a data transfer' follo ed by .CB being pulled lo . This is called .T96T condition. .imilarly' ants to terminate the data transfer it first releases .CB =.CB becomes high> and then .C9. This is

called a .T+P condition. .T96T and .T+P conditions are sho n in the diagram as follo s.

3ig :.<< Timing diagram for .T96T and .T+P Conditions .T96T and .T+P conditions are unique and they never happen ithin a data transfer. #ata Co unication Protoco&: ith a single master. .imilarly' in $&-bit addressing mode' $&): slaves can be ill discuss here 2-bit addressing mode only. $&-bit addressing mode is similar

In I)C communication both 2-bit and $&-bit slave addressing are possible. In 2-bit addressing mode $)8 slaves can be interfaced interfaced ith the master. !e

to 2-bit addressing e(cept from the fact that the number of address bits is more. 3ollo ing a 'start' condition' the master sends a 2-bit address of the slave on .C9 line. The M.? is sent first. 9fter sending 2-bit address of the slave peripheral' a 6* '&'' the follo ing byte =after the ac,no ledgement bit> is master.
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=8th bit> bit is sent by the master. If 6*

bit is

ritten by the master to the addressed slave

peripheral. If 6* 4$' the follo ing byte =after the ac,no ledgement bit> has to be read from the slave by the

9fter sending the 2-bit address of the slave' the master sends the address =usually 8 bit> of the internal register of the slave herefrom the data has to be read or ritten to. The subsequent access is automatically directed to the ne(t address of the internal register. The follo ing diagrams give the general format to registers. rite and read from several peripheral internal

3ig :.<: Cata transfer protocol for riting to a slave device 6* 6* =6ead * !rite> bit indicates hether the data is to be ritten by the master or read by the master. If 4 &' the subsequent data are to be ritten by

is $' the subsequent data are to be read by the master. If 6*

the master to the addressed slave. It has to be noted that the slave address is sent first' follo ing a 'start' condition. The addressed slave responds by ac,no ledging and gets ready for data transfer. If data has to be read from a specific address of the slave device' the master sends the 2-bit address of the slave first follo ing a 'start' condition. 6* bit is sent as 'lo '. The addressed slave ac,no ledges by pulling the 9CD line lo . The hich data has to be read. The slave ith 6* 4 $. The slave bit as initially &' the master is in the rite mode. To change this to read mode' the master then sends the 8-bit internal address of the slave from ac,no ledges. .ince 6*

'start' condition is again generated follo ed by 2-bit address of the slave ac,no ledges by pulling 9CD bit lo . The data transfer stops reception and a 'stop' condition is generated.

ac,no ledges. The slave then sends data from previously specified internal address to the master. The master hen the master does not ac,no ledge the data

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131

UNIT V MICROCONTROLLER (ASE# S?STEMS #ESI7N LCD INTERFACING There are basically t o types of BCCs as far as the interfacing technique is concerned7 parallel BCCs and serial BCCs. Parallel BCCs =e.g. 8itachi 8C::28& series> are connected to the microcontroller circuitry such that the data is transferred to the BCC unit using more than one data line' and four or eight data lines are very common. .erial BCCs are connected to a microcontroller using only one data line and data is usually transferred to the BCC using the standard 6.-)<) asynchronous data communication protocol. .erial BCCs are much easier to usebut they usually cost more than the parallel ones. Parallel BCCs are used in the temperature pro;ects in this boo, to sho the value of the measured temperature. The programming of a parallel BCC is usually a comple( tas, and requires a good understanding of the internal operation of the BCCs' including the timing diagrams. 3ortunately' 35C C language provides special commands for displaying data on 8C::28& type parallel BCCs. 9ll the user has to do is connect the BCC to the appropriate I*+ ports of the microcontroller and then use these special commands to simply send data to the BCC. 5#,,6/: LC# odu&e

8C::28& is one of the most popular BCC modules used in industry and also by hobbyists. This module is monochrome and comes in different shapes and siEes. Modules ith line lengths of 8' $1' )&' ):' <)' and :& characters can be selected. Cepending upon the model chosen' the display idth can be selected as $' )' or : lines. The display provides a $:-pin connector to interface to the e(ternal orld.

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. @ss is the & @ supply or ground. The @CC pin should be connected to the positive supply. 9lthough the manufacturers specify a / @ d.c. supply' the modules illusually or, ith as lo as < @ or as high as 1 @. Pin < is named as @55 and this is the contrast control pin. This pin is used to ad;ust the contrast of the device and it should be connected to a variable voltage supply. 9 potentiometer is usually connected bet een the po er supply lines ith its iper arm connected to this pin so that the contrast can be ad;usted. This pin can be connected to ground for most applications. Pin : is the 6egister .elect =6.> and hen this pin is B+!' data transferred to the display is treated as

commands. !hen 6. is 8I#8' character data can be transferred to and from the module. Pin / is the 6ead*!rite =6*!> line. This pin is pulled B+! in order to module. rite commands or character

data to the BCC module. !hen this pin is 8I#8' character data or status information can be read from the

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Pin 1 is the 5nable =5> pin

hich is used to initiate the transfer of commands or data bet een the riting to the display' data is transferred only on the 8I#8 to B+!

module and the microcontroller. !hen

transition of this line. !hen reading from the display' data becomes available after the B+! to 8I#8 transition of the enable pin and this data remains valid as long as the enable pin is at logic 8I#8. Pins 2 to $: are the eight data bus lines =C+ to C2>. Cata can be transferred bet een the microcontroller and the BCC unit using either a single 8-bit byte' or as t o :-bit nibbles. In the latter case' only the upper four data lines =C: to C2> are used. The :-bit mode has the advantage that fe er I*+ lines are required to communicate ith the BCC. Connecting the LC# to the connections are as follo s7 LC# 6. 6*! 5 C: C/ C1 C2 odu&e Port ( 3ins ?$ ?) ?< ?: ?/ ?1 ?2 icrocontro&&er The BCC module is assumed by default to be connected to Port ? of a PIC microcontroller. The pin

134

The functions used to send data and control to the BCC module are LCD and LCDString. 3unction BCC sends a control function to the module as given belo 7 LC# state ent %unction BCC=-$> InitialiEe the display to $ line BCC=-)> InitialiEe the display to ) lines BCC=)/2> Clear display and home the cursor BCC=)/8> 6eturn the cursor to home position BCC=)/1I$)8IG> 6eturn cursor to position G on line $' here G 4 & is the first character position on line $ BCC=)/1I$%)IG> 6eturn cursor to position G on line )' here G 4 & is the first character position on line )

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ANALOG TO DIGITAL CONVERTER There are numerous ays in hich an analog signal can be converted to digital form. The 9nalog to Cigital convertors can be classified into t o general groups based on the conversion technique. +ne technique involves comparing a given analog signal ith the internally generated equivalent signal. This group includes successive appro(imation' counter' and flash-type converters. The second technique involves changing an analog signal into time or frequency and comparing these ne parameters against ,no n values. Thus group includes integrator converters and @oltage to 3requency converters. The trade-off bet een the t o techniques is based on accuracy @s speed. The successive appro(imation and the flash type are faster but generally less accurate than the integrating and the @oltage to 3requency converters. 3urthermore' the flash type is e(pensive and difficult to design for high accuracy. The most commonly used 9*C converters are successive appro(imation and integrating type 9*C converters. The successive appro(imation 9*C converters are used in applications such as data loggers and instrumentation' here conversion speed is important. +n the other hand' integrating type converters are used in applications such as digital meters' panel meters and monitoring systems' here the conversion accuracy is critical.

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SUCCESSIVE APPRO@IMATION A.# CONVERTERS:

3igure sho s the bloc, diagram of a successive appro(imation 9*C converter. The ma;or elements of this converter are a C*9 converter' the successive appro(imation =.96> and the comparator. 8ere the output of C*9 converter is compared the equivalent digital signal. 3irst bit C< is turned +G and the output of the C9C is compared ith an analog signal. If the ith the measured voltage. The digital input to the C9C is generated using successive appro(imation method. !hen the C9C output matches the analog signal' the input to the C9C is

comparator changes state' indicating that the output generated by C< is larger than the analog signal' bit C< is turned +33 in the .96 and bit C) is turned +G. The process continues until the input reaches bit C&. SUCCESSIVE APPRO@IMATION TEC5NIAUE: .uccessive appro(imation process can be shed through either soft are or hard are approach. In soft are approach' an 9*C converter is designed using 9*C converter and the microprocessor plays the role of the comparator and the .96. ?loc, diagram for successive appro(imation 9CC is sho n in 3ig.

137