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EE/APR 2010/ECE590/KJE609/416
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INSTRUCTIONS TO CANDIDATES 1. 2. 3. This question paper consists of five (5) questions. Answer ALL questions in the Answer Booklet. Start each answer on a new page. Do not bring any material into the examination room unless permission is given by the invigilator. Please check to make sure that this examination pack consists of: i) ii) iii) the Question Paper a six - page Appendix 1 (MC68000 CPU instruction set) an Answer Booklet - provided by the Faculty
4.
CONFIDENTIAL QUESTION 1 a)
EE/APR 2010/ECE590/KJE609/416
Refer to the circuit in Figure Q1 a. If the diode is made of Germanium, calculate: i) ii) iii) the current \1. the power dissipated in the 4.7kQ and 1.5kQ resistors. the output voltage, V0.
AA/V
4.7kQ
15V1.5kCL
V0
Figure Q1a (8 marks) b) Refer to the circuit in Figure Q1b. i) ii) iii) Calculate the secondary root mean square voltage, V2rmsSketch the waveform of output voltage, V0. Hence calculate the average voltage, If a 500uF capacitor is connected in parallel with the load, sketch the new waveform of V0. Hence calculate the ripple voltage, Vr.
220 V1rms 50 Hz
*i
'2rms
-o + 1.5k
CONFIDENTIAL
CONFIDENTIAL QUESTION 2
EE/APR 2010/ECE590/KJE609/416
+o
1
Zo Figure Q2
Vin
a)
Referring to Figure Q2, determine the following: i) ii) iii) iv) v) vi) base current, l B collector current, l c emitter current, l E base voltage, VB VCE voltage drop at R E i, VRE1 (10 marks)
b)
Referring to Figure Q2 and given V B E=0.7V, perform AC analysis by drawing the AC equivalent circuit and determine the following: ) i) ii) v) v) re input impedance, Zin output impedance, Z0 voltage gain, A v current gain, Aj (10 marks)
CONFIDENTIAL
CONFIDENTIAL QUESTION 3 a)
EE/APR 2010/ECE590/KJE609/416
Referring to Figure Q3a, a bipolar junction transistor (BJT) is used to switch a motor on and off in response to switch Si closing and opening. The BJT is specified with (3=100. i) ii) iii) Calculate the base current for both on and off condition. Calculate the voltage between collector and emitter terminal when switched on. Calculate the power dissipated in the load and the BJT when switched on.
RL i.5kcr
V^wvr
RB
20V
5V
5.6kQ
Figure Q3a (12 marks) b) Convert the following numbers into the required number system. i) ii) iii) 73.0312510 to binary numbering system, 777.716 to decimal numbering system, 10101.0112 to decimal numbering system. (8 marks)
CONFIDENTIAL
CONFIDENTIAL QUESTION 4 a)
EE/APR 2010/ECE590/KJE609/416
b)
Obtain the Boolean expression of A and B for the combinational logic circuit in Figure Q4b below. W-
xY
J>
^ > \ >
Figure Q4b
o-
(6 marks) c) Construct the Karnaugh map for function F(x,y,z) = 1(1,4,5,6). Write the algebraic expression for the minimized function. Hence, draw the circuit diagram that implements the function with logic gates. (10 marks)
QUESTION 5 a) With reference to MC68000 processor, briefly describe the difference between address register and data register in terms of data size and function. (4 marks) b) Indicate the changes in the associated register(s) and memory location(s) after executing each of the following instructions. Use the initial values given in Table Q5b, for each operation.
CONFIDENTIAL
CONFIDENTIAL
EE/APR 2010/ECE590/KJE609/416
Contents $2342A1B3 $000000B3 $0010FFF5 $2002 $2006 $A9 $F2 $43 $54 $D6 $E5 $C3 $98
Data registers: D1 D2 D3 Address registers: A1 A3 Memory locations: $2000 $2001 $2002 $2003 $2004 $2005 $2006 $2007 i) ii) iii) iv) ROL.W #4, D1 AND.B #$33, D3 MOVE.W (A3), D3 SUB.B (A1), D2 (6 marks)
c)
Figure Q5c shows the MC68230 Pl/T connection to LED and switches. Draw the flowchart and write a MC68000 CPU assembly language program that will turn ON LED1, when switch SW1 is pressed and turn ON LED2 when switch SW2 is pressed. Otherwise, both LEDs will be turned OFF.
CONFIDENTIAL
CONFIDENTIAL
EE/APR 2010/ECE590/KJE609/416
+5V
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APPENDIX 1 (1)
EE/APR 2010/ECE590/KJE609/416
Data Size
Condition
X N Z V
Syntax Dx, Dy -(Ax) ,-(Ay) Dn,<ea> <ea>,Dn <ea>,An #x,<ea> #<l-8>,<ea> Dy, Dx -(Ay),-(Ax) <ea>,Dn Dn,<ea> #<data>,<ea> #<l-8>,Dy Dx, Dy <ea>
U * U
ADD
ADD binary
BWL
* * * *
-k
-k
Bit-wise AND
BWL
BWL BWL
-k -k -k
ASR
Arithmetic Shift Right Conditional Branch Bcc.S <label> Bcc.W <label> Dn,<ea> #<data>,<ea>
BWL BW-
-k
BCHG
B-L
Test a Bit and CLeaR Test a Bit and SET Branch to SubRoutine BSR.S <label> BSR.W <label> Dn,<ea> #<data>,<ea> <ea>,Dn <ea> <ea>,Dn <ea>,An
BTST
Bit TeST
B-L
-W-
* U U
- 0 1 0
_ * * * _ * * * CONFIDENTIAL
CONFIDENTIAL
APPENDIX 1 (2)
EE/APR 2010/ECE590/KJE609/416
CMPI CMPM DBcc DIVS 0 DIVU 0 EOR 0 EORI 0 EXG EXT 0 ILLEGAL JMP JSR LEA LINK LSL
CoMPare Immediate CoMPare Memory Looping Instruction Divide Signed Divide Unsigned Exclusive OR Exclusive OR Immediate Exchange any two registers Sign EXTend on ILLEGAL-Instruction Exception JuMP to Affective Address Jump to SubRoutine Load Effective Address Allocate Stack Frame Logical Shift Left
#<data>,<ea> {Ay)+,(Ax)+ DBcc Dn,<label> <ea>,Dn <ea>,Dn Dn,<ea> #<data>,<ea> Rx,Ry Dn ILLEGAL <ea> <ea> <ea>,An An,#<displacement> Dx, Dy #<l-8>,Dy <ea>
-k
* * *
* * 0 * * 0
- * * 0 - - ~ - - - - - ~ -
- - ~ - - - -
BWL
* *
Logical Shift Right Between Effective Addresses; To CCR To SR <ea>,<ea> <ea>,CCR <ea>,SR
BWL BWL
- *
*r
* 0
- * * 0 I I I I I I I I
-w-W-
MOVE MOVE
-W--L
MOVEA MOVEM
MOVEP
MOVE Peripheral
MOVEQ 0
- * * 0 CONFIDENTIAL
CONFIDENTIAL
MULS 0 MULU 0 NBCD * NEG NEGX
k
APPENDIX 1 (3)
EE/APR 2010/ECE590/KJE609/416
<ea>,Dn <ea>,Dn <ea> <ea> <ea> NOP <ea> <ea>,Dn Dn,<ea> <data>,<ea> <ea> RESET #<l-8>,Dy Dx, Dy <ea> BWL
* * 0
MULtiply Signed MULtiply Unsigned Negate BCD NEGate NEGate with extend No OPeration Form one's complement Bit-wise OR
-W-
* * 0
U * U
* * * *
k k
-k -k
BWL BWL
* * o * * 0
Bit-wise OR with Immediate Push-Effective Address RESET all external devices ROtate Left
BWL L
_ * * 0
Rotate Right ROtate Left with extend ROtate Right with extend ReTurn from Exception ReTurn and Restore ReTurn from Subroutine Subtract BCD with extend RTE RTR RTS Dx, Dy -(Ax),-(Ay) <ea> #<data> Dn,<ea> <ea>,Dn <ea>,An #x,<ea> <data>,<ea> Dy, Dx
* * 0
* * * o
* * * Q
I I I I I I I I
B~
* u * u
Set to -1 if True, 0 if False Enable & wait for interrupts SUBtract binary
B I I I I BWL
* * * *
SUBtract binary from An SUBtract Immediate SUBtract 3-bit immediate SUBtract extended
-k
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APPENDIX 1 (4)
EE/APR 2010/ECE590/KJE609/416
SWAP words of Dn Test & Set MSB & Set N/Z-bits Execute TRAP Exception TRAPV Exception if V-bit Set TeST for negative or zero Deallocate Stack Frame
* * Q * * 0
Symbol * 0 1 U I
Meaning Set according to result of operation Not affected Cleared Set Outcome (state after operation) undefined Set by immediate data
Effective Address Operand Immediate data Assembler label TRAP instruction Exception vector (0-15) MOVEM instruction register specification list LINK instruction negative displacement Same as previous instruction
Addressing Modes Data Register Direct Address Register Direct Address Register Indirect Address Register Indirect with Post-Increment Address Register Indirect with Pre-Decrement Address Register Indirect with Displacement Address Register Indirect with Index Absolute Short Absolute Long Program Counter with Displacement Program Counter with Index Immediate Status Register Condition Code Register , Legend Dn An b w 1
Data Register Address Register 08-bit constant 16-bit constant 32-bit constant
(n i s (n i s
0-7) 0-7)
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CONFIDENTIAL
x Rx
APPENDIX 1 (5)
EE/APR 2010/ECE590/KJE609/416
8-, 16-, 32-bit constant Index Register Specification, one of: Dn.W Low 16 bits of Data Register Dn.L All 32 bits of Data Register An.W Low 16 bits of Address Register An.L All 32 bits of Address Register Condition Codes for Bcc, DBcc and Sec Instructions, Condition Codes set after CMP D0,D1 Instruction.
Unsigned CS LS EQ NE Carry Bit Set Lower or Same Equal (Z-bit Set) Not Equal (Z-bit Clear)
Signed LT LE EQ NE Less Than Less than or Equal Equal (Z-bit Set) Not Equal (Z-bit
PL - PLus (N-bit Clear) VC - V-bit Clear (No Overflow) (Overflow) RA - BRanch Always
DBcc Only
F - Never Terminate (DBRA is an alternate to DBF) T - Always Terminate SF - Never Set ST - Always Set
Sec Only
Partial MC68000 Pl/T registers Register General Control Register A Data Direction Register B Data Direction Register C Data Direction Register A Control Register B Control Register A Data Register B Data Register C Data Register Abbreviation PGCR PADDR PBDDR PCDDR PACR PBCR PADR PBDR PCDR
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APPENDIX 1 (6)
b5 MODE
H34
EE/APR 2010/ECE590/KJE609/416
b2
H3 H2 H1
b4
H12
b3
H4
j>
( P o r t s a n d bits individually programmable) (Ports A and B are together input or output) ( B a c h port input for r e a d a n d output for write) (Ports A and B are t o g e t h e r i n p u t for r e a d a n d o u t p u t for w r i t e )
01: Mode 1 i = > Unidirectional 16 bits 10: M o d e 2 i Bidirectional 8 bits 1 1: M o d e 3 i Bidirectional 16 bits
S U B M O D E
H2
C O N T R O L
H2 INT
H1
svo
Specifies H1 status
I
OO: S u b m o d e O Double-buffered input 01: Submode 1 Double-buffered output 1X: Bit I/O
OXX: H2
input
100: H2 output negated 101 : H2 output asserted 110: H2 handshake mode 11-1: H 2 p u l s e mode
CONFIDENTIAL