Building Blocks Architecture Design of the CPU

Design of a Simple Processor

CS1800: Discrete Structures J. Aslam H. Fell R. Rajaraman R. Sundaram

College of Computer & Information Science Northeastern University

Based on material from CMUs Great Theoretical Ideas course

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Outline

Building Blocks Architecture Components of the Processor Instruction Set Design of the CPU

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Building Blocks That We Have Already Seen

AND OR NOT

XOR

NAND

NOR

4-WAY 1-BIT MULTIPLEXER

4-WAY 1-BIT DEMULTIPLEXER

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Clocked Gates and Registers

Circuits using these basic gates are called combinational circuits.
No notion of time in computation: when inputs are xed, outputs are permanently determined.

We often need to regulate the ow the data; this is done using clocks. Using clocked gates, can build a register that stores values: if the set bit is 1 when the clock pulses, the output takes the input value, otherwise stays the same.

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Components of the Processor Instruction Set

Registers and Adder

Eight 32-bit registers R0 , R1 , . . . , R7 for holding data.

Useful to have the constant values 0 and 1 available. Set register R0 to hold 0 and R1 to hold 1, permanently.

256 16-bit registers P0 , P1 , . . . , P255 for holding a program. An 8-bit register PC that will serve as a program counter. A 32-bit adder.

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Components of the Processor Instruction Set

Registers and Adder, contd.

Input(Ri) Set(Ri) Ri

Output(Ri) A Input(PC) B 1 PC 32-BIT ADDER C A+B=C

Output(PC) Input(Pi) 0 Pi

Output(Pi)

Set bit for PC always 1 and set bit of program registers always 0. Set bits for the data registers determined by the instruction.
J. Aslam, H. Fell, R. Rajaraman, R. Sundaram Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Components of the Processor Instruction Set

Instruction Set

Four types of instructions:

add, negate, load, and jump if zero.

A program is a sequence of instructions stored in the 256 program registers.

Each of these registers holds 16 bits. The contents of the register specify the type of instruction and its operands. Two bits (positions 14-15) specify the instruction.

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Components of the Processor Instruction Set

The add Instruction

add Ra , Rb Rc Adds contents of registers Ra and Rb and stores result in register Rc . The indices a, b, and c are in bit positions 11-13, 8-10, and 5-7, respectively. Bit positions 0-4 will be ignored. Also increments the program counter by 1. 15 0 14 0 13 a 12 a 11 a 10 b 9 b 8 b 7 c 6 c 5 c 4 0 3 0 2 0 1 0 0 0

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Components of the Processor Instruction Set

The negate Instruction

neg Ra Replaces Ra with Ra , using the twos complement representation. Index a is specied by bit positions 11-13. Also increments the program counter by 1. 15 0 14 1 13 a 12 a 11 a 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Components of the Processor Instruction Set

The load Instruction

lod d Ra Loads an 8-bit number d into the 8 low-order bit positions of register Ra . The index a is specied by bit positions 11-13. The value d is specied the 8 low-order bits (positions 0-7) of the instruction. Also increments the program counter by 1. 15 1 14 0 13 a 12 a 11 a 10 0 9 0 8 0 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Components of the Processor Instruction Set

The jump if zero Instruction

jiz Ra d If register Ra is 0, sets the program counter to the value specied by an 8-bit number d , The index a is specied by bit positions 11-13. The value d is specied in binary by the 8 low-order positions of the instruction; that is, positions 0-7. Otherwise the program counter PC is incremented by 1, as usual. 15 1 14 1 13 a 12 a 11 a 10 0 9 0 8 0 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Components of the Processor Instruction Set

Example Program

A program to add numbers from 1 to 10 and store the result in one of the registers 0 1 2 3 4 5 6 7 lod lod lod add add jiz jiz jiz 10 R2 0 R3 1 R4 R2 , R3 R3 R2 , R4 R2 R2 7 R0 3 R0 7 10 010 000 00001010 10 011 000 00000000 10 100 000 11111111 00 010 011 011 00000 00 010 100 010 00000 11 010 000 00000111 11 000 000 00000011 11 000 000 00000111

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Components of the Processor Instruction Set

Example Program

A program to add numbers from 1 to 10 and store the result in one of the registers 0 1 2 3 4 5 6 7 lod lod lod add add jiz jiz jiz 10 R2 0 R3 1 R4 R2 , R3 R3 R2 , R4 R2 R2 7 R0 3 R0 7 10 010 000 00001010 10 011 000 00000000 10 100 000 11111111 00 010 011 011 00000 00 010 100 010 00000 11 010 000 00000111 11 000 000 00000011 11 000 000 00000111

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Components of the Processor Instruction Set

Example Program

A program to add numbers from 1 to 10 and store the result in one of the registers 0 1 2 3 4 5 6 7 lod lod lod add add jiz jiz jiz 10 R2 0 R3 1 R4 R2 , R3 R3 R2 , R4 R2 R2 7 R0 3 R0 7 10 010 000 00001010 10 011 000 00000000 10 100 000 11111111 00 010 011 011 00000 00 010 100 010 00000 11 010 000 00000111 11 000 000 00000011 11 000 000 00000111

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Components of the Processor Instruction Set

Example Program

A program to add numbers from 1 to 10 and store the result in one of the registers 0 1 2 3 4 5 6 7 lod lod lod add add jiz jiz jiz 10 R2 0 R3 1 R4 R2 , R3 R3 R2 , R4 R2 R2 7 R0 3 R0 7 10 010 000 00001010 10 011 000 00000000 10 100 000 11111111 00 010 011 011 00000 00 010 100 010 00000 11 010 000 00000111 11 000 000 00000011 11 000 000 00000111

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Components of the Processor Instruction Set

Example Program

A program to add numbers from 1 to 10 and store the result in one of the registers 0 1 2 3 4 5 6 7 lod lod lod add add jiz jiz jiz 10 R2 0 R3 1 R4 R2 , R3 R3 R2 , R4 R2 R2 7 R0 3 R0 7 10 010 000 00001010 10 011 000 00000000 10 100 000 11111111 00 010 011 011 00000 00 010 100 010 00000 11 010 000 00000111 11 000 000 00000011 11 000 000 00000111

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Components of the Processor Instruction Set

Example Program

A program to add numbers from 1 to 10 and store the result in one of the registers 0 1 2 3 4 5 6 7 lod lod lod add add jiz jiz jiz 10 R2 0 R3 1 R4 R2 , R3 R3 R2 , R4 R2 R2 7 R0 3 R0 7 10 010 000 00001010 10 011 000 00000000 10 100 000 11111111 00 010 011 011 00000 00 010 100 010 00000 11 010 000 00000111 11 000 000 00000011 11 000 000 00000111

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Components of the Processor Instruction Set

Example Program

A program to add numbers from 1 to 10 and store the result in one of the registers 0 1 2 3 4 5 6 7 lod lod lod add add jiz jiz jiz 10 R2 0 R3 1 R4 R2 , R3 R3 R2 , R4 R2 R2 7 R0 3 R0 7 10 010 000 00001010 10 011 000 00000000 10 100 000 11111111 00 010 011 011 00000 00 010 100 010 00000 11 010 000 00000111 11 000 000 00000011 11 000 000 00000111

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Components of the Processor Instruction Set

Example Program

A program to add numbers from 1 to 10 and store the result in one of the registers 0 1 2 3 4 5 6 7 lod lod lod add add jiz jiz jiz 10 R2 0 R3 1 R4 R2 , R3 R3 R2 , R4 R2 R2 7 R0 3 R0 7 10 010 000 00001010 10 011 000 00000000 10 100 000 11111111 00 010 011 011 00000 00 010 100 010 00000 11 010 000 00000111 11 000 000 00000011 11 000 000 00000111

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Components of the Processor Instruction Set

Example Program

A program to add numbers from 1 to 10 and store the result in one of the registers 0 1 2 3 4 5 6 7 lod lod lod add add jiz jiz jiz 10 R2 0 R3 1 R4 R2 , R3 R3 R2 , R4 R2 R2 7 R0 3 R0 7 10 010 000 00001010 10 011 000 00000000 10 100 000 11111111 00 010 011 011 00000 00 010 100 010 00000 11 010 000 00000111 11 000 000 00000011 11 000 000 00000111

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Components of the Processor Instruction Set

Example Program

A program to add numbers from 1 to 10 and store the result in one of the registers 0 1 2 3 4 5 6 7 lod lod lod add add jiz jiz jiz 10 R2 0 R3 1 R4 R2 , R3 R3 R2 , R4 R2 R2 7 R0 3 R0 7 10 010 000 00001010 10 011 000 00000000 10 100 000 11111111 00 010 011 011 00000 00 010 100 010 00000 11 010 000 00000111 11 000 000 00000011 11 000 000 00000111

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Components of the Processor Instruction Set

Example Program

A program to add numbers from 1 to 10 and store the result in one of the registers 0 1 2 3 4 5 6 7 lod lod lod add add jiz jiz jiz 10 R2 0 R3 1 R4 R2 , R3 R3 R2 , R4 R2 R2 7 R0 3 R0 7 10 010 000 00001010 10 011 000 00000000 10 100 000 11111111 00 010 011 011 00000 00 010 100 010 00000 11 010 000 00000111 11 000 000 00000011 11 000 000 00000111

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Components of the Processor Instruction Set

Example Program

A program to add numbers from 1 to 10 and store the result in one of the registers 0 1 2 3 4 5 6 7 lod lod lod add add jiz jiz jiz 10 R2 0 R3 1 R4 R2 , R3 R3 R2 , R4 R2 R2 7 R0 3 R0 7 10 010 000 00001010 10 011 000 00000000 10 100 000 11111111 00 010 011 011 00000 00 010 100 010 00000 11 010 000 00000111 11 000 000 00000011 11 000 000 00000111

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Components of the Processor Instruction Set

Example Program

A program to add numbers from 1 to 10 and store the result in one of the registers 0 1 2 3 4 5 6 7 lod lod lod add add jiz jiz jiz 10 R2 0 R3 1 R4 R2 , R3 R3 R2 , R4 R2 R2 7 R0 3 R0 7 10 010 000 00001010 10 011 000 00000000 10 100 000 11111111 00 010 011 011 00000 00 010 100 010 00000 11 010 000 00000111 11 000 000 00000011 11 000 000 00000111

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Components of the Processor Instruction Set

Example Program

A program to add numbers from 1 to 10 and store the result in one of the registers 0 1 2 3 4 5 6 7 lod lod lod add add jiz jiz jiz 10 R2 0 R3 1 R4 R2 , R3 R3 R2 , R4 R2 R2 7 R0 3 R0 7 10 010 000 00001010 10 011 000 00000000 10 100 000 11111111 00 010 011 011 00000 00 010 100 010 00000 11 010 000 00000111 11 000 000 00000011 11 000 000 00000111

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Components of the Processor Instruction Set

Example Program

A program to add numbers from 1 to 10 and store the result in one of the registers 0 1 2 3 4 5 6 7 lod lod lod add add jiz jiz jiz 10 R2 0 R3 1 R4 R2 , R3 R3 R2 , R4 R2 R2 7 R0 3 R0 7 10 010 000 00001010 10 011 000 00000000 10 100 000 11111111 00 010 011 011 00000 00 010 100 010 00000 11 010 000 00000111 11 000 000 00000011 11 000 000 00000111

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Components of the Processor Instruction Set

Example Program

A program to add numbers from 1 to 10 and store the result in one of the registers 0 1 2 3 4 5 6 7 lod lod lod add add jiz jiz jiz 10 R2 0 R3 1 R4 R2 , R3 R3 R2 , R4 R2 R2 7 R0 3 R0 7 10 010 000 00001010 10 011 000 00000000 10 100 000 11111111 00 010 011 011 00000 00 010 100 010 00000 11 010 000 00000111 11 000 000 00000011 11 000 000 00000111

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Components of the Processor Instruction Set

Example Program

A program to add numbers from 1 to 10 and store the result in one of the registers 0 1 2 3 4 5 6 7 lod lod lod add add jiz jiz jiz 10 R2 0 R3 1 R4 R2 , R3 R3 R2 , R4 R2 R2 7 R0 3 R0 7 10 010 000 00001010 10 011 000 00000000 10 100 000 11111111 00 010 011 011 00000 00 010 100 010 00000 11 010 000 00000111 11 000 000 00000011 11 000 000 00000111

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Design of the CPU

Lay out the registers, giving names to the input bits, output bits, and registers (have already done this). Design the circuits for extracting the next instruction and incrementing the PC. Design the circuits for implementing the add, negate, load, and jump-if-zero operations. Design the circuit that determines the input and the set bits for the data registers and the PC. These circuits can be put together by matching the appropriate labeled inputs and outputs.

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Registers and Adder

Input(Ri) Set(Ri) Ri

Output(Ri) A Input(PC) B 1 PC 32-BIT ADDER C A+B=C

Output(PC) Input(Pi) 0 Pi

Output(Pi)
J. Aslam, H. Fell, R. Rajaraman, R. Sundaram Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Extracting the instruction and incrementing the PC

Output(P0) Output(P1)
16 16

256WAY 16BIT MULTIPLEXER

I0 I1 I15

Output(PC) 00000001

8BIT ADDER
8

16

Increment(PC)

Output(P254) Output(P255)

16 16

Output(PC)

16

Output(Pi)

16 16

INSTRUCTION EXTRACTOR PC INCREMENTER

16

Output(PC)

Increment(PC)

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Circuit for the add instruction

32

Input_A(R0)

Output(R0)

32

8WAY 32BIT MULTIPLEXER Output(R7)

32

32

8WAY 32BIT DEMULTIPLEXER

32

Input_A(R7)

I1113

32 32

32BIT ADDER

I57

Output(R0)

32

Set_A(R0) 8WAY 32BIT MULTIPLEXER 8WAY 1BIT DEMULTIPLEXER Set_A(R7) I810 I57

Output(R7)

32

32

32 32

Output(Ri)

32 32

Input_A(Ri)

ADD INSTRUCTION

32

I513

Set_A(Ri)

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Circuit for the negate instruction

Output(R0)
32 32

Input_N(R0)

8WAY 32BIT MULTIPLEXER Output(R7)

32

32

32BIT NEGATER

32

8WAY 32BIT DEMULTIPLEXER

32

Input_N(R7)

I1113 Set_N(R0) 1 8WAY 1BIT DEMULTIPLEXER Set_N(R7)

I1113

I1113 Output(R0) Output(R7)

32 32 32 32

NEGATE INSTRUCTION

Input_N(R0) Input_N(R7) Set_N(R0) Set_N(R7)

I1113

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Circuit for the load instruction

I0 8WAY 32BIT DEMULTIPLEXER I7 I1113
32 32

Input_L(R0) 1 Input_L(R7) 8WAY 1BIT DEMULTIPLEXER

Set_L(R0)

Set_L(R7) I1113

I07 LOAD INSTRUCTION I1113

32

Input_L(Ri)

32

Set_L(Ri)

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Circuit for the jump-if-zero instruction

Increment(PC) I07
8

2WAY 8BIT MULTIPLEXER

Input_J(PC)

Output(R0)

32

8WAY 32BIT MULTIPLEXER Output(R7)

32

32

32BIT OR

NOT

I1113

PC Output(R0..R7) I07 I1113

32 32

JUMP INSTRUCTION

Input_J(PC)

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor

Building Blocks Architecture Design of the CPU

Storing the new values into the data registers and PC

The preceding circuits give us potential values to be stored in the data registers. The new values for the data registers are determined by instruction type.
Input_A(Ri) Input_N(Ri) Input_L(Ri) Output(Ri)
32 32 32 32

4WAY 32BIT MULTIPLEXER

32

Input(Ri)
8 8 8 8

Increment(PC) Increment(PC) I15 I14 Increment(PC) Input_J(PC)

4WAY 32BIT MULTIPLEXER

Input(PC)

Set_A(Ri) Set_N(Ri) Set_L(Ri) 0 4WAY 32BIT MULTIPLEXER Set(Ri) I15 I14

I15

I14

J. Aslam, H. Fell, R. Rajaraman, R. Sundaram

Design of a Simple Processor