CD4099BC 8-Bit Addressable Latch

October 1987 Revised April 2002

CD4099BC 8-Bit Addressable Latch

General Description
The CD4099BC is an 8-bit addressable latch with three address inputs (A0A2), an active low enable input (E), active high clear input (CL), a data input (D), and eight outputs (Q0Q7). Data is entered into a particular bit in the latch when that bit is addressed by the address inputs and the enable (E) is LOW. Data entry is inhibited when enable (E) is HIGH. When clear (CL) and enable (E) are HIGH, all outputs are LOW. When clear (CL) is HIGH and enable (E) is LOW, the channel demultiplexing occurs. The bit that is addressed has an active output which follows the data input while all unaddressed bits are held LOW. When operating in the addressable latch mode (E = CL = LOW), changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode (E = HIGH, CL = LOW).

Features
I Wide supply voltage range: 3.0V to 15V I High noise immunity: 0.45 VDD (typ.) I Low power TTL: fan out of 2 driving 74L compatibility: or 1 driving 74LS I Serial to parallel capability I Storage register capability I Random (addressable) data entry I Active high demultiplexing capability I Common active high clear

Ordering Code:
Order Number CD4099BCN Package Number N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Connection Diagram

Top View

Truth Table
Mode Selection E CL L H L H L L Addressed Latch Follows Data Unaddressed Latch Holds Previous Data Addressable Latch Reset to 0 Reset to 0 Demultiplexer Clear Mode

Holds Previous Data Holds Previous Data Memory

H Follows Data H Reset to 0

2002 Fairchild Semiconductor Corporation

DS005984

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CD4099BC

Logic Diagram

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CD4099BC

Absolute Maximum Ratings(Note 1)

(Note 2) DC Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) 260C (Note 2) 700 mW 500 mW

Recommended Operating Conditions (Note 2)

DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) 3.0 to 15 VDC 0 to VDD VDC

0.5 to +18 VDC 0.5 to VDD +0.5 VDC 65C to +150C

55C to +125C

Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The tables of Recommended Operating Conditions and Electrical Characteristics provide conditions for actual device operation. Note 2: VSS = 0V unless otherwise specified.

DC Electrical Characteristics
Symbol IDD Parameter Quiescent Device Current VOL LOW Level Output Voltage

Conditions VDD = 5V, VIN = VDD or VSS VDD = 10V, VIN = VDD or VSS VDD = 15V, VIN = VDD or VSS |IO| 1A VDD = 5V VDD = 10V VDD = 15V

55C Min Max 5.0 10 20 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 0.64 1.6 4.2 0.64 1.6 4.2 0.1 0.1 3.5 7.0 11.0 0.51 1.3 3.4 0.51 1.3 3.4 4.95 9.95 14.95 Min

+25C Typ 0.02 0.02 0.02 0 0 0 5 10 15 2.25 4.5 6.75 2.75 5.5 8.25 0.88 2.25 8.8 0.88 2.25 8.8 105 105 0.1 0.1 1.5 3.0 4.0 Max 5.0 10 20 0.05 0.05 0.05

+125C Min Max 150 300 600 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 0.36 0.9 2.4 0.36 0.9 2.4 1.0 1.0

Units

VOH

HIGH Level Output Voltage

|IO| 1 A VDD = 5V VDD = 10V VDD = 15V V

VIL

LOW Level Input Voltage

VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1.0V or 9.0V VDD = 15V, VO = 1.5V or 13.5V VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1.0V or 9.0V VDD = 15V, VO = 1.5V or 13.5V VDD = 5V, VO = 0.4V VDD = 10V, VO = 0.5V VDD = 15V, VO = 1.5V VDD = 5V, VO = 4.6V VDD = 10V, VO = 9.5V VDD = 15V, VO = 13.5V VDD = 15V, VIN = 0V VDD = 15V, VIN = 15V

VIH

HIGH Level Input Voltage

IOL

LOW Level Output Current (Note 3)

mA

IOH

HIGH Level Output Current (Note 3)

mA

IIN

Input Current

Note 3: IOH and IOL are tested one output at a time.

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CD4099BC

AC Electrical Characteristics
Symbol tPHL, tPLH Parameter Propagation Delay Data to Output tPLH, tPHL Propagation Delay Enable to Output tPHL Propagation Delay Clear to Output tTLH, tTHL Propagation Delay Address to Output tTHL, tTLH Transition Time (Any Output) TWH, TWL Minimum Data Pulse Width tWH, tWL Minimum Address Pulse Width tWH Minimum Clear Pulse Width tSU Minimum Set-Up Time Data to E tH Minimum Hold Time Data to E tSU Minimum Set-Up Time Address to E tH Minimum Hold Time Address to E CPD CIN Power Dissipation Capacitance Input Capacitance

(Note 4)
Conditions Min Typ 200 75 50 200 80 60 175 80 65 225 100 75 100 50 40 100 50 40 200 100 65 75 40 25 40 20 15 60 30 25 15 0 0 50 20 15 100 5.0 7.5 Max 400 150 100 400 160 120 350 160 130 450 200 150 200 100 80 200 100 80 400 200 125 150 75 50 80 40 30 120 60 50 50 30 20 15 10 5 pF pF ns ns ns ns ns ns ns ns ns ns ns ns Units

TA = 25C, CL = 50 pF, RL = 200k, Input tr = tf = 20 ns, unless otherwise noted VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V Per Package (Note 5) Any Input

Note 4: AC Parameters are guaranteed by DC correlated testing. Note 5: Dynamic power dissipation (PD) is given by: PD = (CPD + C L) VCC2f + PQ; where CL = load capacitance; f = frequency of operation; for further details, see application note AN-90, 54C/74C Family Characteristics.

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Switching Time Waveforms

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CD4099BC 8-Bit Addressable Latch

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E

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