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KS30103 Microprocessor

INTRODUCTION TO PROGRAMMING
Outcomes
At the end of this chapter, you should be able to: 1. 2. 3. 4. 5. Define software, programme, and programming languages Explain the classification of programming languages Describe the stages of a programme's development life cycle Describe the sequence, selection, and iteration programming constructs Design a simple program using flowchart

Fundamentals
Computers, in general, are divided into two parts: hardware and software. By definition, all physical components (CPU, memory, I/O ports etc) of the computer are collectively called the hardware. Software, on the other hand, refers to the instructions that tell the hardware what to do. Software Software refers to computer instructions or data or anything that can be stored electronically. It can be classified into systems software that includes the operating system and all the utilities that enable the computer to function. And applications software that includes programs that do real work for users. For example, word processors, spreadsheets, and database management systems fall under the category of applications software Program A program is an organised lists of instructions in a given programming language that, when executed, causes the computer to behave in a predetermined manner. An instruction is a computer command that tell the computer to perform an action. Programming Languages A programming language has a vocabulary and a set of grammatical rules for instructing a computer to perform specific tasks. The vocabulary is a set of unique keywords (words that it understands). While, the grammatical rules (syntax) specify how instructions are organised. Programming Languages Classifications

KS30103 Microprocessor
Programming languages, in general, can be classified into 4 categories called generations. These generations reflect the historical development of programming languages. As can be seen in figure 1.1 below, the first level of software above the hardware is machine code (first generation). The second level (second generation) is assembly language. While, the third and fourth levels are high-level (third generation) and objectoriented (fourth generation) respectively.

Fourth Generation High-Level Language Assembly Language Machine code Hardware


Figure 1.1

First Generation (Machine Code)

Machine code is the lowest-level programming language and is the only languages understood by computers. Machine language instructions are written in binary or hexadecimal numbers. This makes it easily understood by computers but almost impossible for humans to understand and use. Every CPU has its own unique machine language and thus, machine language are called machine-dependent which means a program written for a given CPU can only runs on that CPU.

Second Generation (Assembly Language)


Assembly language is the next level above machine code. It has the same structure and set of commands as machine language, but it allows a programmer to use names (mnemonics) instead of numbers to write instructions. Each type of CPU has its own machine language and assembly language, so an assembly language program written for one type of CPU won't run on another. Thus, assembly language is machine-dependent. In the early days of programming, all programs were written in assembly language. Now, most programs are written in a high-level language. Programmers, however, still use assembly language when speed is essential or when they need to perform an operation that isn't possible in a high-level language. Assembly language programs need to be translated to machine code before they can be executed (run) by the CPU. An assembler (translator program) is used to translate assembly language programs into machine language

Third Generation (High-Level Language)


Machine code and assembly language are called low-level programming languages because each instruction corresponds to one CPU action. High-level languages, on the other hand, allow programmers to write powerful instruction that may generate many CPU actions. In addition, high-level languages enable a programmer to write programs that are more or less independent of a particular type of computer. Thus, high-level languages are called machine-independent.

KS30103 Microprocessor
The main advantage of high-level languages over low-level languages is that they are easier to read, write, and maintain. Programs written in a high-level language must be translated into machine language by a compiler or interpreter.

Fourth Generation (Object-Oriented, Query Language)


Fourth-generation languages, often-abbreviated 4GL, are programming languages closer to human languages than typical high-level programming languages. Most 4GLs are used to access databases. Program Development Life Cycle The phases a software product goes through between when it is conceived and when it is no longer available for use is called the software life cycle. The software life cycle typically Testing includes the following Design, and stages: Coding, Coding Requirements Analysis, Design Requirement Analysis

(validation)

Debugging, Testing

Implementation, Operational Maintenance, and Retirement. The development process tends to run iteratively through these phases rather than linearly as shown in figure 1.2 below. Although all the stages given in figure 1.2 are important, only those stages that are very critical for developing assembly language programs are briefly described below. Yes

Logical Errors?

No Implementation

Maintenance

Design Stage
The design stage involves expressing the solution to the problem in a standard format. There are several design tools (pseudoFigure 1.2 languages) that can be used by programmer. The most common design tool used by assembly language programmer is flowchart. While, pseudocode is a common design tool used by third and fourth generation programmers. These common design tools are briefly described below: Retirement

Flowchart

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Flowchart is a graphical representation of the program logic. It is one of the oldest methods of program design. Flowchart uses graphical shapes to represents different actions that the computer will perform. Arrows that indicate the flow of control connect these shapes. Figure 1.3 shows the common flowchart symbols.

PROCESS

DECISIO N

INPUT OUTPUT /

START/END

PROCEDUR E

TERMINATION CONNECTOR OFF-PAGE CONNECTOR

DIRECTION OF FLOW CONTROL

Figure 1.3

Pseudocode
Pseudocode is a notation resembling a programming language but not intended for actual compilation. It usually combines some of the structure of a programming language with an informal natural-language description of the computations to be carried out. It is often produced by CASE systems as a basis for later hand coding.

Coding
A written computer instruction is called a code and the process of writing codes is called coding. The code written by programmers is called source code. The programmer then uses a compiler to compile the source code to produce what is called an object code. The object code is then converted to a program that is ready to run which is called executable code or machine code.

Debugging
A bug is an error or defect in software or hardware that causes a program to malfunction. The process of detecting and removing bugs is called debugging. This process is an iterative process that is carried out every time an error is detected by the testing stage. Thus, the debugging stage may involve going back through the analysis, design, coding, and testing stages.

Program Constructs
A program can be written using only few constructs (building blocks). These constructs are: 1. Sequence 2. Selection 3. Iteration

KS30103 Microprocessor
Sequence The simplest construct is the sequence. In a sequence, all the statements are executed one after another in the same order they are found in the program. The diagram below shows a sequence in flowchart and pseudocode

STATEMENT 1

STATEMENT 1 STATEMENT 2

deduction = epf +income-tax

deduction = epf +income-tax

b) Pseudocode STATEMENT 2 Salary = grossdeduction

Salary = grossdeduction

a) Flowchart
Selection There are two constructs that perform selection: The IF construct. The CASE construct

The IF Construct
This construct has two forms: IF <condition> THEN <true action> ELSE <false action> and IF <condition> THEN <true action>. The condition is evaluated. If the condition evaluates to logical True then the <true action> is executed and the <false action> is skipped. is skipped. The diagram below shows an example. If the condition evaluates to logical False then the <false action> is executed and the <true action>

KS30103 Microprocessor

Yes

Decision

No

True?

Decision True?
Yes

No

True Action

False Action

True Action

IF.THEN.ELSE
a) Flowchart

IF.THEN

IF Conditon THEN True Action ELSE False Action ENDIF


b) Pseudocode

IF Conditon THEN True Action ENDIF

The Case Construct


The case construct can be thought of as a group of nested if constructs. In this construct, several conditions are evaluated. If condition1 evaluates to true then action1 is executed and all other actions are skipped. If, however, condition2 is true then action2 is executed and all other actions are skipped. This process continues until all conditions are evaluated. If no condition evaluates to true then the false action (if there is one) is executed. Like the IF construct, only one action or no action in the case construct will be executed.

c) Pseudocode

a) Flowchart
Select Case Case 1

Select Case Expression


Case 2 Case 1 Case 2 Case n .. Case N

Do action 1

Do action 2

Action 1

Action 2

..

Action n

Do action N [Otherwise Do falseaction] Endcase

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Iteration There are basically two types of Iterations: the While Loop and the Repeat until loop

The While Loop


A condition is evaluated at the beginning of the loop. If the condition is true, all the statements in the loop are executed and the condition is evaluated again. These processes continue until the condition evaluates to false.

No

Is Condition True? Yes Body of the Loop

THE REPEAT-UNTIL LOOP


All the statements in this loop are executed before the condition placed at the end of the loop is evaluated. If it evaluates to true the loop is terminated. However, if it evaluates to false, the statements are executed again until the condition is true.

Body of the Loop

Yes

Is Condition True? No

Figure

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Example. The program below reads a set of numbers and counts how many odd and even numbers exist in the set. As it can be seen, the flowchart is made of a single while loop that checks if there are more numbers in the set. If yes, then a number is read from the set. Within the While construct there is an IF construct. If the number is odd the odd number counter is incremented by 1 else the even number counter is incremented by 1. This process continues until no more numbers in the set. A procedure displays the results before the program is terminated. Start

No

More number ? Yes Read a Number

Print Result

End

No

Is Number odd?

Yes Increment Even Number Counter Increment Odd Number Counter

Self-Test Questions 1) 2) Computers, in general, are divided into: a) Hardware and programs b) Hardware and software A programming language has: a) Keywords b) Syntax c) All of the above Programming languages are classified into: a) 3 generations b) 4 generations c) 5 generations d) None of the above

3)

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4) The common design tools are: a) Flowchart and coding b) Pseudocode and chart c) Pseudocode and flowchart The common programme constructs are: a) Sequence, IF, and Loop b) If, While loop, and Repeat loop c) Sequence, Selection, and Iteration d) None of the above In a While loop, the condition that control the execution of the loop is placed at: a) The beginning of the loop b) The end of the loop c) Anywhere in the loop

5)

6)

Review Questions
1) 2) 3) 4) 5) 6) 7) Define Software Define Program Define Programming Languages Describe 2nd generation programming languages List the stages in the programme development life cycle Describe the flowchart symbols given in figure 3.3 Draw a flowchart for the program whose pseudocode is given below Input age If age > 21 then Display "You are eligible to vote" Else Display " Sorry! You are under-age" Endif 8) 9) Draw a flowchart for a program that displays the odd number from 1 to 9 A program that perform the following tasks: a) b) c) Accept a long sentence Convert it to upper case Display the result on the screen Design this program using flowchart and pseudocode

You are required to:

KS30103 Microprocessor

INTRODUCTION TO ASSEMBLY LANGUAGE PROGRAMMING


Outcomes
1. 2. 3. Explain the basic structure of an assembly language programme List and explain the tools required for assembly language programming Describe the steps in creating assembly language programmes

Fundamentals
The Structure of an Assembly Language Program An assembly program contains: 1. Statements or instructions that the programmer wants them executed by the

microprocessor. Each statement may have up to 4 fields 2. Directives to the Assembler (translator program) that informs the assembler how to assemble (translate) the program 3. Remarks that explains the working of the program to other programmers. These remarks are optional and will be ignored by the assembler.

Assembly Language Programs Statements


An assembly language statement may have up to 4 fields as shown in example 2.1. The first field (new:) is the label field. It is used for flow control of the program. A colon (:) must terminate the label field. This field is not required unless the programmer wants to refer to that line somewhere in the program. The next field is the operation code (Add), which must be a valid operation code for the given microprocessor. The operation codes are given by the microprocessor manufacturer and are called the instructions set. The operation code tells the microprocessor what action to perform. This field is required unless that line of the program is a remark line. The third field is the operand field (AX,5H). This contains the data on which the operation will be performed. The type and the number of operands depend on the operation code, as some may required no operand, one, or two operands. If more than one operand is required they

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must separated by commas. The last field is the remark field (; Add percentage). This may contains anything as it is intended for the programmer and not the computer. The objectives of the remark field are to aid the readability of the program; help the programmer understands the program and thus improve maintainability. The comment field starts with a semicolon (;). This field is not compulsory but recommended. Example 2.1 New: Add Mov Jmp Field No 1 Label field 2 Operation Code 3 Operand 4 Comment Used for reference in program execution control Must be a single word Must be terminated by a colon (: ) Optional i.e. not compulsory A mnemonic taken from the microprocessor instructions set Compulsory except for empty lines Depends on the operation code Not all operation code requires an operand Can be a constant or a variable Must start with a semicolon (;) Used to explain the statement line Optional AX,5H dx,ax new Comment ; Add percentage

Contents

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Assembler Directives
Assembler directives are pseudo-operations that control the assembly process but they do not generates any instructions in the assembled program. They merely instruct the assembler on how to process the assembly programs and as such they are specific to each particular assembler. Some common uses of assembler directives are: To declare variables (reserve memory space to store data), To define segment, and To define procedures (subroutines) ; Exp2_1.asm ; display a message on the screen .MODEL SMALL

.STACK 200h .DATA Prompt .CODE .startup

db 13,10,"This is the message $"

.exit end

mov ax, seg prompt ;moves the segment of data into ax mov ds,ax mov ah,9 mov dx,offset Prompt int 21h ;print the message

Figure 2.1 An Example of an Assembly Language Program

Assembly Language Programming Tools To be able to effectively develop assembly programs, the following tools are needed:

Text Editor
A text editor is a program that allows you to create a file containing the assembly programs (source code). Some of the operations that you can perform with a text: 1. Type the assembly program 2. Correct any typing error in the program 3. Insert new statements or delete unwanted ones 4. Save the program on magnetic medium for later uses

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5. Rearrange the order of the statements by moving them from one place in the program to another 6. Copy part of the program and insert it in another part of the program or in another program 7. Some text editors may have more advanced facilities like find and replace, etc. Text Editor Source Code

Hand written Assembly Program

Manual Input

Figure 2.2

Source Code

Assembler
The assembler is a program that translates assembly language statements into machine code instructions that can be executed by the microprocessor. The assembler takes the source code as input and will produces an object file containing the machine code instructions if the assembler did not detect any syntax error during the assembly process. Other optional files may be generated depending on the assembler in use. If the assembler detects any error during the assembly process only a list file containing the assembly instructions, the error code, and an error message for each error encountered will be produced.

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Source Code

Assembler

Syntax Errors?

Source code Listing + error messages

Figure 2.3

Source code Listing

Object Code

LINKER
A linker is a program that links several object files into an executable file (a program) that can be executed. The output of the linker is an executable file if no error encountered during the linking process. If any error encountered the linking process is halted and an error message describing the error is displayed Linker

Object Code

Executable Code

Library Files

Figure 2.4

Creating Assembly Programs To create an assembly program, follow the steps below: 1. Design your program using any of the design tools mentioned earlier 2. Use a text editor or a word processor that can produce text file to type the assembly language programs 3. Save the program (as a DOS text file) on a disk 4. Assemble the program to check for syntax errors

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5. If the program assembles properly, Link the program to produce an executable file 6. Run the executable file Self-Test Questions 1) An assembly program may contain a) b) c) d) 2) 3) Assembly language instructions Assembler directives Comments All the above

An assembly language statement may have up to ______ fields Assembler directives can be used to: a) b) c) d) Declare variables Define segments Define procedures All the above

4)

The input file to an assembler is called a) b) c) Source code Object code Executable code

Review Questions
1) 2) Describe the structure of an assembly language program Describe the structure of an assembly language statement

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ARCHITECTURE OF THE 80386 MICROPROCESSORS


Outcomes
1. Describe the RISC and CISC microprocessor architectures 2. Highlight the major events in the history of microprocessor 3. Give an overview of the software view of the 80386 microprocessor 4. Describe the functions of the 80386 registers 5. Describe the usage of the 80386 flags

The Architecture of a Microprocessor


A central processing unit (CPU) on a single integrated circuit is often called a microprocessor. The CPU is divided into several smaller units such as the Arithmetic and Logic Unit (ALU), the decoding unit, etc. Each of these units is designed to perform specific function such as arithmetic and logic operations performed by the (ALU). Architecture The architecture of a microprocessor refers to its internal design. Microprocessors can be classified according to their architecture as either Reduced Instruction Set Computing (RISC) or Complex Instruction Set Computing (CISC). However, microprocessors can also be classified according to the type of applications they are used for to two main categories general-purpose and special-purpose. General-purpose microprocessors are used in computers while specialpurpose ones are used in embedded systems.

Reduced Instruction Set Computing


A processor whose design is based on the rapid execution of a sequence of simple instructions rather than on the provision of a large variety of complex instructions is called a RISC processor Features that are generally found in RISC designs are: Uniform instruction encoding which allows faster decoding A homogenous register set, allowing any register to be used in any context and simplifying compiler design Simple addressing modes with more complex modes replaced by sequences of simple arithmetic instructions. Examples of RISC processors are the Berkeley RISC, HP-PA, Clipper, i960, AMD 29000, RISC System 6000 and SP/2 lines

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Complex Instruction Set Computing
A processor where each instruction can perform several low-level operations such as memory access, arithmetic operations or address calculations is called a CISC processor. The aim of this design is to bridge the "semantic gap". Thus, to design instruction sets to support high-level languages by providing "high-level" instructions such as procedure call and return, loop instructions such as "decrement and branch if non-zero" and complex addressing modes to allow data structure and array accesses to be compiled into single instructions. While these architectures achieved their aim of allowing high-level language constructs to be expressed in fewer instructions, it was observed that they did not always result in improved performance. Examples of CISC processors are the Motorola 680x0 family and the Intel 80186 through Intel 486 and Pentium.

Embedded Systems
An embedded system is a system in which the microprocessor performs a dedicated task. A typical embedded system consists of a single-board microcomputer with software in ROM, which starts running some special purpose application program as soon as it is turned on and will not stop until it is turned off. An embedded system may include some kind of operating system but often it will be simple enough to be written as a single program. It will not usually have any of the normal peripherals such as a keyboard, monitor, serial connections, mass storage, etc. or any kind of user interface software unless these are required by the overall system of which it is a part. Often it must provide real-time response. Embedded systems can be classified as either event controller or data controller. Event controller as often called Microcontroller such as the Intel 8051 while data controller are called embedded microprocessor such as the 80386EX. The control of an air condition unit is an example of event control. The Microcontroller is used primarily to detect the temperature and to switch the air condition unit on and off. The hard-disk controller however, is an example of data control because the primary function of the microprocessor is to transfer as fast as possible data between the hard disk and the computer memory.

The History of Microprocessors


Microprocessors have evolved very fast during the introduction of the first microprocessor in 1971 by Intel. A brief history of the evolution of the microprocessor is given in the table below Year 1971 Microprocessor Intel 4004 and 4040 Family 4-bit Remarks address up 4k*4 memory has only 45 instructions speed of 50 KIPs (Kilo Instructions per second)

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1972 1974 1977 1978 Intel 8008 Intel 8080 Motorola Zilog Z80 Intel 8085 8-bit 8-bit 8-bit 1986 1989 Intel 80386, Motorola 32-bit 68020 Intel 80486 32-bit address up 16k*8 memory has only 48 instructions can manipulate data and characters address up 64k*8 memory has only 48 instructions 10 times faster than the 8008 An updated version and slightly faster than the 8080 has 246 instructions address up 1M*8 memory has 20,000 instructions speed of 2.5MIPs (Million Instructions per second) has an instruction cache or queue address up 16M*8 memory has a few additional instructions than the 8086 speed of 4.0 MIPs (Million Instructions per second) address up 4G*8 memory clock speed of 16 to 33 MHz address up to 4G*8 memory clock speed of 25 to 100 MHz has an 8K internal cache speed of up to 50 MIPs address up to 4G*8 memory clock speed of 60 to 166 MHz has an 16K internal cache speed of up to 110 MIPs address up to 64 Gigabytes Clock speed from 233 to 450 MHz Has two levels caches 512K level 2 and 32K level 1 Bus speed of 66 and 100 MHz address up to 64 Gigabytes Clock speed from 450 to 550 MHz Has two levels caches 512K level 2 and 32K level 1 Bus speed of 100 MHz 70 new instructions

MC6800,

Intel 8086, Motorola 16-bit 68000

1983

Intel 80286

16-bit

1993

Intel PowerPC

Pentium, 64-bit

1997

Intel Pentium II

64-bit

1999

Intel Pentium III

64-bit

The Software View of the 80386 Microprocessor


The 80386 Microprocessor Family
The 80386 family contains several microprocessors to satisfy the needs of different types of users. The most common family members are the 80386DX and the 80386SX. Table 3.2 below gives a brief description of some of the features of both DX and SX versions of the 80386. Both

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the SX and the DX versions of the 80386 can operate in either real mode or protected mode. In the real mode the 80386 microprocessor operates like a powerful 80286 (16-bit microprocessor) and thus can address only 1 MB of memory. In the protected mode the 80386 can access the entire memory space. In this book only the real mode will be discussed.

80386 DX 32-bit data bus 32-bit address bus 132 pin package can address up to 4 Gigabyte

80386 SX 16-bit data bus 24-bit address bus 100 pin package can address up to 16 megabyte 16 bit data transfer

32 Model bit data transfer Real Mode

To enable a programmer to write assembly programs for the 80386 family of microprocessors, Table 3. 2 a software model of the internal architecture of the microprocessor is needed. Figure 2.1 shows software view of the real mode model of the 80386 microprocessor. In this model, it can be seen that all the registers that are available in the 80286 are available in the 80386 real mode for upward compatibility.

Registers
The 80386 microprocessor has a large number of registers as can be seen in figure 3.1. We can broadly classify these into two groups: General-purpose registers, and Special purpose registers

GENERAL PURPOSE REGISTERS


The general-purpose registers can also be divided into two groups: Data registers, and index and pointers registers.

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31

15

CS Segment Register DS SS ES FS GS EAX

AX

EAX EBX ECX EDX

AH BH CH DH

AL BL CL DL

AX BX CX DX

ESP EBP ESI EDI


IP

SP BP SI DI

Flags CR0

Figure 3.1

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There are 4 data registers that can be used to store temporary data during execution of program instructions. They can be used as destination or source for any data movement instruction. These register can be used as 8-bit (for example AL or AH) so that programs written on Intel 8-bit microprocessor can be executed on the 80386 in real mode. They can also be used as 16-bit (for example AX) to allow 80286 codes to run by the 80386. These registers also allow 32-bit operations (for example EAX). Although, these registers are called general purpose, there are certain operations that only possible on a given register. Table 3.2 below lists the 4 general-purpose data registers and the operations specific to each of them.

REGISTER NAME Accumulator

ABBREVIATION 8 AL 8 AH 16 AX 32 EAX

USAGE

Arithmetic operations like addition, subtraction, division and multiplication, data conversion between byte, word, double word, and quadruple word. Input/output operations and memory addressing

Base Index Count Data

BL CL DL

BH CH DH

BX CX DX

EBX ECX EDX

Memory addressing Looping and repeating string operations, reading and writing data to disk files Input/output operations with external devices, multiplication operations Table 3.2 and division operations (in conjunction with accumulator), and string

Index and Pointer Registers


The 4 registers in this group can be used either as 16-bit or 32-bit registers. These registers are used to hold the offset of the address of the data held in memory. The other part of the

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address, the segment address, is normally held by a segment registers. Table 3.3 list the name and abbreviation of these registers.

Register Name Base Pointer Destination Index Source Index Stack Pointer

Abbreviation 16 BP DI SI SP 32 EBP EDI ESI ESP

Usage Used to hold the offset address of the stack as well as the memory Used to hold the offset address of a destination operand Used to hold the offset address of a source operand Used to hold the offset address of the stack Table 3.3

SPECIAL PURPOSE REGISTERS


The 80386 microprocessor has 4 types of special purpose registers. These are the Segment registers, the Flags register, Instruction Pointer, and Control registers.

The Segment Registers


The six segment registers are 16 bits wide. Each segment register holds the base memory address for a 64K-memory segment. Table 3.4 below briefly describes the usage of the segment registers.

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REGISTER NAME Stack Segment Code Segment Data Segment Extra Segment Additional Segments ABBREVIATION SS CS DS ES GS and FS USAGE Holds the Base address of the stack memory Holds the Base address of the code memory Holds the Base address of the data memory Holds the Base address of the extra memory Hold Table 3.4 the Base address for two additional segments of memory

The Flags
The 80386 microprocessor has a 32-bit flag register (EFLAGS). However, in real-mode only the first nine bits are used. These are the same as those for the 80286 microprocessor. The first six are called status flags because their states (set or reset) change as a result of executing certain instructions. The last three flags are control flags used to control the operations of the 80386 microprocessor. The name and usage of these status flags are summarised in table 3.5 below

NAME Carry

ABBREVIATION C

USAGE This flag is set (1) if there is a carryout or a borrowfrom the most significant bit of an arithmetic instruction such as Add. Otherwise, it is reset (0)

Parity

If the result of an instruction has an even number of 1's (even Parity) then this flag is set. Otherwise, it is reset

Auxiliary Carry

This flag is set if there is a carryout from the low nibble to the high nibble or a borrow-from the high nibble to the low nibble during BCD addition and subtraction. Otherwise, it is reset

Zero

This flag is set if the result of an instruction is 0

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otherwise, it is reset Sign Overflow Trap S O T This flag is set if the result of logic or an arithmetic operation is negative. Otherwise, it is reset. This flag is set when an overflow occurs during signed number arithmetic Used to enable trapping errors during program debugging. If this flag is set, the single-step mode of the 80386 is enabled Interrupt Direction I D If set to 1 interrupt is enabled otherwise interrupt is disabled If set to 1 the DI and SI registers are automatically decremented incremented Table 3.5 otherwise they are automatically

The Instruction Pointer


The instruction pointer (IP) is a 16-bit register. This register is used with the code segment register (CS) to hold the address of the next instruction to be fetched from the code segment of the memory.

Control Register
Although, the 80386 microprocessor has several control registers, only one of them control register zero is active in real-mode. The five least-significant digits are called the machine status word (MSW). In real-mode, only bit 0 of the control register zero is active. This bit is called the protection enable and is used to switch between real-mode and protected-mode. Self-Test Questions 1. Microprocessors are classified according to their architecture as: a. b. 2. a. b. General-purpose, and special-purpose Complex instruction set computing, and reduced instruction set computing True False

The 80386EX is an example of event controller?

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3. RISC microprocessors decode instructions faster than CISC microprocessor of the same class? a. b. 4) a) b) c) d) 5) a) b) c) 6) a) b) c) d) 7) a) b) c) d) 8) a) b) c) d) 9) True False General-purpose and special-purpose General-purpose, data, index and pointer registers Special-purpose, data, index and pointer registers None of the above 6 4 8 8-bit access 16-bit access 32-bit access All the above Arithmetic operation Input/output operation Data conversion All the above 6 4 2 None of the above

The registers of the 80386 microprocessor can be classified into:

The number of data registers in the 80386DX microprocessor is?

The data registers in the 80386 microprocessor allows:

Which of the following operations can be performed on the accumulator?

The number of index registers in the 80386DX microprocessor is?

Which two of the index and pointer registers can be used to hold the offset for the stack segment? a) b) c) d) SP and SI BP and DI SP and BP All the above

10)

The special-purpose registers of the 80386 microprocessor are:

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a) b) c) 1. 2. 3. 4. 5. 6. Segment registers, Instruction pointer, and Control register Segment registers, Flags register, Instruction pointer, and Control register Segment registers and Flags register

Review Questions Contrast the RISC and CISC microprocessor architectures Highlight the main features of Intel 32-bits microprocessors List the 4 data registers and briefly explain their usage List the 4 index and pointer registers and briefly explain their usage List the 6 segment registers and briefly explain their usage Explain the usage of the Carry flag

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DATA STORAGE AND MOVEMENT

Objectives
1. Show how numeric data are represented in computers 2. Show how alphanumeric data (Characters) are represented in computers

Data Representation within a Computer


Data can be classified into numeric and alphanumeric. The decimal digits from 0 to 9 are called numeric data because arithmetic operations can be performed on them. Alphanumeric data, on the other hand, comprises alphabets, numbers, and symbols. Alphanumeric Data The most common way to represent alphanumeric data is the ASCII code. The ASCII is an acronym of American Standard Code for Information Interchange. This code assigns the letters of the alphabet, decimal digits from 0 to 9 and some additional symbols a binary number of 7 bits, putting the 8th bit in its off state or 0. This way each letter, digit or special character occupies one byte in the computer memory. In most microcomputer, placing a 1 in the most significant bit uses an extended ASCII character set. The extended ASCII is used to represent foreign letters, Greek and mathematical symbols as well as box drawing and other special characters. Table 4.1 below shows the ASCII code. Notice that the codes from 0H to 1FH (Grey background) are called control codes and are used to control the operation of the computer. The control codes are non-printable. Only 4 of the control codes are shown here.

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MSB LSB 0 1 2 3 4 5 6 7 8 9 A B C D E F CR LF ESC BEL 0 1 2 SP ! " # $ % & ' ( ) * + , _ . / 3 0 1 2 3 4 5 6 7 8 9 : ; < = > ? Table 4.1 Numeric Data Numeric data can be classified as either integer or real. Integer numbers are whole number with no decimal point, while real numbers have decimal point. The 80386 can only perform arithmetic operations on integers and therefore, only the representation of integers in computer will be discussed here. Integers can be represented in the computer as pure binary digits or as a binary coded decimal (BCD). 4 @ A B C D E F G H I J K L M N O 5 P Q R S T U V W X Y Z [ \ ] ^ 6 ' a b c d e f g h i j k l m n o 7 P q r s t u v w x y z | ~ DEL

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KS30103 Microprocessor
BCD Method
BCD is an acronym for Binary Coded Decimal. In BCD a group of 4 bits are used to represent each decimal digit from 0 to 9. Data in BCD can be stored either as packed BCD or as unpacked BCD. In packed BCD, each nibble of a byte represents one decimal digit. Thus, we can store two digits per byte of information. While, in unpacked BCD, the upper nibble is set to 0 and the lower nibble is used to store the decimal digit. Thus, we can only store one digit per byte of information. Table 4.2 below shows how integers are stored as packed and unpacked BCD.

DECIMAL 25 427

PACKED 0010 0101 0000 0100 0010 0111

UNPACKED 0000 0010 0000 0101 0000 0100 0000 0010 0000 0111

Table 4.2 Storage of decimal numbers as Packed and unpacked BCD

Integer Representation In Binary Format


Integers, signed and unsigned can be represented as a single byte, single word (2 bytes) or as a double word (4 bytes).

Byte-Sized Data
An integer can be stored as a single byte (8-bits). The range for unsigned integer is from 0 to 28-1 i.e. from 0 to 255. While the range for the signed integer is from -27 to 27-1 i.e. from -128 to 127. Signed integers are stored in 2's complement, thus, the most significant bit is 1 for negative numbers and 0 for positive numbers. Figure 4.2 below shows how signed and unsigned integers are stored as a single byte.

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KS30103 Microprocessor

Binary Weights

Binary Weights

128 64 32 16 8 0 0 0 0

2 1
Smallest

-128 64 32 16 8 1 0 0

2 1 0

0 0 0 0

0 0 0 0

Figure 4.2 Single byte storage of signed and unsigned integers

1 1 1

1 1

1 1 1

Largest

0 1 1 1 1 Signed byte

1 1 1

Unsigned byte

Word-Sized Data
An integer can be stored as a single word (16-bits). The range for unsigned integer is from 0 to 216-1 i.e. from 0 to 65535. While the range for the signed integer is from from -215 to 215-1 i.e.

-32786 to 32785. Figure 4.3 below shows how signed and unsigned integers are stored

as a single word. Binary Weights 32768 0 0 0 0 0 0 0 256 0 128 0 64 0 0 32 16 0 8 0 4 0 2 0 0 1

Figure 4.3 a) Storage of an unsigned integer in a 16-bit (word) format

Binary Weights -32768 1 0 0 0 0 0 0 256 0 128 0 64 0 0 32 16 0 8 0 4 0 0 2 0 1

Figure 4.3 b) Storage of a signed integer in a 16-bit (word) format

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KS30103 Microprocessor
Double-Word Sized Data
An integer can be stored as a double word (32-bits). ). The range for unsigned integer is from 0 to 232-1 i.e. from 0 to 4294967295. While the range for the signed integer is from 1 i.e. from -2147483648 to 2147483647. -231 to 231-

Data Storage in Memory


The Intel family of microprocessors uses the little Endian technique when storing data in memory. This technique stores the least significant byte of data in the low memory address and the most significant byte in the high memory address. Figure 4.4 below shows how the data FA3BH is stored in memory starting at address 0000EH.

Address

Content Binary

Content Hexadecimal

00010H 0000FH 0000EH 0000DH 1111 1010 0011 1011 FA 3B Figure 4.4

Data Movement
The move (MOV) instruction will be used to illustrate the addressing modes available in the real-mode programming of the 80386 family of microprocessors. This Instruction can be used to move, actually copy, data between registers and/ or memory. The general syntax is: Mov destination, source The destination can be a register or a memory address where the data will be stored. While the source can be a register, a memory address, or an immediate value

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KS30103 Microprocessor
Example 4.1 Mov BL, 23 ; Store the number 23 decimal in the BL register

Mov AL, 10010010B ; The binary number 10010010 is stored in the AL register mov cl, 0F3H ; The hexadecimal number F3 is stored in CL register Mov AX, BX ; The content of the BX register is copied into the AX register

Mov DX, 7234O ; The Octal number 7234 is stored in the DX register mov BX, 'AB'; The ASCII code for the letters A and B are stored in the BX Register mov BX, AB Self- Test Questions 1) What is the ASCII code for the 'Intel 80386'? a) b) c) 2) 3) What 496E74656C203830333836H 696E74656C203830333836H 696E74656C3830333836H is the alphanumeric data represented by the ASCII code

696E74656C203830343836H What is the Decimal equivalence of the packed BCD byte 10010111? a) b) c) 4) a) b) 5) a) b) c) 79 97 151 136 -120 256 255 127

What is the Decimal equivalence of the signed integer 10001000?

The largest unsigned integer that can be stored a single byte is?

Review Questions
I. What is the largest memory that can be accessed by the 80386 microprocessor in real mode? II. List the 4 data registers and briefly explain their usage III. List the 4 index and pointer registers and briefly explain their usage IV. List the 6 segment registers and briefly explain their usage V. Explain the usage of the Carry flag VI. Contrast the flat and segmented addressing techniques

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KS30103 Microprocessor
VII. VIII. Explain the 80386 real-mode memory addressing scheme Show how the data 'Intel 80386' is stored in memory starting at address 00FC0H

IX. Show how the signed integer -512 is stored as a word in memory starting at address 00FFFH X. Show how the unsigned integer 234 is stored in memory starting at address 0F000H A. As unpacked BCD B. As packed BCD C. As binary

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KS30103 Microprocessor

ADDRESSING MODES

Objectives
1. Explain flat and segment addressing techniques 2. Explain the 80386 real mode addressing schemes

Memory Addressing
Memory can be addressed in two ways: 1. Segment Addressing as used by Intel 2. Flat Addressing as used by other microprocessor manufacturers Segment Addressing Segment addressing scheme used on the Intel 8086 and later Intel microprocessors where all memory references are formed by adding a 16 bit offset to a 16 bit base address held in a segment base registers. Each instruction has a default segment, which determines which segment register is used. Special prefix instructions allow this default to be overridden. The effect is to segment memory into blocks. Blocks may overlap either partially or completely, depending on the contents of the segment registers but normally they would be distinct to give access to the maximum total range of addresses. Flat Addressing The memory architecture in which any memory location can be selected from a single contiguous block by a single integer offset is called flat addressing. A flat address space greatly simplifies programming because of the simple correspondence between addresses (pointers) and integers. 80386 Real Mode Memory Addressing In real mode, the 80386 can address up to 1M bytes of memory. Thus, the address space in real mode ranges from 00000H to FFFFFH. The memory is divided into two sections: a

dedicated-use section and a general-use section. The dedicated-use section occupies the

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KS30103 Microprocessor
address space from 00000H to 003FFH and is reserved for the storage of the microprocessor interrupt-table and cannot be used for the storage of program or data. While, the general-use section uses address range from 00400H to FFFFFH and is used for the storage of program and data. As mentioned earlier, the Intel microprocessor use segmented addressing technique. Thus, The general-use section of memory is divided into blocks called segment. Each segment is 64K-byte. The segments can be contiguous, adjacent, disjointed or even overlapping. As the 386

microprocessor has 6 segment registers, only 6 segments can be active at any given time. Thus, the total memory that can be active at any given time is 6 x 64 for a total of 384K-byte. To address a memory location, a logical address consisting of a segment address and an offset (displacement) address is specified. The actual address (Physical address) is obtained by appending 0H to the segment address and adding it to the offset address. If the offset address generated by combining the contents of two registers is bigger than FFFFH the extra bit is ignored. A memory address can only begin at a 16-byte boundary in the memory system. This 16- byte address is sometimes called a paragraph. Table 5.1 shows few examples of logical and physical addresses.

Segment 1000H 23FBH 0FF1H

Offset 1234H FAB3H 1324H

Logical Address 1000:1234H 23FB:FAB3H 0FF1:1324H

Physical Address 10000H +1234H =11234H 23FB0H + FAB3H = 33A63H 0FF10H + 1324H = 11234H

Table 5.1 Segments and their Default Offset Registers As mentioned earlier, the logical address is formed from a segment address held in a segment register and an offset address. The offset address is obtained from one of the general purpose or special purpose registers or from a combination of both depending on the type of access to

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KS30103 Microprocessor
be performed by the microprocessor. Each segment register has a default offset register as shown in table 5.2 below. This default segment-offset relationship can be overridden for certain operations by specifying the name of the segment to be used in front of the offset register.

Type of operation

Offset

Default Segment

Comment

Instruction Stack Data and String Source

EIP ESP, EBP

CS SS

Cannot be changed

EAX, EBX, EDX, ESI, DS EDI

Can

use

any

other

data segment ES Cannot be changed

Destination String Table 5.2

EDI

Addressing Modes
The Intel 80386 family of microprocessors supports several addressing techniques in real-mode programming. The following addressing modes can be used in the real-mode: Register addressing Immediate addressing Direct addressing Register indirect addressing Base plus index addressing Register relative addressing Base relative plus index addressing Scaled index addressing

Register Addressing The register-addressing mode is very simple. It allows data to be moved between the 80386 registers. In this mode:

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KS30103 Microprocessor
1. The source and destination of the data is an 80386 register such as AH, AL, BH, BL, CH, CL, DH and DL or their 16-bit counterparts i.e. AX, BX, CX, DX, SP, BP, SI and DI. In addition, the 32 bit registers EAX, EBX, ECX, EDX, ESP, EBP, ESI, EDI, and EDI can also be used. 2. Never mix registers of different sizes. For ex: MOV AX, BL is not allowed because BL is an 8bit register while AX is a 16-bit register 3. Segment to segment register is not allowed. For ex: MOV CS, DS is not allowed 4. The code segment register (CS) cannot be used as a destination register Example 5.1 Mov AX, CX ; the content of CX register is copied into the AX register Mov CS, AX ; Invalid the code segment register cannot be a destination Mov DS, AX ; the content of AX register is copied into the DS register Immediate Addressing The immediate addressing mode allows a constant value to be loaded into a register or to be stored in memory. The constant value is included in the instruction immediately after the destination. In this mode: 1. The source data is included in the instruction. 2. The data is constant (cannot change between program runs) 3. The data can be in DECIMAL, BINARY, HEXADECIMAL, or CHARACTER 4. The destination can be a register or a memory location Example 5.2 Mov AX, 3 ; the decimal value 3 is stored into the AX register

Mov List, 0FFh; the hexadecimal value FF is stored into the memory location given by the label list Mov CH, 11001001b Mov AX, 'a' ; the binary value 11001001 is stored into the CH register

; the ASCII code of the letter a is stored in the AX register

Direct Addressing There are two basic forms of direct addressing:

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KS30103 Microprocessor

AX

xxxx 7A a) F3 Memory List

7AF3H 7A b) F3

Figure 5.2

1.

Direct Addressing Between Memory And Accumulator a) Transfers data from a memory location in the data segment and the accumulator (AL or AX or EAX) b) The address of the memory location can be specified by a variable (symbolic memory location) or can be given as direct memory address in some assembler

2.

Displacement Addressing a) Transfers data from a memory location in the data segment and any of the general-purpose registers including the accumulator. b) The address of the memory location can be specified by a variable (symbolic memory location) or can be given as direct memory address in some assembler

The two forms are identical except for the length of the generated machine code instruction. Example 5.3 Mov AX, list ; A word is copied from the memory location list to the AX register

Mov name, BX ; the content of the BX register (a word) is copied to the memory starting the memory address given by the name label It is important to note that both labels (list and name) must have been declared in the data segment before being used. Figure 5.2 below shows the AX register and the memory content at address list a) before and b) after the Mov AX, list instruction is executed.

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KS30103 Microprocessor
Register Indirect Addressing The direct addressing method discussed earlier is good if you want to read or write a single value to the memory. However, when several values (a vector or a column) is to accessed the register indirect addressing is more appropriate than the direct method. This is achieved by loading the offset of the vector or column (a single dimension array) into one of the base registers and then incrementing it in a loop to access the other elements. Any of the following base registers: BX, BP, DI, and SI can be used. The BX, DI, and SI registers use the data segment by default. While the BP register uses the stack segment by default Example 5.5 Mov AX,[BX] ; The word whose address in the BX register is copied into AX Mov list, byte ptr[SI] ; copy the byte addressed by the content of SI into the memory location addressed by list. Figure 5.3 shows the content of memory and registers a) before and b) after the Mov AX, [BX] instruction is executed. Assuming DS = F000 then physical address = F0000+F001 = FF001

AX BX a)

xxxx F001 7A F3 Memory FF002 FF001

7AF3H 7A b) F3

DS = F000

Figure 5.3

Base-Plus-Index Addressing The Base plus index addressing method is another indirect addressing method that allows access to two-dimensional arrays (table). In this method, two registers are required: a base register such as BX and BP (SP cannot be used) and an index register such SI and DI. One register will be used as the base and the other as the offset. The effective address (physical

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KS30103 Microprocessor
address) is obtained by adding the Base register and the Index register to the default data segment register. The offset of the table should be loaded into the base register and then incrementing it in a loop and to load the offset of the first element into the index register and then incrementing it in an inner loop to access the other elements. Example 5.6 Mov AX,[BX+DI] ; The word stored at the memory address DS:BX+DI is copied into the AX register. Figure 5.4 shows the contents of memory and registers a) before and b) after the instruction Mov AX, [BX+DI] is executed assuming DS = F000

AX BX DI

xxxx F001 00A3 Memory a) Figure 5.4 DS = F000 7A F3 FF0A5 FF0A4

7AF3H F001 00A3 7A F3

b)

Register Relative Addressing This addressing technique is similar to the base plus index addressing technique described earlier except that here only one register (an index or a base register) is used compared with two registers (an index and a base register). This technique can address Data in a segment of memory by adding the displacement to the content of a base or index register like (BP, BX, DI, and SI). Thus, it can be used to access data stored in table (array) by: 1. Loading the offset of the table into the displacement (a variable) and 2. Loading the offset of the first element of the table into one of the base registers and then incrementing it in a loop to access the other elements

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KS30103 Microprocessor
Example 5.7 Mov AX, [BX+100] ; copy a word from the memory addressed by DS:BX+100 to the AX register Mov CX, list[DI] ; copy a word from the memory addressed by DS:list+DI to the CX register Figure 5.5 shows the content of memory and registers a) before and b) after the Mov CX,list[DI] is executed. Assuming that DS = 1000H and list = F000H. Thus, the physical memory address of this instruction is DS*10+list+DI = 10000+F000+00A3 = 1F0A3H.

CX DI

xxxx 00A3 BA 3F Memory a) Figure 5.5 1F0A4 1F0A3

BA3F 00A3 BA 3F

DS = 1000 and list = F000

b)

Base Relative plus Index Addressing In this technique, adding the content of a displacement (offset) to a base register and an index register forms the physical address. Thus, it can be used to access data stored in table (one or two dimensions array) by: 1. Loading the offset of the table into the base registers and then incrementing it in a loop and 2. Loading the offset of the first element into the index register and then incrementing it in an inner loop to access the other elements. Thus, it can be seen that this technique is almost identical to the base-plus-index addressing mode except for the addition of the displacement. The addition of the displacement allows the addressing of 3 dimensional table or arrays.

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KS30103 Microprocessor
Example 5.8 Mov AX,list[BX+DI] ; The word stored at the memory address DS:list+BX+DI is copied into the AX register. Figure 5.6 shows the contents of memory and registers a) before and b) after the instruction Mov AX, list[BX+DI] is executed assuming DS = F000 and list = 0100. Thus, the physical memory addressed by this instruction is DS*10+list+DI+BX = F0000+100+A3+C300 = FC4A3.

AX DI BX

xxxx 00A3 C300 BA 3F FC4A4 FC4A3

BA3F 00A3 C300 BA 3F

Memory a) Figure 5.6 DS = F000 and list = 0100 b)

Self-Test Questions 1) The 80386 microprocessor uses: a) b) c) 2) a) b) c) 3) Flat addressing techniques Segment addressing techniques All of the above 0000H to 003FFH 00000H to 003FH 00000H to 003FFH

In real-mode, the memory-address range reserved for the interrupt table is?

What is the total active memory that can be accessed by the 80386DX microprocessor in real-mode? a) b) c) d) 256K-byte 384K-byte 1M-byte None of the above 222F3H

4)

What is the physical address for the logical address 1234:FFB3? a)

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KS30103 Microprocessor
b) c) 5) a) b) c) d) 6) a) b) c) d) 22F23H None of the above CS:IP CS: BP DS:IP None of the above Direct Addressing Immediate Addressing Register Addressing Register Indirect Addressing

Which pairs of registers are used to hold the address of instructions in memory?

Which addressing mode is used in the instruction Mov Ax, [BX]

Review Questions
1. List 3 addressing modes and give an example of each 2. If you need to sum the marks obtained by a group of students for the microprocessor class, which addressing modes are suitable and why?

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KS30103 Microprocessor

ACCESSING SYSTEM HARDWARE

Outcomes
1. Explain the 3 methods used for accessing the hardware 2. Use the DOS function calls to access the hardware

Fundamentals
You can access the PC system hardware at one of three general levels from assembly Language. Programming the hardware directly Use ROM BIOS routines to access the hardware Use MS-DOS calls to access the hardware.

Each level of system access has its own set of advantages and disadvantages. Programming the hardware directly 1) Programming the hardware directly offers two advantages over the other schemes: 2) Control and Efficiency.

Programming the hardware directly has its drawbacks. The needs to create different versions of the same program to work with the same hardware type (monitor for example) produced by different manufacturers

Use ROM BIOS The Basic Input Output System, or BIOS provide a hardware-independent interface to various devices in the IBM PC system. For example, one of the BIOS services is a video display driver. By making various calls to the BIOS video routines, your software will be able to write characters to the screen regardless of the actual display board installed. The BIOS allows you to manipulate devices in a very low level fashion

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KS30103 Microprocessor
Use MS-DOS MS-DOS provides a high-level interface to many devices. This high-level interface greatly reduces the amount of effort in accessing the hardware. Accessing the hardware using BIOS or DOS call requires the use of software interrupts

What is an Interrupt?
1. An interrupt is a signal that tells the CPU to temporarily stop what it is doing and go do something else. 2. Interrupt can be either External or Internal 3. External interrupts are generated by external hardware devices. While Internal interrupts are generated by a running program

Invoking an Interrupt
There are 256 different interrupts numbered from 0 to 255. A program can invoke any of these interrupts with a special instruction, known as a INT, and is given the number of the interrupt. Thus an INT 21h instruction invokes interrupt number 33 decimal. In real mode, the lowest 1024 bytes of memory are reserved for a table (IVT, Interrupt Vector Table) containing the addresses for each of the 256 possible interrupts. When an interrupt occurs (hardware or software), the processor multiplies its number by 4 and looks at the resulting memory location to find the address of the piece of code which handles the interrupt. It then places the current address in the program and the processor flags on the stack, and jumps to the beginning of the interrupt handler. When the interrupt handler finishes, it invokes a special instruction to return from the interrupt. This instruction takes the previously saved flags and program address off of the stack and places them back in the appropriate registers in the CPU. The interrupt handler has to be careful to preserve any registers that it uses which are not used to communicate results to the program that invoked the interrupt.

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KS30103 Microprocessor
If the interrupt can be triggered by a hardware interrupt (only certain ones can on IBM PC's, XT's, and AT's), then the interrupt handler has to preserve ALL registers, since the interrupt could have happened anywhere. ACCESSING THE BIOS The IBM PC BIOS uses software interrupts to accomplish various operations. Most of these routines require various parameters in the 80x86's registers. Some require additional parameters in certain memory locations.

Ms-Dos Calling Sequence


MS-DOS is called via the int 21h instruction. To select an appropriate DOS function, load the ah register with a function number before issuing the int 21h instruction. Most DOS calls require other parameters as well. Generally, these other parameters are passed in the CPU's register set. Terminate Program Execution Function (ah): Entry parameters: Exit parameters: 4Ch al - return code Does not return to your program

This is the function call normally used to terminate your program. It returns control to the calling process. A return code can be passed to the calling process in the al register. Exactly what meaning this return code has is entirely up to you.

Display a Character String Function: AH = 09 Entry Parameter: DS:DX = Address of the character string Description: This function displays a string of characters on the screen. The address of the string should be in DS:DX register pair. The string must be terminated with the $. The string can be of any length and may contain control characters.

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KS30103 Microprocessor
Buffered Keyboard Input Function: AH = 0A Entry Parameter: DS:DX = address of a keyboard input buffer Description: The first byte of the buffer must be the size of the buffer, which can be up to 255 bytes. The second byte is filled by the function when it returns. It contains the number of character typed. The remaining bytes contain the typed characters followed by a carriage return (0D).

This function continues to read the keyboard until either the buffer is filled or the carriage return (Enter key) is pressed. The program EX6_1.asm shown in Figure 6.1 is an example of using DOS function calls to access the hardware. The program first displays Message 1, What

is your name

?, is

on

the screen then waits for the user to type his/her name. Then it displays Message 2, It

nice to meet you, before placing a dollar sign $ at the end of the stored name and then
displaying it after Message 2.

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KS30103 Microprocessor

; EX6_1.ASM ; input the name and display a message .MODEL SMALL .stack 200h .DATA message1 DB 'What is your name ? $' nam db 32, 33 dup(0) message2 db 10,13,'It is nice to meet you $' .CODE START: mov ax,seg message1 ;get segment of message1 mov ds,ax ; put it in ds mov dx, offset message1 ; get offset of message1 mov ah,09h ; display message1 int 21h mov dx,offset nam ; get offset of name mov ah,0Ah ; get name from user int 21h mov ah,09h mov dx,offset message2 ;get offset message2 int 21h ; display message2 mov DI,offset nam ; get offset of name inc di ; point to number of character entered mov bl,[di] ; get no of character mov bh,0 ; clear bh, bx = no of character inc di mov BYTE PTR [Bx+di],'$'; put '$' at end of string mov dx,di ; offset of name in dx mov ah,09h ; display name int 21h mov ax,4c00h ;Returns control to DOS int 21h ; END START

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KS30103 Microprocessor

Self-Test Questions 1) The advantages of accessing the hardware by direct programming are: a) b) c) d) 2) a) b) c) 3) a) b) c) d) Speed and efficiency Control and Speed Control and Efficiency None of the above Use interrupts Use DOS function calls None of the above Use 1 Kbytes of memory Has 256 interrupts All of the above None of the above

The Access the hardware using DOS or BIOS, you need to:

In real mode, the interrupt table

Review Questions
1. List 3 addressing methods of accessing the hardwires 2. List one advantage and one disadvantage of each of the three methods listed in 1 3. Draw a flowchart for the program given in Ex6_1.asm

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KS30103 Microprocessor

PROGRAM CONTROLS

Outcomes
1. Ability to write assembly programs that performs selection 2. Ability to write assembly programs that performs Iteration

Fundamentals
The Jump Commands The jump commands can be used to control of the flow of statements execution within a program There are two main groups of jump commands:- Conditional and Unconditional jumps

The Unconditional Jump


The general syntax of the unconditional jump is: JMP [short/near/far] label There are 3 types: - Short, Near and Far jumps For short jump the label must be within +127 or -128 bytes from the JMP label instruction For near jump the label must be within 32 Kbytes from the JMP label instruction For far jump the label can be anywhere in the real memory. The far jump can be obtained by:- using the FAR PTR directive or by defining the label as an external label using the EXTRN directive

CONDITIONAL JUMPS
Conditional jumps are either short or near jumps The Carry (C), Sign (S), Zero (0), Parity (P), and Overflow (O) flags are tested to see if they are set (equal 1) or reset (equal 0) There are conditional jumps commands for signed and unsigned numbers

Unsigned Conditional Transfers

Mnemonic Condition Tested JA/JNBE JAE/JNB JB/JNAE JBE/JNA JC JE/JZ (CF or ZF) = 0 CF = 0 CF = 1 (CF or ZF) = 1 CF = 1 ZF = 1

"Jump If..." Above/not below nor equal Above or equal/not below Below/not above nor equal Below or equal/not above Carry Equal/zero

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KS30103 Microprocessor
JNC JNE/JNZ JNP/JPO JP/JPE CF = 0 ZF = 0 PF = 0 PF = 1 Not carry Not equal/not zero Not parity/parity odd Parity/parity even

Signed Conditional Transfers

Mnemonic JG/JNLE JGE/JNL JL/JNGE JLE/JNG JNO JNS JO JS

Condition Tested "Jump If..." ((SF xor OF) or ZF) = 0 Greater/not less nor equal (SF xor OF) = 0 Greater or equal/not less (SF xor OF) = 1 Less/not greater nor equal ((SF xor OF) or ZF) = 1 Less or equal/not greater OF = 0 Not overflow SF = 0 Not sign (positive, including 0) OF = 1 Overflow SF = 1 Sign (negative)

Since the conditional jump commands depend on the state of the flags, the question is how to set or reset the values of these flags to make the jump instruction transfers control to the specified location within the program so that we can make selection and iteration? There are several ways of setting the values of these registers. The most common method of setting the values of the flags is by using logical and arithmetic command. The most common used command for performing program control is the Compare command.

Compare
1. 2. 3. 4. The CMP instruction compares two binary data items by subtracting the source from the destination. Neither the value of the source nor the destination change by this command. Only the status of the flags will be changed. Almost all addressing methods except memory-to memory and segment registers cannot be used This command is normally used before a conditional jump to check whether a condition is true or false The general syntax of this command is: CMP destination, source Where: destination can be a register or a memory variable. Source can be a register, a memory variable, or an immediate value.

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KS30103 Microprocessor

Selection
The program vote.asm shown in Figure 6.1 shows how to use the compare (CMP) command and the conditional jump instructions to perform a selection. The flowchart of the program is shown in Figure 6.2.
; vote.asm .MODEL SMALL .STACK 200h .DATA Prompt db 13,10,"Type your age please (0 to 99) $" age db 3, 4 dup(?) yesmessage db 10,13, "Congragulation, you are eligible to vote $" nomessage db 10,13, "Sorry, you are under age $" .CODE START: ;display prompt mov ax, seg prompt ; mov ds,ax mov ah,9 mov dx,offset Prompt int 21h ;print a message ;input the age mov ah,0ah mov dx,offset age int 21h ;get the age ;move age to ax mov bx, offset age mov ah,[bx+2] ;MSB in ah mov al,[bx+3] ;LSB in al ; check if age is more than 21 cmp ax,'21' ; is age > 21 jae yes ;yes display yesmessage mov dx,offset nomessage ; no display nomessage jmp dispmessage yes: mov dx,offset yesmessage dispmessage: mov ah,9 ; display message int 21h ;return to dos mov ax,4c00h ;Returns control to DOS int 21h ; END START

Figure 6.1 The Source Code for Vote.asm

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KS30103 Microprocessor
Start Display Enter your age

Input Age

Is Age > 21?

No

Display Sorry

Yes Display Congratulation

End Figure 6.2 Flowchart of the Vote.asm Program Iteration


The program ASCII.asm shown in Figure 6.3 shows how to use the Compare (CMP) and the conditional jump statements to perform iteration, loop. The program makes a loop that repeats itself 256 times to print out the entire ASCII code. The flowchart of the program is shown in Figure 6.4. Another method of making an iteration is by using the LOOP commands. Looping the Loop The loop instructions are conditional jumps that use a value placed in ECX to specify the number of repetitions of a software loop. All loop instructions automatically decrement ECX and terminate the loop when ECX=0. Four of the five loop instructions specify a condition involving ZF that terminates the loop before ECX reaches zero.

The LOOP Instruction


The LOOP command (Loop while ECX Not Zero) is a conditional transfer that automatically decrements the ECX register before testing ECX for the branch condition. If ECX is non-zero, the program branches to the target label specified in the instruction. The LOOP instruction causes the repetition of a code section until the operation of the LOOP instruction decrements ECX to a value of zero. If LOOP finds ECX=0, control transfers to the instruction immediately

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following the LOOP instruction. If the value of ECX is initially zero then the LOOP is executed 2^(32) times.
;ascii.asm .MODEL SMALL .STACK 200h .CODE START: mov cx,0 mov ah,6 begin: mov dl,cl int 21h cmp cx,255 jae done inc cx jmp begin done: .exit END START

; first number in the ASCII table ; DOS function to display a single character ; ascii code of first character ; display it

Figure 6.3 The Source Code for the ASCII.asm Program Syntax: Loop Label

LOOPE
The LOOPE (Loop While Equal) and LOOPZ (Loop While Zero) are synonyms for the same instruction. These instructions automatically decrement the ECX register before testing ECX and ZF for the branch conditions. If ECX is non-zero and ZF=1, the program branches to the target label specified in the instruction. If LOOPE or LOOPZ finds that ECX=0 or ZF=0, control transfers to the instruction immediately following the LOOPE or LOOPZ instruction. Syntax: Loope Label Condition for looping: ECX # 0 and ZF = 1 LOOPNE The LOOPNE (Loop While Not Equal) and LOOPNZ (Loop While Not Zero) are synonyms for the same instruction. These instructions automatically decrement the ECX register before testing ECX and ZF for the branch conditions. If ECX is non-zero and ZF=0, the program branches to the target label specified in the instruction. If LOOPNE or LOOPNZ finds that ECX=0 or ZF=1, control transfers to the instruction immediately following the LOOPNE or LOOPNZ instruction. Syntax: Loopne Label Condition for looping: ECX # 0 and ZF = 0

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EXECUTING A LOOP ZERO TIMES JCXZ (Jump if ECX Zero) branches to the label specified in the instruction if it finds a value of zero in ECX. JCXZ is useful in combination with the LOOP instruction and with the string scan and compare instructions, all of which decrement ECX. Sometimes, it is desirable to design a loop that executes zero times if the count variable in ECX is initialised to zero. Because the LOOP instructions (and repeat prefixes) decrement ECX before they test it, a loop will execute 2^(32) times if the program enters the loop with a zero value in ECX. A programmer may conveniently overcome this problem with JCXZ, which enables the program to branch around the code within the loop if ECX is zero when JCXZ executes. When used with repeated string scan and compare instructions, JCXZ can determine whether the repetitions terminated due to zero in ECX or due to satisfaction of the scan or compare conditions. Syntax: JCXZ Label Condition for looping: ECX = 0 The program ASCII2.asm shown in Figure 6.5 shows how to use the Loop command to perform an iteration. The program makes a loop that repeats itself 256 times to print out the

Start No = 0

Display Char(No)

Is No>255? No No = No + 1

Yes

End

Figure 6.4 Flowchart of the ASCII Program

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;ascii2.asm .MODEL SMALL .STACK 200h .CODE START: mov cx,255 mov ah,6 begin: mov dl,cl int 21h loop begin done: .exit END START

; last number in the ASCII table ; DOS function to display a single character ; ascii code of first character ; display it

Figure 6.5 The Source Code for the ASCII2.asm Program entire ASCII code in reverse order. The flowchart of the program is shown in Figure 6.6

Self-Assessment Questions
1. The jump commands can be classified into 2 groups: _____________ jumps and _______________________ jumps

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2. 3. 4. 5. The number of bytes between the jmp Short label instruction and the label should be between ________________________ and ______________________ bytes The conditional jump can only be ____________ and _____________ The conditional jump statement JA is used with unsigned number, the equivalent conditional jump statement used with signed number is ________________ For the Repeat until loop, the condition that controls the loop is placed at _________ _________________________ of the loop

Review Questions
1. 2. Draw a flowchart and then write the source code for an assembly language program that displays the EVEN numbers from 0 to 100 on the screen The ASCII program shown in Figure 6.3 uses the Compare and conditional jumps commands to display the ASCII codes starting from 0 to 255. You are required to modify the ASCII program so that it uses the Loop command to display the ASCII code 3. Draw a flowchart and then write the source code for an assembly language program that: a. Request the user to enter his or her sex b. If the user is a male then the message Hi Handsome Guy is displayed. If the user is a female, then the message Hi Beautiful Lady is displayed.

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ARITHMETIC AND LOGIC OPERATIONS

Outcomes
1. 2. Ability to write assembly programs that perform arithmetic operations on integers Ability to write assembly programs that perform logic operations

Logic Operations The AND Instruction 1. The AND instruction performs the logical AND operation on the bits of two data items 2. Can be used to clear selected bits of a binary number by using a mask The general syntax is: AND destination, source Where: destination can be a register or a memory variable while source can be a register, a memory variable or an immediate value. However, both source and destination cannot be memory variables. After the operation is completed the destination = destination AND source Example 7.1 and al, 0F0h and num1,00Fh and byte ptr[bx],0F5h and ax, bx The OR Instruction 1. The OR instruction performs the logical OR operation on the bits of two data items 2. Can be used to set selected bits of a binary number by using a mask The general syntax is: OR destination, source Where: destination can be a register or a memory variable while source can be a register, a memory variable or an immediate value. However, both source and destination cannot be memory variables. After the operation is completed the destination = destination OR source Example 7.2 OR al, 0F0h OR num1,00Fh OR byte ptr[bx],0F5h

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OR ax, bx The XOR Instruction 1. The XOR instruction performs the logical XOR operation on the bits of two data items 2. Can be used to invert (complement) selected bits of a binary number by using a mask The general syntax is: XOR destination , source Where: destination can be a register or a memory variable while source can be a register, a memory variable or an immediate value. However, both source and destination cannot be memory variables. After the operation is completed the destination = destination XOR source Example 7.3 XOR al, 0F0h XOR num1,00Fh XOR byte ptr[bx],0F5h XOR ax, bx The NOT Instruction The NOT operation performs the logical NOT operation. Thus, it invert or performs the 1s complement on the binary data item The general syntax is: NOT destination. Where: The destination can be a register or a memory variable. After the command is completed the destination = 1s complement of the destination. Example 7.4 NOT num1 NOT byte ptr[bx] NOT ax The TEST Instruction 1. The TEST instruction performs a logical AND operation on the destination and the source. However, unlike the AND operation only the flags are changed 2. Like the CMP command, this command is normally followed by a conditional jump instruction 3. All the addressing mode that can be used for the AND instruction can be used for this command The general syntax is: TEST destination, source

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Where: destination can be a register or a memory variable. Source can be a register, a memory variable, or an immediate value. Example 7.5 test al, 0F0h test num1,00Fh test byte ptr[bx],0F5h test ax, bx The BT Instruction 1. The BT instruction is used to test a single bit by placing it in the carry flag (C) which can then be used to control the flow program execution 2. This command can also be used to clear, set, or complement the bit under test as shown in the table below The general syntax is: BT/BTS/BTC/BTR Operand, location Where: operand can be a register or a memory variable. Location can be a register, or an immediate value representing the location of the bit as an offset from the low-order end of the operand Instruction BT (Bit Test) BTS (Bit Test and Set) BTR (Bit Test and Reset) Effect on CF Effect on Selected Bit CF BIT CF BIT CF BIT (none) BIT 1 BIT 0 BIT NOT(BIT)

BTC (Bit Test and Complement) CF BIT Example 7.6 BT ax, 3 BTS num1, 6 BTC ax, 7 BTR num2, ax The Bit Scan Instructions

The BSF (Bit Scan Forward) and BSR (Bit Scan Reverse) scans a source data item forward or reverse respectively until a 1 bit (a bit whose value is 1) is found. The position where the 1 is found is stored in the destination.

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The general syntax is: BSF/BSR destination, source Where: Destination is a 16-bit register while Source can be a 16-bit register, or a memory variable. Example 7.7 BSF BX,AX BSR BX,num1

Arithmetic Operations
Binary Arithmetic

ADDITION
1. The ADD instruction can be used to perform binary addition on 8, 16, or 32 data bits 2. All the addressing modes discussed earlier can be used. The only types of addition not allowed are memory to memory addition and segment register addition 3. The sign, zero, carry, auxiliary carry, parity, and overflow registers may be changed by the ADD instruction. 4. The ADC (add with carry) performs binary addition on 8, 16, or 32 data bits and add the content of the carry flag to the addition result The general syntax of the ADD command is: ADD destination, source Where: destination can be a memory address, or a register. The source can be a memory address, a register, or an immediate value The result of the addition will be stored in the destination i.e. destination = destination + source Example 7.8 add al, num1 add al,bl add BX, num2 adc cl,num1

INCREMENT ADDITON
The INC instruction is a special form of addition that add a 1 to the value of a memory or a register content The general syntax is: INC destination. The destination can be a memory address or a register

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SUBTRACTION
1. The SUB instruction can be used to perform binary subtraction on 8, 16, or 32 data bits 2. All the addressing modes discussed earlier can be used. The only types of subtraction not allowed are memory to memory subtraction and segment register subtraction 3. The sign, zero, carry, auxiliary carry, parity, and overflow registers may be changed by the SUB instruction. 4. The SBB (subtract with borrow) performs binary subtraction on 8, 16, or 32 data bits and subtract the content of the carry flag from the subtraction result The general syntax of the SUB command is: SUB/SBB destination, source Where: destination can be a memory address, or a register. While, source can be a memory address, a register, or an immediate value The result of the subtraction will be stored in the destination i.e. destination = destinationsource Example 7.9 sub al, num1 sub al,bl sub BX, num2 sbb cl,num1

DECREMENT SUBTRACTION
The DEC instruction is a special form of subtraction that subtract a 1 from the value of a memory or a register content The general syntax is: DEC destination. The destination can be a memory address or a register

MULTIPLICATION
1. The MUL command can be used to multiply unsigned binary data. 2. The IMUL command can be used to multiply signed binary data 3. The multiplicand must be in the accumulator (AL for 8 bits, AX for 16 bits and EAX for 32 bits) 4. The product of the multiplication will be in AX for 8 bits, DX-AX for 16 bits and EDX-EAX for 32 bits 5. The Carry and Overflow flags are cleared if the product is the same size as the multiplicand. However, they are set to 1 if the product is double the size of the multiplicand

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The general syntax is: MUL/IMUL multiplier Where, the multiplier can be a register or a memory address Multiplier 8-bit 16-bit 32-bit Example 7.10 Mul BX Mul al ; DX-AX = AX x BX. The content of AX is multiplied by the content of BX and the result is stored in the register pair DX-AX ; AX = AL x AL Multiplicand AL AX EAX Result AX (16 bit) DX:AX (32 bit) EDX:EAX (64 bit)

DIVISION
1. The DIV instruction can be used to divide unsigned numbers. If the dividend is the same size as the divisor it must be zero extended 2. The IDIV instruction is used to divide signed number. The quotient can be positive or negative while the remainder has the same sign as the dividend. If the dividend is the same size as the divisor it must be sign extended. 3. The dividend is assumed to be double the size of the divisor and also assumed to be in AX if the divisor is 8 bits and in DX-AX for 16 bits divisor and EDX-EAX for 32 bits divisor. 4. The remainder - quotient will be in AH-AL for 8 bits and in DX-AX for 16 bits and EDX-EAX for 32 bits The general format is: DIV/IDIV divisor Where, the divisor can be a register or a memory address. Divisor 8-bit 16-bit 32-bit Example 7.11 Div BX ; The content of the register pair DX-AX is divided by the content of the BX register. The Quotient is stored in AX and the remainder is in DX Div num1 : Assuming num1 is of type byte, the AX is divided by num and the quotient is stored in AL and the remainder in AH. Dividend AX (16 bit) DX:AX (32 bit) EDX:EAX (64 bit) Quotient AL AX EAX Remainder AH DX EDX

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;barith.asm .model small .data num1 db 75 num2 db 130 add12 db ? sub12 db ? mul12 dw ? div12 dw ? mul12S dw ? div12S dw ? .code Start: mov ax,seg num1 mov ds,ax ; set Data Segment mov al,num1 ; load num1 into AL mov bl,num2 ; load num2 into BL add al,bl mov add12,al mov al,num2 ; load num2 into AL mov bl,num1 ; load num2 into BL sub al,bl mov sub12,al mov al,num1 ; load num1 into AL mov bl,num2 ; load num2 into BL mul bl ; multiply num2 by num2 mov mul12,ax ; store result mov al, num1 imul bl mov al, num2 mov ah,0 ; zero extend Al mov bl,num1 div bl mov div12,ax mov al,num2 cbw ;sign-extend AL idiv bl mov div12S,ax .exit end start

Figure 7.1 The Source Code for Barith.asm Programme The program barith.asm shown in Figure 7.1, illustrates the usage of the binary arithmetic instructions

BCD Arithmetic 1. BCD data can be either packed (2 BCD digits per byte) or unpacked (one BCD digit per byte) 2. BCD arithmetic operates on packed BCD only 3. Only addition and subtraction operations can be performed on BCD data stored as 8 bits in the AL register

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4. The DAA (decimal adjust after addition) should be used after the addition operation to adjust the result to BCD 5. The DAS (decimal adjust after subtraction) should be used after the subtraction operation to adjust the result to BCD ASCII Arithmetic 1. ASCII arithmetic operates on ASCII-coded numbers. These ranges in value from 30H (0) to 39H (9) and they are stored as a single byte 2. The AAA (ASCII adjust after addition) is used to adjust the result of ASCII addition to a valid unpacked BCD number 3. The AAS (ASCII adjust after subtraction) is used to adjust the result of ASCII subtraction to a valid unpacked BCD number 4. The AAM (ASCII adjust after multiplication) is used to adjust the result of the multiplication of two unpacked BCD numbers to a valid unpacked BCD number 5. The AAD (ASCII adjust before division) is used to convert a 2 bytes unpacked BCD in AX into a binary number before dividing it by a single byte unpacked BCD number.

;arith.asm ;ASCII and BCD Arithmetic .model small .data bcd1 db 10010011b bcd2 db 45h asc1 db '39' asc2 DB '93' .code Start: ;BCD Arithmetic mov ax,seg bcd1 mov ds,ax mov al,bcd1 add al,bcd2 DAA mov al,bcd1 sub al,bcd2 DAS mov al,asc1 mov ah,0
Figure 7.2 The Source Code for arith.asm

add al,asc2 AAA mov al,asc1[1] mov ah,0 sub al,asc2[1] AAS mov al,asc1 sub al,30h mov bl,asc2 sub bl,30h mul bl AAM mov al,asc1 mov ah, asc1[1] sub ax,3030h AAD mov bl,asc2[1] sub bl, 30h div bl .exit end start

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Self Test Questions

Review Questions

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WORKING WITH STRING DATA

Outcomes
1. Ability to write assembly programs that operate on string data

Fundamentals of String Operations


All string data transfer instructions use the Destination Index (DI) and the Source Index (SI) to address the offset of the destination and the source of the string data respectively. The DI uses the Extra Segment (ES) as the default segment and cannot be changed. The SI uses the Data Segment (DS) by default but can use other segments by using Segment Override. The Direction Flag (D) selects either auto-increment (D=0) or auto-decrement (D=1) for both SI and DI The CLD (clear direction flag) instructions sets D to 0 while the STD (set direction flag) instruction set D to 1 LOADIND A STRING INTO ACCUMULATOR The LODS instruction load the accumulator with data stored at Data Segment offset specified by the SI The instruction can be appended with a B for 8 bits, or a W for a word, or D for double words. Syntax: LODSB/LODSW/LODSD Example 8.1 Loadsb Loadsw Loadsd The byte stored at DS:SI is copied into AL and the value of SI is changed by 1 The word stored at DS:SI is copied into AX and the value of SI is changed by 2 The double-word stored at DS:SI is copied into EAX and the value of SI is changed by 4 STORING A STRING The STOS instruction can be used to store a string placed in the accumulator at the Extra Segment (ES). The Destination Index (DI) register gives the offset. The instruction can be appended with a B for 8 bits, or a W for a word, or D for double words.

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Syntax: STOSB/STOSW/STOSD Example 8.2 Stosb Stosw Stosd The byte in AL is copied to memory addressed by DS:DI. The value of the DI register is changed by 1 The word in AX is copied to memory addressed by DS:DI. The value of the DI register is changed by 2 The double-word in EAX is copied to memory addressed by DS:DI. The value of the DI register is changed by 4 MOVING A STRING The MOVS instruction can be used to move a string of data from the Data Segment (DS) at offset specified by the Source Index (SI) register to a memory location in the Extra Segment (ES) offset given by the Destination Index (DI) register. The instruction can be appended with a B for 8 bits, or a W for a word, or D for double words. Syntax: MOVSB/MOVSW Example 8.3 Movsb Movsw The byte stored at the memory address DS:SI is copied into the memory address ES:DI . The value of both SI and DI is changed by 1 The word stored at the memory address DS:SI is copied into the memory address ES:DI. The value of both SI and DI is changed by 2 REPEATING A STRING DATA MOVEMENT INSTRUCTION The REP prefix can be used in front of any string data movement instruction except the LODS The instruction will be repeated until the CX register becomes equal 0 Each time the instruction is executed the CX register is decremented by 1

Example 8.4 Rep movsb Example 8.5 The program string1.asm shown in Figure 8.1 shows how to use the string commands to fill-in a string (string1) with 10 As i.e. AAAAAAAAAA, then copy the content of one string (string1) to another string (string2) ; repeats the move string byte (movsb) command as long as CX not equal 0

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;string1.asm ; demonstrates the string instructions .model small .data string1 db 10 dup(?) string2 db 10 dup(?) .code Start: ; fill-in string1 with the letter A mov ax, seg string1 mov es,ax mov ds,ax mov di,offset string1

cld mov cx,10 mov al,"A" rep stosb ; move string1 to string2 mov si, offset string1 mov di, offset string2 cld mov cx, 10 rep movsb .exit end start

Figure 8.1 The Source Code for String1.asm Program

STRING COMPARISION
SCAS The SCAS (Scan String) compares the accumulator (AL, AX, EAX) with a byte, word, double word of string block held in the memory The DI is used as the offset for the string data in the Extra segment This command subtract the content of the memory from that of the accumulator and set the flags accordingly As with other string commands, the CX register can be used as a counter with the REP prefix to repeat this command more than once The general syntax is: SCASB/ SCASW/ SCASD to scan a byte, a word, or a double word respectively. CMPS The CMPS compares two data strings held in memory and set the zero flag if the two strings are equals or reset the zero flag if they are not equals. The SI register holds the offset to one data string in the data segment (default) and the DI holds the offset for the second data string in the extra segment. This command can be used to compare bytes (CMPSB) or word (CMPSW) or double word (CMPSD) As with other string commands, the CX register can be used as a counter with the REP prefix to repeat this command more than once

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The general syntax is: CMPSB/ CMPSW/ CMPSD to compare two bytes, two words or two double words respectively. REPEATING A STRING COMPARISON INSTRUCTION The REPE and the REPNE prefixes can be used to repeat any of the string comparison commands These prefixes will repeat the string comparison instruction until either condition1 or condition 2 shown in table 8.1 is true

Table 8.1
Prefix Condition 1 REP REPE/REPZ REPNE/REPNZ Example 8.6 The program Scomp.asm shown in Figure 8.2 shows how to use the string comparison commands to: 1. 2. Search a string for a given character in this case the letter a Compares two strings for equality ECX = 0 ECX = 0 ECX = 0 Termination Condition 2 (none) ZF = 0 ZF = 1

Self-Assessment Questions

Review Questions

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; scomp.ASM illustrate string comparison .MODEL SMALL .stack 200h .386 .DATA string1 db string2 db .CODE START: mov ax,seg string1 mov ds,ax mov es,ax 'how are you today' 'how are you Today'

mov di, offset string1 mov cx, 17 mov al,'a' cld repne scasb mov si,offset string1 mov di,offset string2 mov cx,17 repe cmpsb mov ax,4c00h int 21h END START

Figure 8.2 The Source code for the Program Scomp.asm

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MODULAR PROGRAMMING

Outcomes
1. The ability to describe the operations of the stack 2. The ability to describe the modular programming concept 3. The ability describe the process of passing parameters between the calling program and the called procedure 4. The ability to write assembly language programs that use modular programming

Working with the Stack


What is the Stack? The stack is: A storage area of memory Can be up to 64K segment organized as 32K words. Operates as a Last-In First-Out (LIFO) principle. The stack segment register (SS) is used to hold the base address while the stack pointer (SP) register holds the offset to the stack segment. Initialising the Stack Segment A stack segment can be defined by: 1. The Segment and Ends directive pairs in a full segments program or 2. The .Stack directive in a model program Example 9.1 The code segment below defines a stack segment with 100 words Stack_seg Stack_seg Example 9.2 The code segment below defines a stack segment with 256 words . stack 200h segment stack "stack" ends DW 100 dup(?)

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10200 SP SS 0200 1000 * 10000

End of Stack

Figure 9.1 A Graphical Representation of Stack Memory with 256 Words Figure 9.1 shows a graphical representation of stack memory segment with 256 words. Notice that when the stack is empty, the stack pointeris pointing at the top of the stack and when the stack is full it is pointing to the bottom of the stack Usage of Stack Memory To store the return address (the values of the CS: IP) during procedures calls. To pass parameters between calling programs and called procedures To return values from called procedures to the calling programmes

Stack Operations There are only two operations that can be performed on the stack: Placing data on the stack (PUSH) and removing data from the stack (POP)

PUSHING DATA ONTO THE STACK


1. The PUSH instruction places 2 or 4 bytes of data on the stack depending on the size of the register being pushed. 2. The general syntax is: PUSH source. The source can be a value, a register or a memory variable however, the size of the source must be an integer multiple of words. The push instruction place the source at the current position of the stack pointer and then decrements the stack pointer by the number of words in the source 3. There are two variations to the push command. PushA and PushAD push the contents of the 16-bit and 32-bit registers respectively on the stack. The PushF and PushFD push the contents of the 16-bit and 32-bit flag register respectively. Example 9.3

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push num1 push num2 push ax push 45 pusha pushad pushf

POPING DATA FROM THE STACK


1. 2. The POP instruction removes 2 or 4 bytes of data from the stack depending on the size of the register being poped. The general syntax is: POP destination. The destination can be a register or a memory variable however, the size of the destination must be an integer multiple of words. The pop instruction removes data at the current position of the stack pointer and place it in the destination and then increments the stack pointer by the number of words removed 3. There are two variations to the pop command. PopA and PopAD pop the contents of the 16-bit and 32-bit registers respectively from the stack. The PopF and PopFD pop the contents of the 16-bit and 32-bit flag register from the flag respectively. Example 9.4 popf popad popa pop cx pop num1 pop num2

WHAT IS A PROCEDURE
1. A procedure is a small program that normally performs a single task

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2. In assembly language, the PROC and ENDP directives delimit a procedure. 3. The PROC directive indicates the beginning of the procedure 4. The ENDP directive indicates the end of the procedure 5. The RET command returns control to the calling program. Therefore, it must be at the end of the procedure just before the ENDP directive 6. A procedure can be:- A near procedure i.e. the procedure and the calling program are in the same code segment or a far procedure where the procedure and the calling program can be in different code segments Creating a Procedure The general form of a procedure is: procname PROC [NEAR/FAR]

Assembly instructions RET procname ENDP

Where: procname is a unique name for the procedure CALLING A PROCEDURE A procedure is executed (called) by the CALL directive When a near procedure is called, the CALL directive PUSHES the Instruction Pointer (IP) onto the stack and load the IP with the offset address of the called procedure When a far procedure is called, the CALL directive PUSHES the Instruction Pointer (IP) and the Code Segment (CS) onto the stack. And then load the IP with the offset address and the CS register with the segment of the called procedure When the execution of a procedure is completed, the RET instruction POP the IP address from the stack for near procedure or the IP and CS for a far procedure

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Example 9.5 Figure 9.2 shows an example of near procedure, addbcd. The procedure adds the contents of the BX, CX, and DX registers and stores the content in the AX register. The procedure is place at the end of the calling program, add3.asm.

;add3.asm ; a program to add 20+30+50 .model small .stack 100h .code Start: mov bx,20 mov cx,30 mov dx,50 call addbcd .exit

; A procedure that adds BX, CX, and DX. ;The results is stored in AX addbcd proc add bx,cx ; add bx and cx adc bx,dx ; add dx to the sum of bx and cx mov ax,bx ret addbcd endp end start

Figure 9.2 The Source Code for the Add3.asm Program SAVING THE STATE OF THE REGISTERS

Why?
Any register that will be changed by the called procedure must be saved before it is changed by the procedure and then must be restored to its original value before the calling program resumes. If the state of the machine is not preserved during procedure calls it may results in unpredictable behavior. Example 9.6 The program shown in Figure 9.3 is supposed to print 10 lines, each line having 40 dash (-) characters. Try it!

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;rsave.asm. Illustrate the need ; to save the registers .model small .stack 100h .code Start: mov cx, 10; number of lines Line: call Printline mov ah,6 ; mov dl,13 int 21h ; next line mov dl,10

int 21h loop Line .exit Printline proc near mov ah,6 mov cx,40 ; no of characters PLine: mov dl,0c4h int 21h ; print character loop Pline ret Printline endp end start

Figure 9.3. The Source Code for Rsave.asm Program

How?
Having established the need to save the state of the machine between procedure calls, the next question is how to do that? The state of the machine can be saved by: The called procedure or The calling program

Saving the state of the Registers in the Procedure


1. At the beginning of the procedure, all those registers that will be used by the procedure should be pushed onto the stack. 2. Before the procedure returns, the registers are poped from the stack in reverse order. Example 9.7 Figure 9.4 shows the source code for Rsaves.asm program. In this program, all the registers used by the printline procedure are saved by the procedure by pushing them onto the stack just at the beginning of the procedure and then restored back by poping them from the stack in reverse order just before the procedure returns.

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;rsaves.asm shows how registers ;are saved by the proceudre .model small .stack 100h .code Start: mov cx, 10 ; number of lines Line: call Printline mov ah,6 ; mov dl,13 int 21h ; next line mov dl,10 int 21h loop Line .exit

Printline proc near Push cx ; save registers Push ax Push DX mov ah,6 mov cx,40 ; no of characters PLine: mov dl,0c4h int 21h ; print character loop Pline Pop DX pop ax pop cx ; restore registers ret Printline endp end start

Figure 9.4. The Source Code for Rsaves.asm Program

Saving the state of the Registers in the Calling Program


1. 2. Before the procedure is called, all those registers that will be used by the procedure should be pushed onto the stack. After the procedure returns, the registers are poped from the stack in reverse order.

Example 9.8 Figure 9.5 shows the source code for Rsavep.asm program. In this program, all the registers used by the printline procedure are saved by the program by pushing them onto the stack just before the procedure is called and then restoring back by poping them from the stack in reverse order just after the call procedure.

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;rsavep.asm shows how registers ;are saved by the proceudre .model small .stack 100h .code Start: mov cx, 10 ; number of lines Line: Push cx ; save registers Push ax Push DX call Printline Pop DX pop ax pop cx ; restore registers mov ah,6 ; mov dl,13

.exit Printline proc near mov ah,6 mov cx,40 ; no of characters PLine: mov dl, 0c4h int 21h ; print character loop Pline ret Printline endp end start

int 21h mov dl,10 int 21h loop Line

; next line

Figure 9.5. The Source Code for Rsavep.asm Program

Having used both methods, which method do you think is better?

Passing Parameters
Most procedures require some input data from the calling program and return some values to the calling program. Parameters are values that you pass to and from a procedure. HOW TO PASS PARAMETER Parameters can be passed to and from a procedure by: 1. Value 2. Reference 3. Name 4. Value-Returned

Pass by Value
A parameter passed by value is just that - the caller passes a value to the procedure. Pass by value parameters are input only parameters. That is, you can pass them to a procedure but the procedure cannot return them. Since you must pass a copy of the data to the procedure, you should only use this method for passing small objects like bytes, words, and double words

Pass by Reference
To pass a parameter by reference, you must pass the address of a variable rather than its value. In other words, you must pass a pointer to the data. The procedure must de-reference

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this pointer to access the data. Passing parameters by reference is useful when you must modify the actual parameter or when you pass large data structures between procedures.

Pass by Name
Pass by name is the parameter passing mechanism used by macros and text equates. This parameter passing mechanism uses textual substitution on the parameters

Pass by Value-Returned
Pass by value-returned (also known as value-result) combines features from both the pass by value and pass by reference mechanisms. You pass a value-returned parameter by address, just like pass by reference parameters. However, upon entry, the procedure makes a temporary copy of this parameter and uses the copy while the procedure is executing. When the procedure finishes, it copies the temporary copy back to the original parameter.

WHERE TO PASS PARAMETER


Common places that you can pass parameters are:1. Registers 2. Global Memory Locations 3. The stack 4. The Code Streams

PASSING PARAMETER ON THE REGISTER


If you are passing a small number of bytes to a procedure, then the registers are an excellent place to pass parameters. The registers are an ideal place to pass value parameters to a procedure. Generally, use the general-purpose register for parameter passing.

PASS BY VALUE
The value of the parameter to be passed is placed in one of the general purpose registers where it will be read by the procedure. ;pprv ; shows how to pass ; parameters by value on registers .model small .stack 100h .code Start: mov cx, 40 ; number of characters mov dl, 41h ; character call Printline

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.exit Printline proc near Push cx ; save registers Push dx mov ah,6 PLine: int 21h ; print character loop Pline pop dx pop cx ; restore registers ret Printline endp end start

PASS BY REFERENCE
The main procedure passes the address (reference) of the parameter in one of the generalpurpose registers. ;pprr2 ; shows how to pass parameters ; by reference on registers .model small .stack 100h .data string db 13,10, "Passing parameters by reference $" string2 db 10,13, This is the second string to be passed by reference $ .code Start: Mov ax,seg string Mov ds,ax Mov bx,offset string call Pstring Mov bx,offset string2 call Pstring .exit Pstring proc near Push bx ; save registers Push ax mov ah,6 PLine: Mov dl,[bx] ; character in DL Cmp dl,"$" Je done int 21h ; print character inc bx jmp Pline done:

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pop ax pop bx ; restore registers

ret Pstring endp end start

PASSING PARAMETR ON THE STACK


1. The calling program pushes the parameters on the stack 2. The called procedure pops the parameters from the stack

PASSING THE PARAMETERS BY VALUE


;ppsv ; shows how to pass ; parameters by value on the stack .model small .stack 100h .data ret_add dw ? .code Start: mov cx, 40 ; number of characters mov dx, 41h ; character push cx ; parameters to be passed push dx call Printline .exit Printline proc near Pop ret_add ; return address Pop dx Pop cx ; read parameters Push ret_add Push ax ; save registers mov ah,6 PLine: int 21h ; print character loop Pline pop ax ; restore registers endp

ret Printline end start

;ppsvF .model small .stack 100h .data ipret_add dw ? csret_add dw ? .code

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Start: mov cx, 40 ; number of characters mov dx, 41h ; character push cx ; parameters to be passed push dx call far ptr Printline .exit Printline proc far Pop ipret_add ; return address Pop csret_add Pop dx ; read parameters Pop cx Push csret_add Push ipret_add Push ax ; save registers mov ah,6 PLine: int 21h ; print character loop Pline pop ax ; restore registers ret Printline endp end start A better way, however, is to use the BP (base pointer) register to access parameters passed on the stack. ;ppsvbp ; shows how to pass ; parameters by value on the stack .model small .stack 100h .code Start: mov cx, 40 ; number of characters mov dx, 41h ; character push cx ; parameters to be passed push dx call Printline .exit Printline proc near Push ax ; save registers Push bp Mov bp,sp mov dx,6[bp] mov cx,8[bp] ; read parameters mov ah,6 PLine: int 21h ; print character

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loop Pline pop bp pop ax ; restore registers ret 4 Printline endp end start The maintainability and readability of the program can be improved by using text equates to index the parameters on the stack. ;ppsvbpe ; shows how to pass ; parameters by value on the stack .model small .stack 100h .code Start: mov cx, 40 ; number of characters mov dx, 41h ; character push cx ; parameters to be passed push dx call Printline .exit chr_no equ 8[bp] chr equ 6[bp] Printline proc near Push ax ; save registers Push bp Mov bp,sp mov dx,chr mov cx,chr_no ; read parameters mov ah,6 PLine: int 21h ; print character loop Pline pop bp pop ax ; restore registers ret 4 Printline endp end start

PASSING THE PARAMETERS BY Reference


;ppsrbpe ; shows how to pass parameters ; by reference on the stack .model small .stack 100h .data string db 13,10, "Passing parameters by reference $"

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.code Start:

Mov ax, seg string Push ax Mov ax,offset string push ax call Pstring .exit str_seg equ 6[bp] str_offset equ 4[bp] Pstring proc near Push bp Mov bp,sp Push ax ; save registers Push bx Mov bx,str_offset Mov ds,str_seg mov ah,6 PLine: Mov dl,[bx] ; character in DL Cmp dl,"$" Je done int 21h ; print character inc bx jmp Pline done: pop bx pop ax ; restore registers pop bp ret 4 Pstring endp end start

Passing Parameters by Value using Memory


;ppmv ; Passing parameters by value using memory .model small .stack 100h .data noof_chr db ? chr db ? .code Start: Mov ax,seg chr Mov ds,ax mov noof_chr, 40 ; number of characters mov chr, 41h ; character call Printline .exit Printline proc near

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Push ax Push cx Push dx ; save registers mov ah,6 mov cl, noof_chr mov ch,0 mov dl,chr ; retrieve parameters PLine: int 21h ; print character loop Pline pop dx pop cx pop ax ; restore registers ret Printline endp end start

Passing Parameters by Reference using the Memory


;ppmr ; Passing Parameters by reference using memory .model small .stack 100h .data string db 13,10, "Passing parameters by reference $" string_seg dw ? string_off dw ? .code Start: Mov string_seg, seg string Mov string_off,offset string call Pstring .exit Pstring proc near Push ax ; save registers Push bx Mov bx,string_off Mov ds,string_seg mov ah,6 PLine: Mov dl,[bx] ; character in DL Cmp dl,"$" Je done int 21h ; print character inc bx jmp Pline done: pop bx pop ax ; restore registers ret Pstring endp end start

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Self-Test Questions
Question 1 a) List 4 methods of passing parameters b) List 4 places where parameters can be passed c) Describe the method of passing parameter by value on the register d) Describe the method of passing parameter by reference on the stack e) Describe the method of passing parameter by value on the memory

Review Questions
Question 1 With reference to the program Wcount.asm shown below, answer the followings: a) How many parameters passed from the main program to the procedure? b) Where and how these parameters were passed? c) Show the stack memory just before the first instruction in the procedure is executed d) Show the stack memory just before the instruction mov bx,10[bp] at line 20 is executed e) Show the stack memory just before the ret instruction in the procedure is executed f)

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1. ; wcount.asm 2. .MODEL SMALL 3. .STACK 200h 4. .DATA 5. sentence db "This is a very long sentence that contains many words" 6. .CODE 7. START: 8. mov ax, seg sentence 9. mov ds,ax 10. mov bx,offset sentence 11. push bx 12. call countw

13. .exit
14. countw proc near 15. push dx 16. push di ; save the state of the machine 17. push cx 18. push bp 19. mov bp,sp 20. mov bx,10[bp] 21. mov dx,0 ; no of words 22. mov di,0 ; pointer 23. mov cx,54 ; no of characters 24. begin: 25. cmp byte ptr [bx+di],' ' ; is current character a space 26. je nextcharacter ; yes get next character 27. cmp byte ptr [bx+di+1],' ' ; is next character a space 28. jne nextcharacter ; no, get next character 29. inc dx ; increase no of words by 1 30. nextcharacter: 31. inc di ; check next character 32. loop begin 33. mov 10[bp],dx 34. pop bp 35. pop cx 36. pop di 37. pop dx 38. ret 39. countw endp 40. END START Figure 1. The Source Code for the Wcount.asm Program

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BUS OPERATIONS

The 386 Signals


The 386 DX has 32 address lines and 32 data lines The 386 SX has 24 address lines and 16 data lines Both processors require a +5.0 V power supply and a current ranging from 500mA to 1.0A Each pin is capable of providing 4.0mA for data and address and 5.0mA from other connections. The function of each group of pins is as follows: 1) Address Bus Connections 2) A2 to A31 on the DX (A0 and A1 are encoded as #BE0 - #BE3 bus enable to select either a byte, a word, or a double word). A1 to A23 on the SX (A0 is encoded as #BHE and #BLE bus enable to select either a byte, or a word). Data Bus Connections 3) 4) D0 to D31 D0 to D15 #BE0 - #BE3 Select the access method. A byte, a word or a double word #BHE and #BLE select either a byte or a word

Bank Enable Signal

Memory/#IO. This pin selects a memory device with a logic 1 and an I/O device with logic 0. The address of the I/O device appears on address bus (A2-A15) for the DX and (A1-A15) for SX

5) 6) 7) 8) 9) 10)

Write/#Read. Logic 1 indicates a write operation and logic 0 a read operation Address Data Strobe (ADS) is active (logic 1) whenever a valid memory or I/O address is issued by the processor Reset a logic 1 applied to this pin causes the 386 to begin executing at memory location FFFFFFF0H in the real mode Clock Times 2. The CLK2 pin is connected to an external clock that is twice the operating frequency of the processor Ready control the number of wait states inserted into the timing diagram to lengthen the memory access time Lock becomes 0 whenever any instruction is prefixed with the LOCK: prefix. This is most often used during the DMA accesses

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11) Data/Control (D/C). A logic 1 on this pin indicates that the data bus contains data. While a 0 indicates that the microprocessor is halted or executing an interrupt acknowledge 12) 13) 14) 15) 16) 17) 18) 19) 20) Bus Size 16 bits. The BS16 selects a 32 bits data bus if it is logic 1 and 16 bits data bus for logic 0 Next Address. A logic 0 on the NA pin causes the 386 to output the address of the next instruction in the current bus cycle. This is often done during pipelining the address HOLD a logic 1 on this pin requests a DMA action Hold Acknowledge (HLDA) a logic 1 on this pin indicates that the 386 is currently in a hold condition Coprocessor Request (#PEREQ). A logic 0 on this pin requests the 80386 to relinquish control to the coprocessor. This pin is connected directly to the coprocessor. Busy (#BUSY). This pin is directly connected to the coprocessor. A logic 0 indicates that the coprocessor is busy. Error (#ERROR). A logical 0 on this pin indicates to the 80386 that an error is encountered by the coprocessor. Interrupt Request (INTR). This pin is used by external devices to request a service from the processor. Non Maskable Interrupt (NMI). This pin is normally used by external devices to issue non maskable interrupts. Figure 10.1 shows a diagram of the functional grouping of the 80386DX pins.

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Figure 10.1 The 80386DX Functional Signal Groups The 80386 Internal Clock
CLK2 provides the fundamental timing for the Intel 386 microprocessor. It is divided by two internally to generate the internal processor clock used for instruction execution. The internal clock is comprised of two phases, phase one'' and phase two.'' Each CLK2 period is a phase of the internal clock. Figure 10.2 illustrates the relationship between the CLK2 signal and the internal clock

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Figure 10.2. The Relationship between the Internal Microprocessor Clock and the CLK2 Singal Bus Cycle Definition Signals
The W/R#, D/C#, M/IO#, LOCK# define the type of bus cycle being performed. W/R# distinguishes between write and read cycles. D/C# distinguishes between data and control cycles. M/IO# distinguishes between memory and I/O cycles. LOCK# distinguishes between locked and unlocked bus cycles. The primary bus cycle definition signals are W/R#, D/C# and M/IO#, since these are the signals driven valid as the ADS# (Address Status output) is driven asserted. The LOCK# is driven valid at the same time as the first locked bus cycle begins, which due to address pipelining, could be later than ADS# is driven asserted. The LOCK# is negated when the READY# input terminates the last bus cycle which was locked. Exact bus cycle definitions, as a function of W/R#, D/C#, and M/IO#, are given in Table 10.1

Table 10.1
M/IO# Low Low Low Low High High D/C# Low Low High High Low Low W/R# Low High Low High Low High Bus Cycle Type INTERRUPT ACKNOWLEDGE Does not occur I/O DATA READ I/O DATA WRITE MEMORY CODE READ HALT: SHUTDOWN: Address 2 Address 0 BE0# High Low BE0# BE1# High High BE1# BE2# Low High BE2# BE3# High High BE3# A2-A31 Low Low) A2-A31 MEMORY DATA READ MEMORY DATA WRITE Locked? Yes X No No No No No

High High

High High

Low High

Some Cycles Some Cycles

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Thus, the operations performed by the bus are: 1. 2. 3. 4. 5. 6. Read from Memory Write to Memory Read from IO Devices Write to IO Devices Interrupt Acknowledge Indicates Halt or Shutdown Operations

Each of these operations requires two or more bus states. A bus state is one processor clock period (equivalent to two CLK2 periods) in duration. Thus, the shortest time unit of bus activity is a bus state

Non-Pipelined Read and Write Operations


The status of Next Address (NA#) pin indicates whether address pipelining is used or not. Address pipelining increases the time from address valid to data valid i.e. the device access time without the need to insert wait states. Figure 10.3 shows six two read and two write bus cycles, each consisting of two bus states. The bus states in each cycle are named T1 and T2.

Figure 10.3 Two Non-pipelined Read and Write Cycles with no Wait States 93

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Any memory or I/O address may be accessed by such a two-state bus cycle, if the external hardware is fast enough. Every bus cycle continues until it is acknowledged by the external system hardware, using the READY# input. Acknowledging the bus cycle at the end of the first T2 results in the shortest bus cycle, requiring only T1 and T2. If READY# is not immediately asserted, however, T2 states are repeated indefinitely until the READY# input is sampled asserted.

Pipelined Read and Write Operations


The address pipelining option provides a choice of bus cycle timings. Pipelined or non-pipelined address timing is selectable on a cycle-by-cycle basis with the Next Address (NA#) input. When address pipelining is selected, the address (BE0#BE3#, A2-A31) and definition (W/R#, D/C# and M/IO#) of the next cycle are available before the end of the current cycle. To signal

Figure 10.4 Three Consecutive Pipelined Read Cycles with no Wait States 94

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their availability, the address status output (ADS#) is also asserted. Figure 10.4 illustrates the fastest read cycles with pipelined address timing. Note from Figure 10.4 the fastest bus cycles using pipelined address require only two bus states, named T1P and T2P. Therefore cycles with pipelined address timing allow the same data bandwidth as non-pipelined cycles, but addressto-data access time is increased compared to that of a non-pipelined cycle. By increasing the address-to-data access time, pipelined address timing reduces wait state requirements. For example, if one wait state is required with non-pipelined address timing, no wait states would be required with pipelined address WAIT STATES Wait states are needed if memory access time is longer than the time allowed by the microprocessor. The READY# input controls whether or not wait states are inserted into the timing. The READY# input must be activated during each bus cycle. The READY# signal is sampled at the end of each bus cycle to determine if it is a T2 or TW. If READY# is logic 0 then is T2 and it is the end of the bus cycle. If READY# is logic 1 then it is a TW cycle and the microprocessor continue to test READY# looking for logic 0. Figure 10.5 shows read and write cycles with variable number of wait states INTERLEAVE Interleaved memory can be used to lengthen the access time so that wait states are not required or their number is reduced. An interleaved memory is divided into 2 or 4 parts. When the microprocessor accesses the first location, the interleave control logic generates the address strobe signal of the next location. Interleaving lengthen the access time provided to the memory. The problem with interleaving is that the memory addressed alternately. This does not happen all times during program execution. At a time, the same memory address is read again this requires wait states.

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Figure 10.5 Pipelined Read and Write Cycles with Variable Number of Wait States

Active Bus operations Figure 10.6 State Diagram of Bus Cycles 96

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ADDRESS DECODING

Address decoding is used to: Allow more than one memory chip to be connected to the microprocessor at the same time Solve the mismatch between the number of address lines on the microprocessor and that of the memory chip DECODING TECHNIQUES

MULTIPLEXER DECODERS
The lower order bits are connected to the address bus of all the memory chips The remaining bits are connected to the selection input pins of the multiplexer Each output pin of the multiplexer is connected to the selection pin on one of the memory chip The diagram below shows how to connect eight memory chips with a 4Kbyte capacity each to the 20-bits address bus of a microprocessor

Figure 11.1 Address Decoding using a Multiplexer 97

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The range of addresses that can be decoded by this example is given by: 1111 1111 1111 1xxx 1000 1111 xxxx 0000 1111 xxxx 0000 1111 xxxx 0000 1111 F8000H FFFFFH lowest address Highest address Where x indicates either a 0 or a 1. Thus

PROM DECODERS
The PROM must be pre-programmed with the correct binary bit pattern to select all the memory chips one by one. The location of the address decoding in the PROM dictate the beginning of the memory address being decoded The remaining address inputs on the PROM (Data selection) must be grounded The number of outputs of the PROM determines the maximum number of memory chips that can be decoded. Figure 11.2 shows how to use an 512x8 PROM as an address decoder for an eight memory chips with 8Kbyte capacity connected to 20-bits address bus

Figure 11.2 Address Decoding using EPROM

Figure 11.3 shows the location and the data used for the address decoding of Figure 11.2

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Figure 11.3 The Content of the PROM for the Address Decoding of Figure 11.2

PLD DECODERS Like PROM, the PLD devices (PLA or PAL) must be programmed before it can be used as a decoder. The address space for the decoded memory is selected by the set of Boolean expressions used for the control signal for each memory chip. The number of memory chips decoded is determined by the number of outputs available on the PLD device Figure 11.4 shows how to connect the PAL16L8 as an address decoder to connect eight memory chips with 8Kbyte to a 20-bits address bus. The Boolean expressions for the 8 outputs are: /o1 = a19*a18*a17*a16*/a15*/a14*/a13 /o2 = a19*a18*a17*a16*/a15*/a14*a13 /o3 = a19*a18*a17*a16*/a15*a14*/a13 /o4 = a19*a18*a17*a16*/a15*a14*a13 /o5 = a19*a18*a17*a16*a15*/a14*/a13 /o6 = a19*a18*a17*a16*a15*/a14*a13 /o7 = a19*a18*a17*a16*a15*a14*/a13 /o8 = a19*a18*a17*a16*a15*a14*a13 These equations will generate address space from 1111 0000 0000 0000 to 1111 1111 1111 1111 i.e F000h to FFFFh

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Figure 11.4 Address Decoding using PAL

386 Memory Interface


The 386SX data bus is 16 bits wide and the 386DX is 32 bits wide, while most memory chips have an 8-bits data bus. Thus, the 386 can access 8-bits, 16 bits or 32 bits of data The 386SX address bus has 24 bits and the 386DX has 32 bits and not 20 bits.

Data Bus Control The data bus of the 386Sx is divided into two banks: High bank and Low bank. This allows the 386SX to access 8 bits or 16 bits data. The high bank contains odd memory address while the low bank contains even memory address. The high bank is selected by the BHE# signal and the low bank by the BLE# signal. However, the data bus of the 386DX is divided into 4 banks (bank 0 to bank3). This allows the 386DX to access 8 bits, 16 bits or 32 bits of data. Each bank is selected by a separate bank enable signal (BE0# to BE3#). There are two methods to interface the memory to the 836: 1. Separate bank decoders

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2. Separate Write Strobes

SEPARATE BANK DECODERS


A separate address decoder is used for each bank. A byte in the high bank is selected by BHE# while BLE# selects a byte in the low bank. When both BLE# and BHE# are active a 16 bits (a word) is selected as shown in the truth table below. BHE 0 0 1 1 BLE 0 1 0 1 Function Both banks active, 16-bits (word) data transfer High bank active, 8-bit (byte) data transfer through D8-D15 Low bank active, 8-bit (byte) data transfer through D0-D7 No bank active

Figure 11.5 shows how to use three 74138 3 to 8 line decoder chips to create separate bank decoders to interface 16 memory chips each having a capacity of 64k. The decoded address is 000000h to 0FFFFFh

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Figure 11.5 Interfacing Memory to 386SX using Separate Bank Decoders

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SEPARATE BANK WRITE STROBES This method is more efficient than separate bank decoders discussed earlier as only one decoder is needed for both banks. The decoder can also generate two signals for write strobes, HWR# for the high bank and LWR# for the low bank. These can be generated from the BLE#, BHE#, and MWTC# signals generated by the 386. The HWR# is active (0) when BHE# and MWTC# are both active (0) while LWR# is active (0) when BLE# and MWTC# are both active (0). Thus, the Boolean expressions are: LWR# = BLE# + MWTC# HWR# = BHE# + MWTC#

BLE# MWTC# BHE# Figure 11.6

LWR# HWR#

Thus, the logic circuit to generate the LWR# and HWR# signals from the BLE#, BHE#, and MWTC# is as shown in Figure 11.6

Figure 11.7 shows an example of how to connect two 32Kbyte memory chips to the 386SX. The PAL16L8 is used as a decoder as well as to generate the write strobe signals for both banks. The equations to program the PAL are: ; pins 1 a23 ; pins 11 ;equations /sel = /a23*/a22*/a21*/a20*/a19*a18*a17*/a16 /LWR = /MWTC*/BLE /HWR = /MWTC*/BHE Hwr = mwtc.bhe The above equations generates an address space from 060000h to 06FFFFh 2 a22 12 3 a21 13 LWR 4 a20 14 HWR 5 a19 15 nc 6 a18 16 nc 7 a17 17 MWTC# 8 a16 9 ble# 18 nc 10 GND 19 bc 20 VCC

bhe# sel

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Figure 11.7 Memory Interfacing with the 386SX using Separate Write Strobes

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Self test Questions


Question 1 a) List 3 different methods of address decoding b) List 2 methods of interfacing memory to a 16-bit data bus c)

Review Questions
Question 1 d) Design a memory addressing circuits that use the 74ALS138 to decode a 16-bit address bus to interface 4 ROMs, each is 8Kx8 at address 8000H to FFFFH to an 8-bit data line. e) Design a memory addressing circuit that use the 74ALS138 to decode the 24-bit address bus of the 80386SX to interface 8 RAMs, each 64Kx8 at address 000000H to 07FFFFH to a 16-bit data line.

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INPUT/OUTPUT INTERFACE Port Address


Fixed Port Address: the address is 8-bit supplied with the I/O instruction. The address line A0-A7 contains the address of the I/O device Variable Port Address: the address is16-bit and stored in the DX register. The address line A0-A15 contains the address of the I/O device

I/O Instructions
The IN and OUT instructions can use both Fixed Port Address or Variable Port Address The IN and OUT instructions transfer data (byte, word, or double words) between the accumulator and I/O devices The INS and OUTS instructions use only Variable Port Address The INS and OUTS instructions transfer string data between memory (ES:DI for the INS and DS:SI for OUTS) The REP prefix can be used with both INS and OUTS to repeat these instructions

Isolated and Memory-Mapped I/O


ISOLATED I/O Only I/O instructions can be used for I/O operations The I/O address is isolated from the memory address Separate control signals for I/O operations are required The I/O space consists of 64K bytes, it can be divided into 64K 8-bit ports, 32K 16-bit ports, or 16K 32-bit ports, or any combination of ports which add up to less than 64K bytes Intel reserves I/O port addresses 00F8H through 00FFH

MEMORY-MAPPED I/O Any instruction that reference memory can be used for I/O operations Part of the memory is reserved for the I/O map No separate control signals are needed

The M/IO# pin acts as an additional address line thus allowing the system designer to easily determine which address space the processor is accessing. Figure 12.1 shows the memory map for both memory mapped and isolated I/O

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Memory-Mapped Versus Isolated I/O There are some problems with memory mapped I/O: For example: Memory caching However, the advantages tend to make it worth while: Isolated I/O device drivers needs specialized assembler instructions, memory mapped drivers can be written in C. Memory mapped I/O is faster. Easier I/O protection (e.g. use page protection)

Memory space

I/O Space Memory space

I/O Space Memory mapped

Isolated

Figure 12.1 Isolated and Memory-Mapped I/O Basic Input/Output Interface


Basic Input Interface 3-state buffers are used to connect input devices to the data bus of the microprocessor The buffer may be a discrete element, or integrated in a programmable I/O device

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Basic Output Interface Latches are used to store (temporarily) the data being output from the microprocessor to the output device The latches may be a discrete element, or integrated in a programmable I/O device

Software Implementation of I/O Interfacing


There are three basic ways of implementing I/O in software: 1. Programmed I/O (polling, busy waiting)

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2. 3. Interrupt-driven I/O I/O using DMA

Programmed I/O Polling or handshaking is a method matching the speed of the microprocessor to that of the I/O device connected to it during data transfer. Handshaking involves checking whether or not the I/O device is ready to accept or send data to the microprocessor Disadvantages: Uses the CPU to wait for I/O (busy waiting) Advantages: Easy to program and understand

Interrupt-Driven I/O Advantages: Program can perform other task while waiting for I/O Disadvantages: More complex and difficult to program CPU might get flooded by interrupts

I/O Port Address Decoding


Like memory decoding, I/O port address decoding can be achieved by using: Multiplexer and PLD

8-BIT I/O PORTS

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16-BIT I/O PORTS Because the data bus of the 80386 is either 16 or 32 bit wide, it can access 8, 16, and 32 bits at the same time. Thus the I/O ports must be organised in banks (2 for 16-bit operations and 4 for 32-bit operations) Separate write signals must be generated for each bank to access 8-bit data No separate write signals are required to access 16-bit data when the data bus is 16-bit wide

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PROGRAMMABLE INTERFACE ADAPTER (PIA)


PIN DIAGRAM AND BASIC OPERATIONS The 8255 PIA has 3 ports A, B, and C programmed in two groups. Group A consists of port A and the upper half part of port C (A0-A7 and C4-C7). Group B consists of port B and the lower half of port C (B0-B7 and C0-C3). A1 0 0 1 1 The chip is selected by placing a logic 0 on the CS pin Pins A0 and A1 select the ports as follows A0 0 1 0 1 Function Port A Port B Port C Command Register

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PROGRAMMING THE 8255 The command register contains two command bytes: command byte A and command byte B. Bit 7 selects the command byte as shown in the diagram below. Group B (port B and the lower part of port C) can operate as either input or output in mode 0 and mode 1 only Group A (port A and the upper part of port C) can operate as either input or output in mode 0, 1 and 2 Mode 0 is the basic input/output that allows buffered input and latched output for group A and B Mode 1 allows strobed input through port A or B and handshaking through port C Mode 2 allows bi-directional mode of operation for group A only

MODE 0 OPERATION
The 8255 function as either a buffered input device or as latched output device The diagram below shows how to connect the 8255 to interface 8 7-segments displays to an 8088 microprocessor. The PAL16L8 is used to decode the address so that the 8255 function at address 0700-0703H Port A is used for the data and port B for selecting the 7-segment displays one at a time

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MODE 1 STROBED INPUT

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STROBED OUTPUT

Mode 2 Bi-directional Operation Only allowed with port A. Bi-directional data is used for interfacing two computers, etc.

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Review Questions
Question 1 f) Figure 1 shows how to use the 74ALS138 3 to 8 lines decoder to decode an 8-bit I/O address into 8 ports. Write down the address of each decoder. g) Modify Figure 1 so that the 8-bit I/O address generates 8 active low ports decoded at address F8H to FFH.

A7 A1 A2 A4 A3 A5 A6 A0

A B C
G1

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

P0 P1 P3 P5 P7 P2 P4 P6

G2A G2B

Figure 1

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KS30103 Microprocessor Interrupt Handling Interrupts and Exceptions


The 80386 has two mechanisms for interrupting program execution: 1. Exceptions are synchronous events that are the responses of the CPU to certain conditions detected during the execution of an instruction. 2. Interrupts are asynchronous events typically triggered by external devices needing attention. Interrupts and exceptions are alike in that both cause the processor to temporarily suspend its present program execution in order to execute a program of higher priority. The major distinction between these two kinds of interrupts is their origin. An exception is always reproducible by reexecuting with the program and data that caused the exception, whereas an interrupt is generally independent of the currently executing program. There are two sources for external interrupts and two sources for exceptions: 1) Interrupts a) Maskable interrupts, which are signaled via the INTR pin. b) Nonmaskable interrupts, which are signaled via the NMI (Non-Maskable Interrupt) pin. 2) Exceptions a) Processor detected. These are further classified as faults, traps, and aborts. b) Programmed. The instructions INTO, INT 3, INT n, and BOUND can trigger exceptions. These instructions are often called "software interrupts", but the processor handles them as exceptions.

Identifying Interrupts
The processor associates an identifying number with each different type of interrupt or exception. The NMI and the exceptions recognized by the processor are assigned predetermined identifiers in the range 0 through 31. Not all of these numbers are currently used by the 80386; unassigned identifiers in this range are reserved by Intel for possible future expansion. The identifiers of the maskable interrupts are determined by external interrupt controllers (such as Intel's 8259A Programmable Interrupt Controller) and communicated to the processor during the processor's interrupt-acknowledge sequence. The numbers assigned by an 8259A PIC can be specified by software. Any numbers in the range 32 through 255 can be used

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KS30103 Microprocessor Enabling and Disabling Interrupts


The processor services interrupts and exceptions only between the end of one instruction and the beginning of the next. When the repeat prefix is used to repeat a string instruction, interrupts and exceptions may occur between repetitions. Thus, operations on long strings do not delay interrupt response. Certain conditions and flag settings cause the processor to inhibit certain interrupts and exceptions at instruction boundaries. NMI Masks Further NMIs While an NMI handler is executing, the processor ignores further interrupt signals at the NMI pin until the next IRET instruction is executed.

Hardware Interrupts
Interrupt Pins Symbol INTR I Type Description INTERRUPT REQUEST is a maskable input that signals the Intel386 to suspend execution of the current program and execute an interrupt acknowledge function. NON-MASKABLE INTERRUPT REQUEST is a non-maskable input that signals the Intel386 to suspend execution of the current program and execute an interrupt acknowledge function.

NMI

Real Mode Interrupts

After the execution of each instruction, the microprocessor determines whether an interrupt is active by checking, in order: Current instruction executions Single-step NMI Coprocessor segment overrun INTR INT If one or more of these conditions are present, then:

1. 2. 3. 4. 5. 6.

1. FLAGS is pushed onto the stack 2. Both the interrupt (IF) and trap (TF) flags are cleared, which disables the INTR pin and

the trap or single-step feature.

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3. The CS and IP are pushed onto the stack. 4. The interrupt vector contents are fetched and loaded into CS and IP and execution 5. On IRET, CS, IP and FLAGS are popped. 6. IF and TF are set to the state prior to the interrupt

resumes in the ISR.

Interrupt Acknowledge (INTA) Cycles In response to an interrupt request on the INTR input when interrupts are enabled, the Intel386 DX performs two interrupt acknowledge cycles. These bus cycles are similar to read cycles in that bus definition signals define the type of bus activity taking place, and each cycle continues until acknowledged by READY# sampled asserted. The state of A2 distinguishes the first and second interrupt acknowledge cycles. The byte address driven during the first interrupt acknowledge cycle is 4 (A31 to A3 low, A2 high, BE3# to BE1# high, and BE0# low). The address driven during the second interrupt acknowledge cycle is 0 (A31 to A2 low, BE3# to BE1# high, and BE0# low).

Methods for Generating the Interrupt Vector


1.

Simplest method of generating an interrupt vector

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2.

Tri-state Buffer for Generating a Variable Interrupt Vector

Handling more than one Interrupt Request


If any of IRQx goes low, the NAND goes high requesting an interrupt.

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Note that if more than one IRQ goes low, a unique interrupt vector is generated and an interrupt priority needs to be defined and the Interrupt Vector table must be expanded to accommodate this.

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