Soft Constraints for SystemVerilog What are Soft constraints: Soft constraints are constraints which hold true

unless contradicted by another constraint. For example if I have the following constraints: . soft a !! " #. a !! $ %. soft b inside " to #" &. b inside #" to %" 'he resolution of these constraints are (a ! $ and b ! #"( In the first case constraint is contradicted by constraint # so the second and non)soft constraint ta*es precedence+ while in the case of b+ both constraints can be resolved by the number #". 'he difference between a soft constraint failing+ and a constraint failing is that in the case of a soft constraint+ the alternate constraint ta*es precedence and the generation continues with no error. Why use soft constraints: Soft constraints are used to define default values+ and default distribution for generated fields. For example if I have created an ethernet pac*et I might want to add in a few constraints to assure legal pac*ets are generated by default. ,xample: constraint p*t-len . pac*et-length inside ./0&: $ 1234 3 constraint valid-crc . gen-valid-crc !! 4 3 5y adding these non)soft constraints+ the user of this pac*et class can generate the pac*ets within these ranges. 6ny generation outside of these ranges will need special attention+ in terms of either changing the values pre7post generation or turning the constraint off. If+ however+ soft constraints were employed+ additional constraints could override the default values+ by adding new constraints li*e the following: constraint test-constraint . gen-valid-crc !! "4 3 or 77 In procedural code pac*et.randomi8e9: with pac*et-length !! 01"4 ;ayered constraints: In my experience+ verification environments are most robust when they are built in a layered fashion. 6. Component layer 6bsolute constraints of the class7ob<ect being constrained. 5. =nobs layer >efault values and distributions used in the current >?'@s verification environment C. 'est ;ayer Specific constraints for the current test 9only if reAuired: For example: In a pac*et generator there is a lowest level of constraints for what the pac*et generator is designed to handle. ,xample of absolute constraints:

constraint absolute-c . p*t-length B 04 p*t-length C """"4 3 ,xample of environment constraints: constraint env-c . p*t-length dist . 0& :7 " 4 /0$: #12 :7 0" 4 / #D: """2 :7 %"34 3 ,xample of test constraints: constraint t -c . p*t-length !! 0&4 3 In most cases these three level of constraints live in harmony. When the test does not add a constraint the @default@ environment constraints are used+ and when the test does use a constraint the constraint overrides the environment constraint. 'he following examples show problems which may arise: 'est constraint t#-c . p*t-length dist . #"" :7 " 4 / #" : %""2 :7 " 4 / %" : $""2 :7 "34 3 'est# constraint t%-c . p*t-length !! $4 34 In both of these cases the test will contradict the environment constraints. In SystemVerilog the user is given the option to (turn off( the constraint. 5ut this needs to be done in procedural code and the user needs to *now the name of the constraint or constraints . Solution: 6ce Verification has developed a small library for providing pseudo soft constraints for SystemVerilog users. 'he pac*age is available free of charge at the following lin*: http:77www.aceverification.com7softconstraints-p*g.htm 'he library provides four macros which can be used as soft constraints. Esoft-eA9CVariableB+ CvalueB: 77 'he variable is constraint to the value Esoft-gt9CVariableB+ CvalueB: 77 'he variable is constrained to greater than the value Esoft-lt9CVariableB+ CvalueB: 77 'he variable is constrained to less than the value Esoft-rng9CVariableB+CvalueB: 77 6llows the user to define a @soft@ range for a variable For example: class example#4 rand bit /F:"2 rand bit /F:"2 b 4 b#4 77 Soft constraints 9Can be overwritten by other constraints constraint c- . Esoft-eA9b +%#:4 77 b will be eAual to %# Esoft-lt9b#+&1:4 77 b# will be generated less then &1 3 endclass