ICSE2004 Proc.

2004, Kuala Lumpur, Malaysia

Characterization of Tunneling Current and Breakdown Voltage of Advanced CMOS Gate Oxide
Yong Yoong Hooi*, Associate Professor Dr. Iskandar Idris Yaacob*, Dr.Suhana Mohd Said*, Richard Alan Keating, Member IEEE *Department Materials Engineering, University of Malaya, 50603 Kuala Lumpur, Malaysia Silterra Malaysia Sdn. Bhd., 09000 Kulim, Kedah, Malaysia. Tel : 604 - 4015714, Email : yoonghooi yongasilterra.com

Abstract Scaling down of the CMOS technology requires ultra thin oxide to meet the scaling of gate length. Gate oxide reliability becomes important as the gate oxide thickness is reduced [1]. Tunneling current that flow through the thin oxide will cause an increase of the off-state current leakage and unnecessary power dissipation. In this study, probing is performed either directly on the silicided poly top-plate or on the Al interconnect top plate MOS capacitor. Probing directly on the silicided poly top plate capacitor shows poorer contact between the Tungsten probe needles and the silicide. We found that the optimal probe needle pressure had to be used to obtain consistent result. This paper studies the tunneling current mechanisms through the oxide and also the soft breakdown and hard breakdown of the oxide. Our baseline flow now utilizes probing directly on silicide which has greatly improved the costs and cycle time of this testing.

improved short channel characteristics [2]. Therefore, decreasing the oxide thickness proportional to the channel length is necessary in scaling of the MOS channel length [3]. With miniaturization of MOS device, concernr on the reliability of the gate oxide is increasing because of the increased number of transistors within a die and the higher electric field across the gate oxide. The quality of the gate oxide must be carefully monitored. Silicided poly top plate

(a)

I. INTRODUCTION
CMOS technologies are improving to meet the scaling of CMOS devices. Today, many CMOS device use the 0.1 8um channel length with the -30A oxide thickness. A shorter channel length provides a faster device speed. However, the shorter channel length, which will also cause an increase in the leakage current. Due to short channel effects devices with thinner oxide have a smaller channel depletion layer and hence

Fig. 1 (a) Silicided poly top plate capacitor. (b) Al interconnect top plate capacitor.

(b)

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In this paper, a MOS capacitor is used as a test structure for characterizing the reliability of gate oxide film with respect to oxide breakdown and electron degradation. Electrical testing or probing is done on two different structures. They are Silicided (CoSi) top plated MOS capacitor and Al interconnect top plated MOS capacitor.

The second type of tunneling current is direct tunneling current. In direct tunneling, electrons tunnel through the trapezoid energy barrier as shown in Figure 3. Electrons can tunnel directly through the forbidden-energy-gap of the oxide layer instead of tunneling into the conductionband of the SiO2 layer [4].

lI.GATE TUNNELING CURRENT

It is always desirable to obtain a zero current when a device is in the off state. However in real MOS transistor or capacitor, there is still some gate and drain current flow when the transistor is turned off. This is the gate tunneling current, 1g. The component through the gate oxide is normally due to gate tunneling current

Ig. This phenomenon is more severe when the gate oxide is thin. The energy barrier that an electron must overcome in order to cross the oxide is 3.1 eV. Electrons with energy less than this barrier cannot go through the oxide classically, but they can tunnel through the oxide quantum mechanically. Because of the differences in height of barriers for electrons and holes, and because holes have a much lower tunneling probability in oxide than electrons, the tunneling leakage of electrons through the oxide needs more concern than tunneling of holes through the oxide. There are two types of tunneling current, Fowler-Nordheim (F-N) tunneling I,n electrons are injected by tunneling into the conduction band of the oxide through the triangular energy barrier (Fig 2). Once the electron is injected into the oxide conduction band, electron is accelerated by the oxide field towards the gate, and eventually causes the gate leakage current. F-N tunneling is predominant at higher voltages. As higher voltages are applied, the effective barrier width is reduced, and so the electrons can easily tunnel through the triangular barrier.

Fig.2 Energy band diagram for the phenomenon of Fowler-Tunneling in MOS capacitor

Fig. 3 Energy band diagram for the phenomenon of Direct-Tunneling of electron through the gate oxide.

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III. OXIDE BREAKDOWN

Gate oxide breakdown will eventually bring a catastrophic failure of the device. It is always desirable to have a strong dielectric strength gate oxide. Strong gate oxide will only shows failure or breakdown when they are stressed at higher electric field (>8MV/cm). Breakdown is defined as the time when there is a conduction path from the anode to the cathode through the gate oxide. As the voltage across the oxide increases, the electron current flowing through the oxide increases due to Direct or Fowler-Nordheim tunneling. Electron-hole pair (EHP) will be generated by electrons that are tunneling through the oxide. These electrons will have gained sufficient energy to create the EHP. Mobility of holes in SiO2 is very low as compared to the electrons. Thus trapped holes in the oxide will cause significant damage to the oxide. If enough of these traps are created, a conductive path of traps between the gate and substrate can be formed. This will finally lead to breakdown of the oxide (percolation model). This type of breakdown is called soft breakdown (SBD) [5]. Hard breakdown of oxide occurs when a silicon filament is formed between the substrate and the poly gate. When sufficient heat is generated by the leakage current, the silicon can melt in a small region and cause melting. Gate oxide breakdown can also be caused by the presence of the defects. For example, Na+ contamination can greatly accelerate the breakdown process [6]-[7]. Also, crystalline defects in the silicon substrate such as stacking faults can reduce the breakdown of the oxide [8].

group are normally contains weak spots. Oxides that fail in mode B may give rise to early failures of ICs under normal operating condition although they do not produce instant shorting. C-mode group oxides can withstand extremely high electric fields (812MV/cm). The failure mechanism exhibited by this group is referred to as 'intrinsic' failure [4].
In this study, breakdown voltage of the gate oxide can be obtained directly from the Jg-Vg plot. Breakdown voltage of gate oxide is defined as the voltage where the current of the gate is luA. From this, the electric field is calculated. The failure can then be categorized as mode A, B or C.
IV EXPERIMENTAL RESULTS AND DISCUSSIONS

The MOS capacitors being tested have gate oxide thickness of -29A. The gate area is 0.0 1cm2. The substrate material is n-doped Si. The gate oxide was grown in 02 in 8500C followed by N2 anneal. Bench tests were carried out on two different capacitors; silicided poly and Al interconnect top plate (Fig.1). Silicided poly top plate MOS capacitors have the advantage of requiring fewer masking layers; shorter cycle time and a faster feedback than the Al interconnect top plate capacitor.

During testing, gate oxide breakdown is categorized into 3 modes, A, B and C. Amode occurs when the oxide fails when stressed at electric field < 1MV/cm. It is believe that this oxide is already shorted before the application of the low strength field. In B-mode failure, breakdown of oxide

Both of the structures were tested with the voltage ramp test at room temperature. Ramped voltage stress is used to measure the breakdown voltage (Vbd) and current-voltage flow through the oxide. A continuously increasing voltage is applied to the gate until breakdown is detected, while the substrate was grounded. The gate tunnel current density Jg ( Jg = Ig/Area of capacitor) is measured and showed in figures below. Figure 4 shows that probing on Al interconnect results in similar
and stable results.

occurs when the oxide is stressed at electric field 2-6MV/cm. The oxides of B-mode

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1.00E+02 1.00E+00 1.00E-02

1.OOE-04
0

techniques and optimal probe needle pressure had to be used to obtain consistent
result (Figure 6).

However, it is found that with proper

1.00E-06
1. OOE-08
,

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Direct tunneling

1.00E-12
Vg(V)

41i.00EO
1
5

ErN Tunneling
|x Al interconnect
l
1~~~~~~~~~~~~~~....O

1OO0E-09
Fig.4 Jg-Vg curves for probing directly on the Al interconnect MOS capacitors.

iiie

1.00&11

4 Vg(V) 6

10

Fig.6 Jg-Vg curves for both the silicided poly

Typical tunneling current

1.E*02 with minimal contact
1.E-02
N 1.E-04
a
E
im

top-plate and Al interconnect capacitors.

and Al interconnect capacitors give similar results. A proper and consistent reading for silicided poly top plate capacitors can be obtained when optimal pressure is applied to
/ w

directly

Figure 6 shows the Jg vs Vg. Probing

on

top

of

silicided poly top-plate

1.E-06
1.E08 l

Variations of current due to to 2V, direct tunneling occurs. Beyond 2V

give a better contact between the tungsten 8Nneedles and the silicide. For voltages from 0

unstable con act.

9 10 11 Q

till breakdown is FN tunneling.

t 2

3 4

5 6

7 8

Noisy, unstable current at low voltages due to poor contact.

Fig.5 Jg-Vg curves for probing directly on the silicided poly top plate MOS capacitors.

Va

Probing directly on the silicided poly top plate capacitors is more sensitive than probing on Al interconnect top plate capacitors. It can be seen from Figure 5 that measurements obtained from the probing are not consistent. This may due to poor contact between the tungsten probe needles and the silicide. Also, the trend of the curves is not the same because of the poor contact.

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Cm&d"

bablfty

V. BREAKDOWN VOLTAGE - DISTRIBUTION

90%
,.

breakdown voltages. In our study, both of the structures show similar distribution of breakdown voltages. Although there is a small tail of the distribution, but as long as the low breakdown tail is small, the oxide quality is considered good.

.2
-:
i

50%
33%

VI CONCLUSIONS

10

10r

06

defecti
0.8

2 -

0.40

1.2

1.6

2.4

Fig.7 Cumulative probability plot of silicided poly top plate capacitor.

CMubMb

90% 67%
.2

D1
DI

50%

2o Q

33%

10%,
0

Defect tail detected

05
1

Probing directly on the silicided poly top plate MOS capacitor shows similar results with conventional probing on the Al interconnect top plate capacitor provided the optimal pressure is being stressed on the structure for a better and stable contact between the probing needles and the silicide. Results show that, oxide breakdown characterization for both the structure shows similar and consistence result. Therefore, our baseline flow now utilizes probing directly on silicide which has greatly improved the costs and cycle time of this testing. Gate current across these 29 A oxide is mainly due to Direct and FN tunneling. Defects can cause higher leakage and thus lower breakdown voltages which show up as a tail in the breakdown distribution. Fabs must be therefore closely monitor this breakdown voltage distribution to assure the on going quality of the gate oxide. ACKNOWLEDGEMENT
The authors would like to thank Silterra management for the support in making this project a success, and to Associate Professor Dr. Iskandar Idris Yaacob, Dr.Suhana Mohd Said from University of Malaya for their valuable advice.
REFERENCES

1.5

25

Fig.8 Cumulative probability plot of Al interconnect top plate capacitor.

Figure 7 and 8 show the cumulative plots of breakdown voltage for both the silicided poly top plate and Al interconnect top plate MOS capacitor. The breakdown voltage (Vbd) in this study is defined as the voltage across the oxide when the current is I uA. Most of the industry looks at the distribution of the breakdown voltages. The sample data is collected on many sites of the wafer. Typical results show breakdown voltages of 2.3V to 2.4V. The small tail of the distribution shows devices with lower breakdown voltage than the typical

[1] International Technology Roadmap for Semicondutor (ITRS), 2003. International SEMATECH. [2] MOS scaling: Transistor challenges for the 21St century. Scott Thompson, Portland technology development,

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intel corp. Paul Packan, technology computer aided design, Mark Bohr, Portland technology development, intel Corp. [3] Jackson, J. C., Robinson, T., Oralkan, 0., Dumin, D.J. and Brown, G. A., "Differentiations between electric breakdown and dielectric breakdown in thin silicon oxides" Spring Meeting of the Electrochemical Society, Proceedings of the Oxide and nitride Symposium, Montreal, May, 1997. [4] Stanley Wolf Ph.D, Silicon Processing For The VLSI ERA, Volume 4: Deep Submicron Process Technology, Lattice Press, California, 2003, ch. 3. [5] H.C. Lin. D.Y.Lee, C.Y.Lee, T.S.Chin, T.Y.Hung, and T.Wang, New insight into breakdowns mode and their evolution in ultra thin gate oxide. International Symposium on VLSI Technolgy. Pgs 37-40, 2000. [6] T.H. D'Selano, " Dielectric breakdown indeed by sodium in MOS structures," J.Appl. Phys., vol 44, pg. 527, Jan. 1973. [7] C.M.Osburn and D.W. Omond, " Sodium-induced barrier-height lowering in dielectric breakdown on Si02 films on silicon," J. Electronichem Soc, vol 121, no.9, pg 1195, Sept 1974. [8] P.S.D.Lin, R.B. Marcus, and T.T. Sheng " Leakage a breakdown and breakdown in ultra thin oxide capacitorscorrelation with decorative stacking faults," J. Electrochem. Soc., vol 130, no.9, p. 1878, Sept 1983. [9] R. Degraeve, Oxide Reliability, 1997 IEEE International Reliability Physics Symposium,Tutorial Notes, Topic 7, pp.7.1-7.7 1.

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