ECE 210 Introduction to Digital Logic Design Lab 4 Finite State Machines Fall Term 2013 University Of Alberta

INTRODUCTION
Logic circuits are classified into two types, combinational and sequential. A combinational circuit is one whose outputs depend only on the current inputs. A sequential circuit is one whose outputs depend not only on its current inputs, but also on the past sequence of inputs. Until now, we have looked exclusively at combinational circuit design. Today we will focus on techniques for implementing sequential circuits.

PRE-LAB ASSIGNMENT
You are expected to read the lab instructions and complete the pre-lab assignments before attending the lab sessions. Pre-lab assignments will be checked at the beginning of each lab session. You are responsible for including your pre-lab assignment as an appendix to your lab report if necessary. 1. Design a Moore finite state machine to meet the specifications in this lab. It should be an 8-state machine using 3 D-Type flip-flops. Detail all state assignments, state outputs, and provide a detailed state diagram. Include the following in the derivation of your solution: i. State tables ii. Transition tables iii. K-maps (Hint 5 variable k-map) iv. Flip-flop input and output equations v. A complete schematic diagram showing connections to LEDs, Seven Segment Display, switches, reset button, and 50 MHz Clock.

It is very important that you complete the pre-lab components before you come to the lab. Failing to do so will impede your ability to complete the lab within the allotted time.

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BACKGROUND
D-Type Flip Flop In this lab you will use a common device known as a Flip-Flop, as the memory element in your state machine. Flip-Flops use feedback logic to store a digital value so long as there is power applied to the circuit. There are a number of different types of Flip-Flops, in this lab we will deal with the D-Type Flip-Flop. Below is the schematic symbol for a basic D Flip-Flop.

The inputs to the device are D (data) and C (clock). On each rising edge of the clock signal, the value present on the data input will be latched and held at the output, Q, until the next clock edge. At that time, whatever value is present at D will be transferred to Q. A variation of the basic D-FF is shown below with PRE (preset) and CLR (clear) inputs. The preset and clear inputs are used to force the value of the output, Q, to a certain state. Activating the preset signal will cause the output to go to logic 1. Asserting the clear signal will cause the output to go to logic 0. Note: We will not use this variation in this lab

Flip-Flops are typically used as a storage element, latch or buffer in digital electronics. An SRAM is a made up of Flip-Flops with each device storing 1-bit of information.

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PROCEDURE
There has been a problem for those traveling through secondary roads across very busy primary highways. To alleviate this problem, a decision is made to design a traffic light controller for highways passing through rural areas. To achieve this feat, you have been hired in the hope that you can design and implement a solution before the end of winter. Several locations along Highway 16 have been targeted for testing the controller. In each location, detectors are to be placed along the secondary road coupled with some simple timer logic to raise a signal when a vehicle is waiting to cross the highway. A second set of detectors, intelligent enough to discern between a regular vehicle and an Emergency Vehicle, will be placed on the main highway. A special signal will be raised when an emergency vehicle is approaching (see Figure 1). In addition, 7 Segment counters are placed on the secondary highway which will count down from five to zero before cycling the light to red. The traffic light controller should operate with the following criteria: 1. If no vehicle is detected on the secondary road, the highway lights should be green, while the secondary road lights should be red. The 7-segment should display a 0. 2. If a vehicle is detected on the secondary road, the change signal will be asserted and the highway lights should cycle through yellow, then red. The secondary road lights will then turn green. Upon turning green, the 7-Segment will display a 5. 3. The secondary road lights will remain green so long as a vehicle is detected on the secondary road. The 7-segment will remain at displaying a 5. 4. When no further cars are detected on the secondary road, the 7-Segment will start counting down in 1 second intervals from 5 to 0 in descending order. Upon hitting 0, the light will cycle from yellow to red. The highway light will then turn green. 5. If an emergency vehicle is detected on the primary highway at any time, the EMV signal will be asserted and the highway lights should immediately (next clock cycle) switch to green, while the secondary road lights should turn red. The 7-segment will reset to 0.

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Figure 1

Your task is to design, test and implement the Moore Finite State Machine (FSM) circuitry, which drives the traffic light cycles. Figure 2 illustrates the state diagram for your project (an explanation of this figure follows):

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Figure 2 Inputs: Reset Change EMV Clock Outputs: HG, HY, HR SG, SY, SR SW1, SW2, SW3 Green, yellow and red highway lights respectively. Green, yellow and red secondary road lights respectively. Inputs to the 7-Segment display designed in lab #3. Places controller in its initial state (highway green, secondary road red) Goes high when a vehicle is detected on the secondary road Goes high when an emergency vehicle is detected on the primary road. System Clock/Timer (not shown in diagram)

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Part A Moore Finite State Machine Create a new schematic template and call it FSM. Using logic gates, implement the circuit for the Finite State Machine based on your K-map and Flip Flop equations. Do not forget to apply the input/output ports for the circuit. When implementing your design, be sure to use a modular approach. There are three distinct blocks in this design; next-state logic, memory elements, output logic. The block diagram below may prove helpful.

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Your circuit schematic could look similar to the figure below:

Alternatively, you could create individual schematics for the Next State Logic, Memory Elements, and Output Logic. These individual schematics would then be converted to schematic symbols, and placed on a single schematic for the FSM. That design approach would yield a schematic such as the following:

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In either event, once the circuit is complete perform a simulation on it for verification. After the simulation verification, create a new symbol for this schematic template. The symbol should look similar to the figure below:

We will be using this symbol in Part B.

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Part B Integration with 7-segment Display and Clock Timing. Create a new schematic template and call it TopLevel. Download and import the file ClockFrequencyDivider into the project. This file will divide the clock frequency from 50 MHz down to 1Hz essentially creating a delay of 1 second. Create a symbol from this file. Import your 7-segment schematic from Lab 3 into the project. Create a symbol from this file. In your TopLevel schematic, create the schematic in the figure below. Do not forget the input and output ports. No simulation is required for this part.

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Part C Implementing the Design Once the TopLevel schematic is complete and error free. Assign the input/output pins to the constraint (.ufc) file and then implement the design onto the NEXYS2 board. The input/output pins are the following: Signal Port Clk Reset Change EMV SR SY SG HR HY HG CA CB CC CD CE CF CG AN0 AN1 AN2 AN3 NEXYS2(FPGA) pin B8 B18 G18 H18 J14 J15 K15 K14 E17 P15 L18 F18 D17 D16 G14 J17 H14 F17 H17 C18 F15 Description 50Mhz Clock Reset Button Change EMV LED0 LED1 LED2 LED3 LED4 LED5 CathodeA CathodeB CathodeC CathodeD CathodeE CathodeF CathodeG Anode0 Anode1 Anode2 Anode3

Once you have completed your implementation, be sure to test all the possible conditions before calling for a check-off.

VERIFICATION
Demonstrate your working implementation to a TA to receive a check-off.

DOCUMENTATION
This lab does not require a formal report.

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ECE 210 LAB 4- MARKING GUIDELINE

Students Names: _________________________________________ IDs : _________________________________________

Pre-Lab 35 Marks (5) (5) (5) (10) (10) State Table Transition Table K-Maps Next State & Output Equations Schematic

Pre-Lab Total: _____ / 35 In-Lab 65 Marks (20) (10) (10) (5) (5) Traffic Light Changes Correctly Side Road Light Change Countdown Correct EMV Detection State Reset Schematic Neatness

TA Signature: ____________________

In- Lab Total: _____/ 65

Lab 4 Total: _____/100

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