The International Semiconductor Roadmap

and Its Impact on Semiconductor-Related

Research

Jan M. Rabaey
Gigascale Research Center (GSRC)
(GSRC
The International Technology RoadMap for
Semiconductors
u Inaugurated in 1992 (as the NTRS).
Initiative of SIA (Semiconductor Industry
Association)
u Became an International effort in 1997
(ITRS)
u Provides bi-annual updates on 15 year
road-map
u Joint effort of industry, government,
consortia, and universities
u An assessment of the semiconductor
technology requirements. The objective of
the ITRS s to ensure advancements in the
performance of integrated circuits.
u Identifies the technological challenges
and needs facing the semiconductor
industry over the next 15 years.

2
A Typical Roadmap Table

3
A Typical Roadmap Table (cntd)

4
More Sophistication over the Years

The “Living” ITRS Roadmap (started in 2001)

u Provides: consistency checks, unified assumptions for power,
frequency, die size, density, performance, etc

u Creates linkages
between different
e nt
areas gem for
an a )
u Improves r M PU
Po we nce M
flexibility, quality, fied rm a gy
nti rfo o lo
transparency of Qua h -Pe echn
à (Hig ign T
roadmapping Gap Des

5
Important Outcome: Challenges and Roadblocks

6
 Example: The Productivity Gap

10,000,000 Logic Transistors/Chip 100,000,000

Logic Transistors per Chip

.10µ 1,000,000 Transistor/Staff Month 10,000,000

Trans./Staff - Month
100,000 58%/Yr. compound 1,000,000

Productivity
Complexity growth rate
.35µ 10,000 100,000
(K)

1,000 10,000
x
100 x x 1,000
x x x
x
10 21%/Yr. compound 100
2.5µ
Productivity growth rate
1 10
1991

1999
2001
2003

2007
1987
1989

1993
1995
1997

2005

2009
1983
1985
1981

Source: SEMATECH
7
Focus Center Research Program
Origin of This Program

u Bill Perry u Gordon Moore

U.S. Universities--Our National Treasure
u Paul Kaminski u Craig Barrett
Semiconductor Technology Council Co-Chairs
u Anita Jones u Larry Sumney
OSD/MARCO Agreement
u Dan Radack u Harold Hosack
DARPA/MARCO Joint Solicitation & Management

8
 Industry Motivation
Critical problems accelerate toward us--In 2 years time,
the red areas are 3 years closer!
2006 2005
1997 NTRS Tables 100nm 1999 ITRS Tables 100nm
Table 14 Memory and Logic Technology Requirements
TWG Technology Requirements
Year of First Product Shipment 1997 1999 2001 2003 2006 2009 2012
Technology Generation 250 nm 180 nm 150 nm 130 nm 100 nm 70 nm 50 nm 1999 2002 2005 2008 2011 2014
2 . 5– 1 . 8 1 . 8– 1 . 5 1.5 – 1 . 2 1.5 – 1 . 2 1.2– 0 .9 0 . 9 –0.6 0 . 6 –0.5 180 130 nm 100 nm 70 nm 50 nm 35 nm
Min. Logic V dd (V) (desktop)
V dd Variation ≤ 10% ≤ 10% ≤ 10% ≤ 10% ≤ 10% ≤ 10% ≤ 10% Min. Logic V dd (V) (desktop) 1.8 - 1.5 1.5 - 1.2 1.2 - 0.9 0.9 - 0.6 0.6 - 0.5 0.6 - 0.3*
T ox Equivalent (nm) 4–5 3–4 2–3 2–3 1.5– 2 < 1.5 < 1.0 Tox equivalent (nm) 2.-3 1.5-2 <1.5 <1 < 1.0 < 1.0
Equivalent Maximum E-field 4–5 5 5 5 >5 > 5 > 5 Max Ioff @ 25 °C
(MV/cm) (nA/µm) 5 5 4 3 3 2
Max I off @ 25 °C (nA/µm) 1 1 3 3 3 10 10
(For min. L device) High Perf.
(For minimum L device) Nominal Io n @ 25 °C (µA/µm)
750/350 750/350 750/350 750/350 750/350 750/350
Nominal I o n @ 25 ° C (µA/µm) 600/280 600/280 600/280 600/280 600/280 600/280 600/280 [NMOS/PMOS] High Perf.
(NMOS/PMOS) Max Ioff @ 25 °C
Gate Delay Metric (CV/I) (ps)* 1 6 –17 1 2 –13 1 0– 1 2 9 –10 7 4–5 3–4 (pA/µm) 10 10 10 10 10
V T 3σ Variation (± mV) 60 50 45 40 40 40 40 (For min. L device) Low Power 4.71E+02
(For minimum L device) Nominal Io n @ 25 °C (µA/µm)
450/210 450/210 450/210 450/210 450/210 450/210
Lgate 3σ Variation ≤ 10% ≤ 10% ≤ 10% ≤ 10% ≤ 10% ≤ 10% ≤ 10% [NMOS/PMOS] Low Power
(For nominal device) VT 3σ variation (±mV)
50 42 33 25 17 17
≤ 20% ≤ 20% ≤ 20% ≤ 20% ≤ 20% ≤ 20% ≤ 20% (For min. L device)
Leff 3σ Variation
S/D extension junction depth,
(For nominal device; % of L eff ) 0.045 - 0.07 0.03 - 0.05 0.025 - 0.04 0.02 - 0.028 0.013 - 0.02 0.01 - 0.014
nominal (µm)
S/D Extension Junction Depth, 5 0 –100 3 6 –72 3 0– 6 0 2 6– 5 2 20 – 4 0 15–30 10–20
Nominal (nm) Gate sheet resistance (Ω/sq)
Total Series Resistance of S/D ≤ 10% ≤ 10% ≤ 10% ≤ 10% ≤ 10% ≤ 10% ≤ 10% 4-6 4-6 4-6 <5 <5 <5
@ minimum dimension
(% of channel resistance)
Gate Sheet Resistance ( Ω/sq) 4–6 4–6 4–6 4–6 4– 6 < 5 < 5
Isolation Pitch Consistent with the linear scaling per generation
6--7 7 7--8 8 8-9 9
Interconnect Levels 6 6–7 7 7 7– 8 8–9 9
Short Wire Pitch (µm) 0.50 – 0 . 75 0.36 –0.54 0.30– 0 . 4 5 0.26– 0 . 3 9 0.2–0.3 0.14–0.21 0.10–0.15 Interconnect Levels
DRAM Cell Size (µm2 ) 0.56 0.22 0.14 0.09 0.036 0.014 0.006
Short wire pitch ( µm) 0.36 - 0.54 0.26 - 0.39 0.2 - 0.3 0.14 - 0.21 0.10 - 0.15
0.07 -
Soft Error Rate (FITs) 1000 1000 1000 1000 1000 1000 1000 0.11
DRAM Retention Time (ms) 6 4 –128 1 2 8– 2 5 6 – 256 – 5 1 2 512– 1 0 2 4 1 0 2 4– 2 0 4 8– 4 0 9 6 0.0074 -
2048 DRAM cell size ( µm2 ) 0.26 - 0.32 0.13 - 0.17 0.06 - 0.08 0.03 - 0.04 0.015 - 0.02 0.0098
Flash Data Retention (year) 10 10 10 10 10 10 10
Cell Dielectric Tox Equivalent 3.3 - 4.3 1.7 - 2.7 1.15 0.7 - 1.0 0.5 0.4
NOR Cell Size (µm 2 ) 0.6 0.3 0.22 0.15 0.08 0.04 0.02
(nm)
+/– V pp 8.5 8 8 7.5 7 6.5 6
250 220 220 200 200 200
Tunnel Oxide (nm) 8.5 8 8 7.5 7 6.5 6 Min. Refresh Time (ms)
Flash Endurance (erase/write 100K 100K 100K 100K 100K 100K 100K 500
cycles) Soft Error rate (fits) 500 500 500 500 500
ESD Protection Voltage (V/µm) 6 7.5 9 10.5 12 13.5 15
Solutions Exist Solutions Being Pursued No Known Solutions

The objective of the FCRP is the establishment of focused multi-

multi-university teams to engage in
* The CV/I gate delay metric is calculated using the data in this table along with the microprocessor gate length given in the
ORTC table (Appendix B). The transistor width is assumed to be 5 mm for NMOS and 10 mm for PMOS at the 250 nm
generation. Device width is then scaled consistent with minimum feature size scaling.

discovery research in areas where evolutionary research and development have failed to find
solutions to anticipated problems for the semiconductor industry.
industry.
16
9
DoD Motivation:
}
PCA(ITO-Graybill)
ASIC( MTO-Reuss) DARPA
TEAM( MTO-Reuss) Programs of
DoDs Biggest Error in Dealing With ICs: Hyperscale(MTO)
Opportunity

}
Noise Radar(MTO)
Design
Interconnect Industry
Mat’ls/Struc./Devices Solves ITRS
Ckts/Sys/Software

Thinking They Could Just

Roadblocks
Focus Centers
1994 1996 1998 2000 2002 2004 2006 2008 2010 2012 2014 2016 2018

Buy Commercial Parts 65%

DoD/Industry/University Partnerships

Japan
projected
55%
45.3%
45% (actual)

35% 40.8 87 to 97
(actual)
25% US
SEMATECH projected
15%
1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004
US and Japanese Semiconductor Market Share
source: SIA Projections, VLSI Research Actuals

10

4
DoD Hands Off Policy
1.25µ • 67 to 87
VHSIC
2
0.5µ •
1966 1968 1970 1972 1974 1976 1978 1980 1982 1984 1986 1988 1990
DoD Use of ICs Fall Behind Commercial Market

Minuteman II
Production
Orders Ignite
DoD R&D
IC Industry 47 to 67
Leads to l IC Invention
1952 1954 1956 1958 1960 1962 1964 1966 1968 9
DoD Ignites Chipmakers
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 Focus Center Research Program Structure
Semiconductor Other
Funding Industry
Suppliers
SIA DoD Potential
Sources
Sources

Focus Center MARCO/DARPA Governing

Management Council

Materials, Circuits,
Design/Test Interconnect Structures,
Devices
Systems,
Software
#5 #6
Lead
Universities

Affiliated
Universities

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 Focus Center Research Program Research Teams:
Design and Test Focus Center UC-Berkeley
Mission: To empower designers to move from ad-hoc SOC
design to disciplined, platform-based design by enabling CMU UCLA
scalable, heterogeneous, component-based design with a MIT UC – San Diego
single-pass route to efficient Si implementation from a Penn State UC – Santa Barbara
microarchitecture. Princeton UC – Santa Cruz
Sponsors: Purdue Univ. of Michigan
Stanford UT Austin
Univ. of Wisconsin
Prof. Jan Rabaey

Interconnect Focus Center Georgia Tech

Agere Intel The IFC is a comprehensive effort to provide a hierarchy of
Agilent LSI Logic interconnect solutions with an optimum interconnect MIT
AMD Micron possessing low latency and little energy dissipation through: Stanford
Analog Devices Motorola •innovative system architectures RPI
Conexant National •original circuit concepts UCLA
Cypress TI •novel interconnect structures Univ. of Albany
IBM Xilinx •new materials and processes
•previously untapped fundamental principles
Prof. James Meindl
Semiconductor
Industry Materials Structures & Devices Focus Center MIT
Suppliers The MSD Center is focused on exploring the most
promising path for microelectronic device evolution in the Cornell UC-Berkeley
Air Products SCP Global next 2-3 decades. There are 2 overlapping approaches: Princeton Univ. of Albany
Applied Materials Speedfam •Scaling CMOS to its ultimate limit Purdue UT-Austin
KLA-Tencor Teradyne •gate length L< 15 nm Stanford UVA
Novellus Veriflo •operating voltage < 0.5v UCLA
•novel matls & structures added to Si
Prof. Dimitri Antoniadis •Exploration of new frontier devices
•high speed/low power transistor alternatives
Circuits, Systems & Software Focus Center CMU
DUSD(S&T) The C2S2 mission is twofold:
Deputy Undersecretary of Defense •Develop the fundamental new methods needed to convert Columbia RPI
for Science & Technology tomorrow’s transistors into useful performance. Cornell Stanford
•Mitigate impacts and exploit opportunities in design of MIT UC–Berkeley
circuits, systems and software. Princeton UIUC
•In other words, how fast, how small, how cheap and how Univ. of Washington
DARPA quickly can they be designed??
Prof. Rob Rutenbar 12
 Focus Center Research Program Funding
1999 2000 2001 2002 2003 2004 2005 2006
Source (FY98) (99/00) (FY01) (FY02) (FY03) (FY04) (FY05) (FY06)
SIA Members 4 6 11 12 20 26 30 30
Suppliers + Fabless 2 3 4 4 10 13 15 15
DUSD(LABS) 4 7 3 8 10 13 15 15
TOTAL FCRP $10 $16 $18 $24 $40 $52 $60 $60
Focus Centers Funding Schedule ($M)
UCB - Design & Test 5 6 9 9 10 10 10 10
GIT - Interconnect 6 6 7 7 10 10 10 10
MIT - Mtls, Structures & Devices 3 4 7 10 10 10
CMU - Ckts, Sys. & Software 3 4 7 10 10 10
Focus Center # 5 3 6 10 10
Focus Center # 6 3 6 10 10
TOTAL FC $11 $12 $22 $24 $40 $52 $60 $60
DARPA Demonstration Funding
DARPA DEMO #1 1 6 10 9 4
DARPA DEMO #2 1 6 10 9
DARPA DEMO #3 1 6 10
DARPA DEMO #4 1 6
DARPA DEMO #5 1
TOTAL DARPA 28 $1 $7 $17 $26 $30
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GSRC (and FCRP)?
“Not Just Research As Usual”
uA unique experiment in long-range, collaborative research,
enabling broad collaboration across many areas of EDA
and Design
uIn the 1960-1980’s DARPA played a key role in creating
and maintaining a collaborative community in design and
architecture
s Xerox PARC & the Alto, Berkeley Unix, RISC, RAID, Integrated
EDA Systems…
uGSRC is about rebuilding and maintaining such a
community of researchers in many fields related to silicon
design productivity
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Summary

u The ITRS Roadmap had done a superb job in keeping the

semiconductor industry focused and forward-looking.
u It has helped to identify major roadblocks, and has
sensitized the industry and government to invest in long-
term research. The Marco FCRP is a perfect example of
this.
u Beware of the pitfalls of road-mapping. As a mostly
extrapolative exercise, it fails to capture technology
surprises.
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