MODELING OF COUNTERS IN XILINX

AIM To design the following counters and simulate the models using Xilinx ISE 9.1i. 1. 2. 3. 4. 4- Bit UP COUNTER 4-Bit Down counter 4-Bit Up/Down counter 3-Bit Ripple counter

MATERIALS REQUIRED: 1. Xilinx ISE 9.1i Software 2. PC PROCEDURE: 1.Open Xilinx ISE 9.1i software->go to file->create new project with an projectname, select HDL->next->select the following specifications:Spartan3 family,XC3S400 device,PQ208 package,-5 Speed grade,Verilog/VHDL Module->next. 2.Go for new source ->select verilog /VHDL module->file name->next. 3.Provide the inputs and the outputs->Finish 4.Type the corresponding program and save it. 5.Go to source->Behavioural simulation->open .v/.vhd extention file->process 6.->check syntax. 7.Right click the program file (.v/.vhd extention)->new source->test bench wave form->file name->finish->select combinational(internal clock)>GSR(FPGA)->finish->give the inputs to the testbench->save. 8.Simulate the test bench file(with .tbw extension)using process-> Xilinx ISE simulator->simulator behavioural model->run and verify the simulated output wave.

THEORY: HDL: HDL stands for Hardware Description Language, it allows the designer to model the concurrency of processes found in hardware elements . HDL is popular for logical verification seven though designers has to manually translate HDL basic design into schematic circuit with inter-connection between gates. Digital circuits could be described at a RTL(Register Transfer Logic) by the use of HDL. The details of gates &there inter-connections to implement the circuits were automatically extracted by logic synthesis tools from the RTL descriptions. Logic Synthesis would implement the specified functionality interms of gates and inter-connections. HDLs are used for system-level design, used for the simulation of system boards, inter-connection buses, FPGAs(Field Programmable Gate Arrays)& PALs(Programmable Array Logic). IMPORTANCE OF HDLs: 1.Designers can write their RTL descriptions without choosing any fabrication technology. No need for re-design in case of emergence of new technology. 2.As describing in HDL, functional verification can be done early in the design cycle. 3.Designing with HDLs is analogous to computer programming. TYPES OF MODELING IN HDL: 1.BEHAVIOURAL MODELING: Here the designing is done to describe the design functionality in an algorithmic manner(i.e.) the designer describes the behavior of the circuit. 2.GATE-LEVEL MODELING: In this type the modeling is done at the low-level of abstraction i.e. it describes in terms of gates that are used in them. 3.DATAFLOW MODELING: In this type the design is done in terms of the data flow between registers and how a design processes data rather than instantiation of individual gates. XILINX ISE: Software is critical to the effective use of programmable logic. The spartan-3 generation is supported by the complete set of Xilinx integrated software environment(ISE) design tools, with additional support available from a variety of partners. This chapter provides

on overview of those design tools. It is intended primarily for the user who is new to the Xilinx development system. Combined with the Spartan-3 generation FPGA family, the ISE optimized design tools help you finish faster and lower your project cost. The ISE packages the collection of Xilinx software design tools that concentrate on delivering the most productivity available for your Spartan-3 generation logic performance. With proactive timing closure technology, you get the fastest run times in programmable logic ensuring you reach your performance goals quicker.

Incremental design delivers faster re-compile times with guaranteed performance, and the optional Xilinx chipscope TM pro verification tools provide real time debug with advantages that are not possible in ASIC designs. The ISE development system make sure you get through the logic design process faster, saving both time and project cost, and getting you to market ahead of your competition. PROGRAMS:

4- Bit UP COUNTER Verilog: module counter (C, S, Q); input C, S; output [3:0] Q; reg [3:0] tmp; always @(posedge C) begin if (S) tmp = 4'b0000; else tmp = tmp + 1'b1; end assign Q = tmp; endmodule

4- Bit DOWN COUNTER Verilog: module counter (C, S, Q); input C, S; output [3:0] Q; reg [3:0] tmp; always @(posedge C) begin if (S) tmp = 4'b1111; else tmp = tmp - 1'b1; end assign Q = tmp; endmodule 4-BIT UP/DOWN COUNTER- VHDL: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port(C, CLR, UP_DOWN : in std_logic; Q : out std_logic_vector(3 downto 0)); end counter; architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (C, CLR) begin if (CLR='1') then tmp <= "0000"; elsif (C'event and C='1') then if (UP_DOWN='1') then tmp <= tmp + 1; else

tmp <= tmp - 1; end if; end if; end process; Q <= tmp; end archi;

3-BIT RIPPLE COUNTER-VHDL: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity yyy is generic ( n : natural := 3 ); Port ( clk : in STD_LOGIC; clear : in STD_LOGIC; dout : out STD_LOGIC_VECTOR (2 downto 0)); end yyy; architecture Behavioral of yyy is -- signals declaration signal clk_i, q_i : std_logic_vector(n-1 downto 0); begin -- clocks

clk_i(0)

<= clk;

clk_i(n-1 downto 1) <= q_i(n-2 downto 0); -- flip-flops gen_cnt: for i in 0 to n-1 generate dff: process(clear, clk_i) begin if (clear = '1') then q_i(i) <= '1'; elsif (clk_i(i)'event and clk_i(i) = '1') then q_i(i) <= not q_i(i); end if; end process dff; end generate; -- output dout <= not q_i; end Behavioral;

BLOCK DIAGRAM OF 4-BIT UP COUNTER:

TRUTH TABLE: clk 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 rst 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Cnt0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Cnt1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Cnt2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Cnt3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

BLOCK DIAGRAM OF 4-BIT DOWN COUNTER:

TRUTH TABLE: clk 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 rst 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cnt0 cnt1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 cnt2 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 cnt3 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

BLOCK DIAGRAM OF 4-BIT UP-DOWN COUNTER:

BLOCK DIAGRAM OF 3-BIT RIPPLE COUNTER-VHDL:

OUTPUT OF 4-BIT UP COUNTER:

OUTPUT OF 4-BIT DOWN COUNTER:

OUTPUT OF 4-BIT UP-DOWN COUNTER:

OUTPUT OF 3-BIT RIPPLE COUNTER: