Sie sind auf Seite 1von 4

Assignment Problems

1. Write a VHDL program to implement NOT gate, TWO input OR gate, NOR and NAND gates. 2. Write a VHDL Program to implement the following expressions a) b) c) d) .

3. Generate a clock waveform with 4. Write a VHDL program to implement a full adder circuit

5. Write a VHDL program to implement a 4 bit full adder circuit

6. Write a VHDL program to implement a full adder circuit using half adders

7. Write program for the following components using data flow style of modeling. a) Half adder and full adder b) 2X4 decoder with enable as input. c) 4X1 Multiplexer. 8. Implement the following in VHDL using behavioral coding a) 4X1multiplexer using concurrent statement (with select statement)

b) 4X1 multiplexer using sequential statements (case statement) 9. Implement a combinational 2X4 decoder in VHDL. Using a) behavioral coding b) structural coding using MUX as a component 10. Design a sequential circuit with one input that produces one output signal under the following condition. Whenever input signal has the same value over three successive clock cycles, an output of 1 is generated, and 0 otherwise. Assume that the value of input signal for a given clock cycle is defined at the time of the rising clock edge at the end of the clock cycle. Write a VHDL code to implement the same either in behavioural model or structural model. 11. Write a VHDL program using behavioural model to implement 4 bit Johnson counter. 12. Write a VHDL program using behavioural model to implement 4 bit Ring counter 13. Write a VHDL program using structural model to implement 3 bit magnitude comparator 14. Write a VHDL program using behavioural model to implement 4:1 Multiplexer using CASE statement. 15. Write a VHDL program using behavioural model to implement 1:4 Demultiplexer using CASE statement. 16. Write a VHDL program using structural model to implement 3:8 decoder. 17. Develop a sequential circuit with a single data input S and a single data output Y. The output is 1 when the input value in the current clock cycle is different from the input value in the previous clock cycle, as shown in the timing diagram in Figure below

18. Write a VHDL structural code to implement BCD to Excess 3 codes designed through Mealy machine design. 19. Write a VHDL Structural code to detect the overlapping sequence detector 101 for a sequential circuit with 1 input and 1 output. 20. Write a VHDL code for parity generator that generates 5 bit odd parity generator for 4 bit input number using LUT method.

21. Design a circuit that counts 16 clock cycles and produces a control signal, ctrl, that is 1 during every eighth and twelfth cycle. a) Write a VHDL code to design a 4 bit magnitude comparator. b) Also design a 8 bit magnitude comparator using the 4 bit magnitude comparator as component. 22. Develop a VHDL model for a pipelined circuit that computes the average of corresponding values in three streams of input values, a, b and c. The pipeline consists of three stages: the first stage sums values of a and b and saves the value of c; the second stage adds on the saved value of c; and the third stage divides by three. The inputs and output are all signed fixed-point numbers indexed from 5 down to 8. 23. Develop a VHDL model for an accumulator that calculates the sum of a sequence of fixedpoint numbers. Each input number is signed with 4 pre-binary-point and 12 post-binarypoint bits. The accumulated sum has 8 pre-binary-point and 12 post-binary-point bits. A new number arrives at the input during a clock cycle when the data_en control input is 1. The accumulated sum is cleared to 0 when the reset control input is 1. Both control inputs are synchronous. 24. Design a BCD to seven segment display decoder and implement the same in VHDL using behavioural model. 25. Design a 2 digit BCD adder and implement the same in VHDL using behavioural model. 26. Design a 1 digit BCD adder and implement the same in VHDL using behavioural model. 27. Design a 4 bit array multiplier and implement the same in VHDL using structural model. ) 28. An array multiplier takes ( to calculate a product. Design an array multiplier which is faster than this. (Pass carry diagonally downwards rather than to left). Write VHDl code and calculate delay.

29. Implement a 4-bit shift register in VHDL with parallel- in, shift- right, shift- left and parallelout options. 30. Implement a full adder in VHDL with structural coding using half adder as component. Also write function & procedure for full adder. 31. Implement an ALU for addition, subtraction, increment A, decrement A with two 4 -bit inputs A and B. 32. Implement a D-latch with a data input, an enable input and a data output port 33. Implement a D flip-flop (with asynchronous reset) in VHDL using a process a) With sensitivity list b) Without sensitivity list 34. Implement a 4-bit shift register in VHDL with parallel- in, shift- right, shift- left and parallelout option. 35. Determine a mealy machine for detecting 101 sequence in VHDL a) Using single process b) Using two processes 36. Determine a Moore machine for the above problem and implement in VHDL 37. a) Implement a JK flip-flop in VHDL b) Using this flip-flop implement a four bit ripple counter 38. Implement a MOD- 6 synchronous counter a) Using behavioral coding b) Using behavioral coding with FSM approach 39.