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1

AIM:
1. To design, construct and test an Inverting Amplifier
2. To design, construct and test an Non Inverting Amplifier
3. To measure CMRR of the differential Amplifier
APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 30 V 1
4. Op-Amp IC 741 1
5. Bread Board - 1
6. Resistors 10K,4.7K Each 1

THEORY:
An amplifier is a circuit that receives a signal at its input and delivers an
undistorted larger version of the signal at its output. The amplifier circuit uses feedback
i.e. output signal is fedback to the input either directly or via another network and
therefore called as feedback amplifiers or closed loop amplifiers. The feedback can be
positive or negative, depending on the polarity of the signal fedback with respect to the
input signal. An amplifier with negative feedback is preferred as it has self correcting
ability against any change in output voltage caused by changes in environmental
conditions. The performance of the feedback amplifier does not depend on the open loop
gain of the Op amp (A
OL
)

since the closed loop gain (A
CL =
V
0
/V
in
) is independent of A
OL.
An Op amp can amplify both ac and dc signals. In dc amplifier the dc output
voltage changes in response to changes in dc input levels. A dc amplifier can be
inverting, non inverting or differential. To reduce the output offset voltage to zero, i.e., to
improve the accuracy of the dc amplifiers, the offset null circuitry of the Op amp should
be used. For Op amps without offset null capability, an external offset voltage
compensating network should be used.
EX. NO: 1 INVERTING, NON-INVERTING AMPLIFIERS AND
DIFFERENTIAL AMPLIFIER
DATE:
2




Fig (i): VOLTAGE FOLLOWER




Fig (ii): INVERITNG AMPLIFIER





3

When Op amps are used to amplify ac signals, it is necessary to use a coupling
capacitor at the input.The inverting amplifier circuit is shown in figure (ii). Assuming
that the voltage between negative and positive inputs is essentially zero, the output is not
in saturation and the current drawn by either negative and positive input terminal is
negligible, it can be shown that the closed loop gain of the inverting amplifier as


in
V
R
R
A
1
F
CL
= (1)
And the output is given by


in
V
R
R
V
1
F
0
= (2)
The circuit of figure (iii) shows the non inverting amplifier. The closed loop gain, in this
case is given by

|
|
.
|

\
|
+ =
1
F
CL
R
R
1 A
(3)

And the output,
in
V
R
R
1 V
1
F
0 |
|
.
|

\
|
+ = (4)
The voltage follower is as shown in figure (i). It is also referred to as source follower,
buffer amplifier or isolation amplifier. The output voltage V
0
is equal to V
in
and closed
loop gain is unity.
DIFFERENTIAL AMPLIFIER:
Many electronic devices use differential amplifiers internally. The output of an
ideal differential amplifier is given by:
)
in
V
in
(V A
out
V
d

+
+
= (5)

4


Fig (iii): NON INVERITNG AMPLIFIER

a. COMMON MODE

b. DIFFERENTIAL MODE
Fig (iv): DIFFERENTIAL AMPLIFIER
5

Where V
in
+
and

V
in
-
are the input voltages and A
d
is the differential gain. In
practice, however, the gain is not quite equal for the two inputs. This means, for instance,
that if V
in
+
and V
in
-
are equal, the output will not be zero, as it would be in the ideal case.
A more realistic expression for the output of a differential amplifier that includes a
second term.


|
|
.
|

\
|

+
+
+
+
=
2
in
V
in
V
A )
-
in
V
in
(V A V
c
d out

(6)

Where A
c
is called the Common-mode gain of the amplifier. As differential
amplifiers are often used when it is desired to null out noise or bias-voltages that appear
at both inputs, a common-mode gain is usually considered good. The Common-mode
rejection ratio(CMRR) is defined as the ratio between differential-mode gain and
common-mode gain, indicates the ability of the amplifier to accurately cancel voltages
that are common to both inputs.


c
A
A
CMRR
d
= (7)

A
c
is zero and the CMRR is infinite. Note that differential amplifier is a more general
form of amplifier than one with single input. By grounding one input of a differential amplifier, a
single-ended amplifier results. An operational amplifier is a differential amplifier with very high
differential-mode gain, very high input impedances and low output impedance.
DESIGN:
Design of an inverting amplifier with closed loop gain of x:
We know for an inverting Amplifier A
CL
=,-R
F
/ R
1
,
A
CL
=, -R
F
/ R
1
, = x
R
F
=x R
1

Choose R
1
=4.7K
Then R
F
=x 4.7K
For a gain of 2, x=2
R
F
=2 4.7k = 9.4KO
6



Fig.(v). VOLTAGE FOLLOWER CIRCUIT using MULTISIM



Fig.(vi). INVERTING AMPLIFIER CIRCUIT using MULTISIM





7

Practically available nearest resistor value = 10 KO




Design a non-inverting amplifier with closed loop gain of y:
We know for a Non-inverting Amplifier A
CL
= , 1 + R
F
/ R
1
,
A
CL
= , 1 + R
F
/ R
1
,=y
R
F
=y R
1

Choose R
1
=4.7K
Then R
F
=yx4.7K,
For a gain of 3,
R
F
=2 4.7k = 9.4KO, R
F
~10kO
A
CL
= , 1 + R
F
/ R
1
, =, 1+ 10

/ 4.7 ,= 3


PROCEDURE:
1. Rig up the circuit of figure (ii) with the designed value of the components.
2. Check for the correct polarity of the supply voltages and pin connections of the
Op amps.
3. Switch on the power supply to the circuit.
4. If the input signal is dc, measure the input and the output voltages using digital
mult imeter. Note the polarity of the output. Enter the readings in table (ii)
5. If the input signal is ac, display the input and output signals on a CRO. Measure
the amplifiers of the input and output signals. Observe the phase of the output
signal with respect to the input signal. Draw the signals to scale on a graph sheet.
6. Calculate the closed loop gain and compare with the designed value.
7. Repeat step 1 to 6 for voltage follower circuit of figure (i)
8. Repeat step 1 to 7 for the non inverting amplifier of circuit shown in figure (iii).
Enter the readings in table (3)

8



Fig.(vii). NON INVERTING AMPLIFIER CIRCUIT using MULTISIM




Fig.(viii). COMMON MODE CIRCUIT

9

COMMON MODE REJECTION RATIO:
1. Rig up the circuit as shown in figure (iv). It is in the common mode configuration.
2. All resistors must be matched and balanced
3. Check for the power supply pins and correct polarity of the supply voltages to Op
amp and then switch on the power supply.
4. Apply a sinusoidal signal of amplitude 0.5V (1V
p-p
)
5. Measure the output voltage V
01

6. Rig up the circuit as shown in figure(iv). It is in the differential mode configuration.
7. Repeat steps 2, 3, and 4.
8. Measure the output voltage V
02

9. Calculate CMRR as follows
10. Common mode gain A
cm
= V
01
/V
in
11. Differential mode gain A
dm
= V
02
/V
in

12. Common mode rejection ratio(CMRR) = A
dm
/A
cm



PROCEDURE FOR MULTISIM:
1. Construct the circuit shown above using Multisim software.
2. Connect the oscilloscope shown in the diagram above for verifying voltage
follower circuit, inverting, non-inverting and differential amplifier circuit.
3. Run the circuit and double click the connected oscilloscope
4. Vary the time base in the oscilloscope to the required value.
5. Check the input and output values with the expected values.








10

Table 1: VOLTAGE FOLLOWER
S.No V
in
V
0













Table 2: INVERTING AMPLIFIER
S.No V
in
V
o
GAIN
MEASURED DESIGNED














11

PRELAB QUESTIONS:
1. List out the charactertics of ideal op-amp.
2. What is an inverting amplifier?
3. What is non inverting amplifier?
4. What are the modes in differential amplifier?
5. Write any two applications for inverting amplifier?
6. Design an inverting amplifier with closed loop of gain 5.

RESULT:



CORE - COMPETENCY LEARNED:




POSTLAB QUESTIONS:
1. What are the three factors that affect the electrical parameters of an Op amp?
2. What are the causes for offset voltage, offset current and bias current?
3. How the loading effect can be avoided in an inverting amplifier?
4. What is the output offset voltage? How the offset voltage is reduced to zero in
case of op-amp?
5. Give the significance of CMRR.







12


Table 3: NON INVERTING AMPLIFIER

S.No V
in
V
o
GAIN
MEASURED DESIGNED

















Fig.(ix). DIFFERENTIAL MODE CIRCUIT

13



CALCULATION:

Common mode gain A
cm
=


Differential mode gain A
dm
=


Common mode rejection ratio (CMRR) =


MARKS ALLOCATION
Details
Marks Allotted Marks Awarded
Preparation 20
Conducting 20
Calculation / Graphs 15
Results 5
Basic understanding (Core
competency learned)
15
Viva 10
Record 15
Total 100

Repetition less 25% of the total marks awarded as above.



Signature of faculty
14



Fig(i): DIFFERENTIATOR


Fig(ii): Frequency response of differentiator



15

AIM:
1. To design and test a Differentiator circuit for the operating frequency of
0.5 KHz using op-Amp IC 741.
2. To design an Integrator circuit for the operating frequency 0.5 KHz using
op-Amp IC 741.
APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 30 V 1
4. Op-Amp IC 741 1
5. Bread Board - 1
6. Resistors 15kO ,820O Each 1
7. Capacitors 0.55nF,0.01uF Each1

THEORY:
DIFFERENTIATOR:
The differentiator circuit performs the mathematical operation of differentiation;
(i.e.) output waveform is the derivative of the input waveform. The relationship between
the input and output of the differentiator can be shown as
V
o
= - R
f
C
1
(

dV
in
/dt

) (1)
The gain of the differentiator circuit is given by
A = R
f
/ X
C1
= C
1
R
f
(2)
The gain of the circuit increases with increase in frequency at a rate of
20db/decade. This makes the circuit unstable. Also the input impedance X
c1
decreases
with increase in frequency which makes the circuit very susceptible to high frequency
noise. When amplified this noise can completely over ride the differentiator output signal.


EX. NO: 2
DIFFERENTIATOR AND INTEGRATOR
DATE:
16


Fig (iii): DIFFERENTIATOR MODEL WAVEFORM

Table 1: DIFFERENTIATOR
S.No Input Output
1.
Amplitude
( No. of div x Volts per div )

2.
Time period
( No. of div x Time per div )

3.

Calculated Frequency












17

The frequency response of the differentiator is shown fig. (ii)., where f
a
is the
frequency at which the gain is zero dB and it is given by
f
a
= 1/(2R
f
C
1
) (3)
Also f
c
is the gain bandwidth of the Op amp, and f is some relative operating
frequency. Both the stability and the high frequency noise problems can be corrected by
the addition of two components R
f
and C
f
as shown in the differentiator. This circuit is a
practical differentiator, the frequency response of which is shown fig. (ii) in model graph
by dashed line. As the frequency increases from f to f
a
, the gain increases at
20dB/decade, after f
b
the gain decreases at the rate of 20dB/decade. This 40 dB / decade
change in gain is caused by the R
f
, C
f
and its combinations. The gain limiting frequency
f
b
is given by
f
a
= 1/(2R
F
C
1
) (4)
Where R
1
C
1
= R
f
C
f
(5)
The circuit components R
1
,

C
1
, R
f
and C
f
should be selected such that
f
a
< f
b
< f
c
(6)
Where f
a
and f
b
are given by equations (3) and (4) respectively and f
c
is the unity gain
bandwidth of the Op Amp. The input signal will be differentiated properly if the time
period T of the input signal is larger than or equal to R
f
C
f
i.e., TR
f
C
f ,
where
R
f
C
1
= 1/ (2f
a
).The differentiator is most commonly used in wave shaping circuits to
detect high frequency components in an input signal and also as a rate of change detector
in FM modulations.

INTEGRATOR:
A circuit in which the output voltage waveform is the integral of the input voltage
waveform is the integrator. Such a circuit is obtained by using a basic inverting amplifier
configuration if the feedback resistor R
f
is replaced by a capacitor C
f.
The relationship
between the input voltage and the output voltage of the integrator can be shown as
V
o
= - (1/R
1
C
f
)

V
in
dt + K (7)



18


Table 2: DIFFERENTIATOR V
in
=
INPUT
FREQUENCY
in Hz
OUTPUT VOLTAGE
in Volts
GAIN in dB
20log(V
o
/ V
in
)











Fig(iv): INTEGRATOR

19

Where K is the integration constant and is proportional to the value of the output voltage
V
0
at time t=0. The gain of the integrator is
|A| = 1 / (R
f
C
f
) (8)
The gain of the integrator decreases with increasing frequency. However at low
frequencies, such as at dc (=0) the gain becomes infinite. The Op - Amp

saturates, i.e.
the capacitor is fully charged and it behaves like an open circuit. Also when V
in
= 0, the
circuit would work as an open loop amplifier to the input offset voltage and produce an
error voltage at the output. To reduce the error voltage and the low frequency gain, the
feedback capacitor is shunted by a resistance R
f
as shown in an integrator circuit.The
frequency response of the integrator is shown in fig. (iv) . At frequency f
b
the gain is zero
dB

and is given by
f
b
= 1/(2R
1
C
1
) (9)
For frequencies f to f
a
the gain (dc gain) is constant and is given by
|A| = R
f
/R
1
(10)
After f
a
the gain decreases at a rate of 20 dB/decade, and the circuit acts as an
integrator. The integrator is most commonly used in analog computers, ADC and signal-
wave . The gain limiting frequency f
a
is given by
f
a
= 1/(2R
f
C
1
) (11)

DESIGN:
DIFFERENTIATOR:
Design a differentiator circuit working over a frequency of 10Hz to 1 KHz.
[Select f
a
equal to the highest frequency of the input signal to be differentiated.
Assuming a value of C
1
<1F, calculate the value of R
f
using equation (3). Choose f
b
= 20f
a

and calculate the values of R
f
and C
f
such that R
1
C
1
= R
f
C
f
]
Let fa

= 1 / (2 R
f
C
1
)=1000Hz
Choosing C
1
=0.01uF
Therefore R
f
= 15.9K
Let f
b
= 1 / (2 R
1
C
1
) = 20f
a

Therefore R
1
= 795.7 Ohm
Choose R
1
= 820 Ohm
20




Fig(v): Frequency response of integrator




Input: Sine wave







Output: Cosine wave


Fig (vi): INTEGRATOR
21


Since R
1
C
1
=R
f
C
f
Therefore C
f
= R
1
C
1
/R
f
= 0.55nF
INTEGRATOR:
Design the integrator circuit operating at a frequency of about 0.5 KHz:
[The value of the circuit components must be such that f
a
< f
b
. Choose f
b
= 10f
a
and
C
f
< 1F. Calculate R
1
and R
f
using equations (9) and (11) respectively. The input signal
will be integrated properly if the period T of the signal is larger than or equal to R
f
C
f
i.e.
TR
f
C
f
where R
f
C
f
= 1/(2 f
a
)]
The period of input signal = 1/500 = 2msec
Choose R
f
C
f
T
R
f
C
f
= 2msec
Choose C
f
= 0.01uF
Therefore R
f
= 33 K
Take R
f
= 33 K
Choose f
b
= 10f
a
R
1
= R
f
/10
= 3.3K

PROCEDURE:
1. Rig up the circuit as shown in figure (i) & (iv) with the designed values of the
components.
2. Connect the input signal from the function generator.
3. Set suitable voltage sensitivity and the time base on CRO. Switch on the power
supply.
4. Check for the correct polarity of supply voltages to the Op Amp. Switch on the
power supply.
5. Set the input signal to 5v peak to peak sinusoidal at 500Hz.Observe the input and
output signals on the CRO. Draw the waveforms to scale on a graph sheet.
6. Measure the peak value and the phase angle of the output signal with respect to
the output signal and mark on the graph sheet.
22




Fig. (vii) DIFFERENTIATOR CIRCUIT USING MULTISIM



Fig. (viii) DIFFERENTIATOR CIRCUIT WITH BODE PLOTTER




23

7. Repeat step 6 for different frequencies. Find the maximum frequency at which the
circuit performs the operation. Compare it with the theoretical value. Tabulate the
frequency and the amplitude of the output signal and compare with the theoretical
value.
8. Set the input signal to 5v peak to peak square wave of frequency within the
desired range. Observe the waveforms on the CRO and plot them on graph sheet
to scale. For square wave input, the output signal will be as shown in model graph
fig.no. (iii).
PROCEDURE FOR MULTISIM:
1. Construct the circuit shown above using multisim software
2. Connect the oscilloscope and verify the input and output.
3. Connect the bode plotter to the output side and connect the AC source to the input
side.
4. Run the circuit
5. Now double click the connected bode plot to check the magnitude and phase
response.
6. Click Simulate
7. Check the graph for determining gain versus frequency and phase versus frequency.

PRELAB QUESTIONS:
1. Design an differentiator with f
a
=f
max
=100Hz.
2. Draw the frequency response of differentiator.
3. What are the changes to be done in a differentiator to get the integrator?
4. What is the other name of integrator and why is it called so?
5. Design an integrator with f
a
=f
max
=2KHz.

RESULT:




24



Fig. (ix) DIFFERENTIATOR CIRCUIT WITH FUNCTION GENERATOR


Fig. (x) INTEGRATOR CIRCUIT

Fig. (xi) INTEGRATOR CIRCUIT WITH BODE PLOTTER
25

CORE - COMPETENCY LEARNED:






POSTLAB QUESTIONS:
1. Write down the input and output relations for the differentiator and integrator?
2. Derive the design equations of the differentiator and integrator?
3. How the saturation is avoided in practical integrator?
4. What is the condition for good differentiator?
5. What is the slope of the frequency response of the integrator?


















26

Table 3: INTEGRATOR
S.No Input Output
1.
Amplitude
( No. of div x Volts per div )

2.
Time period
( No. of div x Time per div )

3. Calculated Frequency

Table 4: INTEGRATOR V
in
=
INPUT FREQUENCY
in Hz
OUTPUT VOLTAGE
in Volts
GAIN in dB
20log(V
o
/ V
in
)


















27

MARKS ALLOCATION
Details
Marks
Allotted
Marks
Awarded
Preparation 20
Conducting 20
Calculation / Graphs 15
Results 5
Basic understanding (Core
competency learned)
15
Viva 10
Record 15
Total 100

Repetition less 25% of the total marks awarded as above.



Signature of faculty

















28



Fig (i): INSTRUMENTATION AMPLIFIER


Table 1: INSTRUMENTATION AMPLIFIER
S.No V
1
V
2
V
O
GAIN
MEASURED DESIGNED












29



AIM:
To design, test and construct an instrumentation amplifier for a gain of 3.

APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 30 V 1
4. Op-Amp IC 741 3
5. Bread Board 1
6. Resistors 1K 7

THEORY:
The commonly used instrumentation amplifier is the one using three Op-amps.
This circuit provides high input resistance for accurate measurement of signals from
transducer. In this circuit, a non-inverting amplifier is added to each of the basic
differential amplifier circuit input terminal. The Op-amps A
1
and A
2
are non-inverting
amplifier forming the input or first stage of the instrumentation amplifier. The output Op-
amp A
3
is normal differential amplifier forming the output stage of amplifier. The output
stage is a standard basic differential amplifier. So, if the output of the Op-amp A
1
is V
1

and the output of Op-amp A
2
is V
2
then,
V
0
=R
2
/R
1
(V
2
-V
1
) (1)
ADVANTAGES:
1. With the help of variable resistance R
S
, the gain can be easily varied without disturbing
the symmetry of the circuits.

Ex. No: 3

INSTRUMENTATION AMPLIFIER
DATE:
30





Fig. (ii) INSTRUMENTATION AMPLIFIER CIRCUIT














31

2. Gain depends on external resistances and hence can be adjusted accurately and made
stable by selecting high quality resistance.
3. The input impedance depends on the impedance of non-inverting amplifier which is
extremely high.
4. The output impedance of A
3
which is very low. This is required by an instrumentation
amplifier.
5. CMRR of the op-amp A
3
is very high and most of the common mode signal will be
rejected.
APPLICATION:
In many industrial applications, it is necessary to measure various physical
quantities such as temperature, humidity, water flow, etc.

DESIGN:
Design an instrumentation amplifier for a gain of 3.
Design for R
1
:
V
o
= 9V, V
1
= 10V, V
2
= 7V
Assume R
1
= R
2
= 1k


R
1
1
= 1k

PROCEDURE:
1. Rig up the circuit of instrumentation amplifier as shown in figure with the
designed values of the components.
2. Connect the input signals V
1
and V
2
from two signal generator.
3. Connect the CRO probe to the output terminal of the A
3
amplifier. Select suitable
voltage sensitivity and time base on the CRO.
4. Check for the correct polarity of the supply voltage to op-amp and switch ON the
power supply of the circuit.
32
































33


5. Display the input and output signals on the CRO. Measure the amplitude and time
period of the input and output signals. Observe the phase of the output signal with
respect to the input signal.
6. Note the amplitude of the output waveform for different values of (V
1
V
2
).
7. Plot input and output waveforms to scale on a graph sheet.

PROCEDURE FOR MULTISIM:
1. Construct the circuit shown above using Multisim software.
2. Connect the oscilloscope shown in the diagram above for verifying
instrumentation amplifier circuit.
3. Run the circuit and double click the connected oscilloscope
4. Vary the time base in the oscilloscope to the required value.
5. Check the input and output values with the expected values.
6. Measure the amplitude and time period of the input and output signal. Observe the
amplitude of the output waveform for different values of (V
1
V
2
).
PRELAB QUESTIONS:
1. What is the need for an instrumentation amplifier?
2. Give the features of instrumentation amplifier.
3. When does loading occur in instrumentation amplifier?
4. Define CMRR. Give the CMRR status of instrumentation amplifier.
5. How can the gain be controlled by resistance?
RESULT:



CORE - COMPETENCY LEARNED:




34
































35


POSTLAB QUESTIONS:
1. Give the gain formula of instrumentation amplifier.
2. How the balanced condition is maintained initially?
3. How is the loading effect avoided?
4. At what condition, the non-inverting amplifier acts as a voltage follower?
5. What do you mean by unbalanced condition?

MARKS ALLOCATION
Details
Marks
Allotted
Marks
Awarded
Preparation 20
Conducting 20
Calculation / Graphs 15
Results 5
Basic understanding (Core
competency learned)
15
Viva 10
Record 15
Total 100

Repetition less 25% of the total marks awarded as above.




Signature of faculty



36




Fig(i): FIRST ORDER LOW PASS FILTER















Fig (ii): FREQUENCY RESPONSE OF LOW PASS FILTER

F
h

A
m

A
m
/ 2
Frequency in Hz
Gain in dB
Practical response
Ideal response
Pass band Stop
band
37



AIM:
1. To design, construct and test a first order low pass filter for a cut off
frequency of 5 KHz and to find corner frequency from frequency response
curve.
2. To design, construct and test a first order band pass filter with a bandwidth
frequency of 1 KHz to 5 KHz and a pass band gain of 4.
APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 30v 1
4. Op-Amp IC 741 1
5. Bread Board 1
6. Resistors 4.7K,3.3K 3,1
7. Capacitors 0.01uF 1

THEORY:
The filter is a frequency selective circuit that passes signals of specified band
of frequencies and attenuates outside that band. Filters may be classified as analog or
digital, passive or active, audio or radio frequency. Based on the pass band frequencies
the filters are classified as i) Low pass filter ii) High pass filter iii) Band pass filter
iv) Band reject filter.
A low pass filter shown in fig.(i), has a constant gain (V
o
/V
in
) from 0Hz(dc)
to a certain frequency called higher cut off frequency corner f
h
. At corner frequency the
gain is 3dB below the pass band gain. Above f
h
the gain decreases with an increase in
frequency. Figure (ii) shows the band pass filter. It has a passband between two cut off
EX. NO:4

ACTIVE LOW PASS FILTER AND BAND PASS FILTER
DATE:
38

frequencies f
h
and f
l
such that f
h
>f
l
. Any input with frequency outside this pass-band is
attenuated.
Table 1: LOW PASS FILTER: V
in
=
S.No
Frequency

(Hz)
First order LPF Gain=2
V
0
(volts) Gain=V
o
/V
in
Gain(dB)=20 log (V
o
/V
in
)










39


The order of the filter indicates the rate at which the gain changes while the input
frequency is approaching or exceeding the corner frequencies of the filter. For the first
order low pass filter, for f>f
h
the gain decreases at the rate of 20dB/decade (roll off rate)
of frequency. For second order filter the changes in gain is 40dB/decade and for third
order filter is 60dB/decade and so on. Higher order filters can be formed by cascading
first and second order filter sections. For example a third order filter is constructed by
cascading first and second order filters designed for same corner frequency. A fourth
order filter is formed by cascading two second order filters.
Practical active filters that approximate the ideal response are of Butterworth type,
Chebyshev type and Causer type. The key characteristics of the Butterworth type filter
are that it has flat pass-band as well as stop-band.Active filters have the following
advantages over passive filters: i) Flexibility in adjusting the gain and frequency. Since
the op-amp is capable of providing a gain the input signal is not attenuated as it is in a
passive filter. An active filter is easier to tune or adjust. ii) No loading problem because
of the high input impedance and low output impedance of the op-amp. So the active filter
does not cause loading of the source or load. iii) Cost effective: active filters are more
economical than passive filters. This is because of the variety of cheaper op-amps and the
absence of inductors.
DESIGN:
1. FIRST ORDER LOW PASS FILTER:
For f
h
= 5 KHz
f
h
= 1/2RC
Choose C = 0.01uF
R = 1/2f
h
C
= 1/ (2 x 5 x 10
3
x 0.01 x 10
-6
)
R = 3.18K
Take R=3.3K
For gain A
CL
= 2
A
CL
=
1
f
R
R
1+ = 2
40

R
f
/ R
1
= 1;R
f
/R
1
=1 i.e. =R
1
=4.7K


Fig (iii): BAND PASS FILTER



Fig (iv): FREQUENCY RESPONSE OF BAND PASS FILTER




41


2.BAND PASS FILTER:
f
l
=1KHz, f
h
= 5KHz and gain A
o
= 4
A
o1
A
o2
=4,where, f
h
= Higher cutoff frequency
f
l
= Lower cutoff frequency
A
o1
= Gain of HPF
A
o2
= Gain of LPF
A. HIGH PASS FILTER:
A
o1
= 1+R
f1
/ R
i1

For A
o1
=2,

1+R
f1
/ R
i1
= 2
Choose R
f1
= 6.8K
Choose R
i1
= 6.8K
f
1
= 2KHz
f
1
= 1/2 R
1
C
1
Choose C = 0.01uF
R
1
= 1 / (2x2x10
3
x0.01x10
-6
) = 7.9 K
B. LOW PASS FILTER:
For A
o2
=2,

1+R
f2
/ R
i2
= 2
R
f2
/ R
i2
= 1
Choose R
f2
= 6.8K
Choose R
i2
= 6.8K
f
h
= 5KH
Z

f
h
= 1/2R
2
C
2
C = 0.01uF
R
2
= 1/(2x5x10
3
x0.01x10
-6
) = 3.3 K




42




Fig (v) LOW PASS FILTER CIRCUIT using MULTISIM



Fig (vi) BAND PASS FILTER CIRCUIT using MULTISIM






43


PROCEDURE:
1. Fig up the circuit of first order LPF with the desired values of the components.
2. Connect the input signal to the circuit from the signal generator.
3. Connect the input and output signals of the filter to the channels 1 and 2 of the
CRO separately.
4. Select the suitable voltage division and time division on the CRO.
5. Check for the correct polarity of supply voltage to OP-AMP and switch on the
power supply.
6. Adjust the input signal amplitude to 1
V
peak to peak and measure the output
voltage (amplitude) for the different frequencies. Take reading from one tenth of
the corner frequency to 10 times the corner frequency of suitable intervals.
Tabulate the readings in the table.
7. Calculate the gain in dB using the formula
AV= 20 log
10
(V
o
/V
in
) dB
8. Plot the gain in dB versus frequency characteristics in a semilog sheet and mark
the corner frequency.
PROCEDURE FOR MULTISIM:
1. Construct the circuit shown above using Multisim software.
2. Connect the oscilloscope shown in the diagram above for verifying the first order
low pass and band pass filter.
3. Run the circuit and double click the connected oscilloscope
4. Vary the time base in the oscilloscope to the required value. Run the bode plot
using the parameters.
5. Observe that the high frequency response is attenuated while the low frequency
response is similar to the basic op amp Bode plot for low pass filter.
6. Use the cursor function to find the high frequency cutoff point for low pass filter
& bandpass filter.
PRELAB QUESTIONS:
1. What are the limitations of active filters?
2. Define pass band and stop band of a filter.
44

3. What is called cutoff frequency?

Table 2: BAND PASS FILTER V
in
=
S.No
Frequency

(Hz)
First order BPF Gain=4
V
0
(volts) Gain=Vo/V
in
Gain(dB)=20 log (V
o
/V
in
)
































































































45


4. Why do we go for higher order filters?
5. What basis will you divide the band pass filter?

RESULT



CORE - COMPETENCY LEARNED:

POSTLAB QUESTIONS:
1. Why the cutoff frequency is chosen at 3dB below the maximum frequency?
2. On what does the damping coefficient of a filter depend?
3. From the experiment determine the roll off rate for BPF?
4. What are the important parameters in band pass filters?
5. How the critical frequency can be controlled in an active filter?
MARKS ALLOCATION
Details
Marks
Allotted
Marks
Awarded
Preparation 20
Conducting 20
Calculation / Graphs 15
Results 5
Basic understanding (Core
competency learned)
15
Viva 10
Record 15
Total 100

Repetition less 25% of the total marks awarded as above.

46

Signature of faculty






























47


AIM:
To design and test a Schmitt trigger circuit using op-amp
APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 30 V 1
4. Op-Amp IC 741 1
5. Bread Board 1
6. Resistors 200k,6.8k 1,2

THEORY:
A comparator compares the signal voltage on one input of an op-amp with a
known voltage called the reference voltage on the other input.It is an open loop op-amp
with two analog inputs and digital output. The output may be at positive or negative
saturation voltage, depending on which input is larger. The basic comparator is shown in
fig 1.The zero crossing detector is the comparator with the reference voltage set to zero.
If the input signal V
in
to a comparator is low frequency or slowly varying signal, it will
take more time to reach the reference voltage level. The output V
o
, may not switch
quickly from one saturation voltage to other. On the other hand, because of the noise at
the op-amps input terminals, the output V
o
may fluctuate (oscillate) between the two
saturation voltages around the reference voltage level. Both these problems can be
overcome with the use of regenerative or positive feedback. The comparator with the
positive feedback is known as Schmitt- trigger or hysteresis comparator. The input signal
V
in
triggers the output V
o
to change state every time it exceeds certain voltage levels
called the upper and lower threshold voltage levels.

EX. NO : 5
SCHMITT TRIGGER
DATE:
48



Fig(i): SCHMITT TRIGGER


Fig (ii): MODEL GRAPH
49


These are expressed as,
) V (
R R
R
V
sat
2 1
1
UT
+
+
= (1)

) V (
R R
R
V
sat
2 1
1
LT

+
= (2)
V
UT
and V
LT
are to be made larger than the input noise voltages to estimate false output
transition.For minimum dc off set
2
1
OM
R
R
R = (3)
The hysterisis voltage is V
hy
= V
UT
V
LT
(4)
)] V ( V [
R R
R
V
sat sat
2 1
1
hy
+
+
= (5)

DESIGN:
To design a hysteresis comparator with threshold voltage levels of 0.5V with
supply voltages 15v. The signal is sinusoidal with 2
V
peak to peak.
V
UT
= V
LT
=
2 1
sat 1
R R
V R
+

0.5=
2 1
1
R R
) 15 ( R
+


2 1
1
R R
R
+
=
15
5 . 0


2 1
1
R R
R
+
=
30
1

30 R
1
= R
1
+ R
2

R
2
= 29 R
1

Choose R
1
= 6.8k
Then R
2
= 29 x 6.8 k
R
2
= 200k
R
OM
= R
1
,, R
2,
R
OM
~ 6.8k
50


Fig (iii): SCHMITT TRIGGER using MULTISIM

Table 1: SCHMITT TRIGGER
S.No Input(V
in
) Output (V
o
)
1. Amplitude
( No. of div x Volts per div )

2. Time period
( No. of div x Time per div )


Upper threshold voltage V
UT
=
Lower threshold voltage V
LT
=










51

PROCEDURE:
1. Rig up the Schmitt trigger circuit as shown in fig (i).
2. Take the input signal as sinusoidal voltage from signal generator.
3. Connect the CRO probe to display the input signal and output signal.
4. Set the CRO for the desired voltage sensitivity and time base. Switch on the
power supply to CRO.
5. Check the correct polarity of the supply voltages to the op-amp and switch on the
power supply.
6. Adjust the input signal to 2V peak to peak sinusoidal at 500Hz.
7. Observe the input and output waveforms. Draw the waveforms on the graph sheet.
Mark the threshold voltage levels and the output transitions corresponding to
them. Indicate the hysteresis voltage by plotting V
o
and V
in
.
PROCEDURE FOR MULTISIM:
1. Construct the circuit shown above using Multisim software.
2. Connect the oscilloscope shown in the diagram above for verifying Schmitt
trigger circuit.
3. Run the circuit and double click the connected oscilloscope
4. Vary the time base in the oscilloscope to the required value.
5. Check the input and output values with the expected values.
PRELAB QUESTIONS:
1. Write down the formula for V
UT
and L
UT
?
2. What is the basic difference between a basic comparator and the Schmitt trigger?
3. When is Schmitt trigger preferred to basic comparator?
4. Give an application of Schmitt trigger?
5. What is meant by lower trigger level in inverting Schmitt trigger?

RESULT:





52
































53

CORE - COMPETENCY LEARNED:



POSTLAB QUESTIONS:
1. How can the gain be increased?
2. What is advantage of CMOS Schmitt trigger?
3. How positive feedback eliminates oscillations around the comparison point?
4. Why there is a phase angle delay in the output square wave?
5. What is the output when the IC 741 is replaced by 555 timer IC?
MARKS ALLOCATION
Details
Marks
Allotted
Marks
Awarded
Preparation 20
Conducting 20
Calculation / Graphs 15
Results 5
Basic understanding (Core
competency learned)
15
Viva 10
Record 15
Total 100

Repetition less 25% of the total marks awarded as above.


Signature of faculty



54



Fig(i): ASTABLE MULTIVIBRATOR


Fig (ii): MODEL GRAPH






55


AIM:
1. To design and test an Astable Multivibrator circuit for the operating
frequency of 1KH
Z
using op-amp.
2. To design and test a Monostable Multivibrator circuit for the pulse
duration of 0.5ms using op-amp.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity
1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 30 V 1
4. Op-Amp IC 741 1
5. Bread Board 1
6. Resistors 15k,4.7k, 6.8k,15k,1.5k 2,1
7. Capacitors 0.1uf, 0.01uF 1
8. Diode 1N4148 2

THEORY:
ASTABLE MULTIVIBRATOR:
This is also known as free running oscillator. The principle of generation of
square wave output is to force an Op-Amp to operate in saturation region. Fraction
=R
2
/(R
1
+R
2
) of the output is fed back to the positive input terminal. Thus the reference
voltage V
ref
is V
0
and may take values as +V
sat
or V
sat
. The output is also fed back to
positive input terminal after integrating by means of a low pass RC combination.
Whenever input at the negative terminal just exceeds V
ref
, switching takes place resulting
in a square wave output. In astable multivibrator both the states are quasi stable.

EX. NO: 6

ASTABLE MULTIVIBRATOR AND MONOSTABLE
MULTIVIBRATOR
DATE:
56




Fig(iii): MONOSTABLE MULTIVIBRATOR

Fig(iv): MODEL WAVEFORM





57

Consider an instant of time when the output is at +Vsat. The capacitor now starts
charging towards +V
sat
through resistance R as shown in fig (ii). The voltage at the
positive terminal is held at +Vsat by R
1
and R
2
combination. This condition continues as
the charge on C rises, until it has just exceeded +V
sat
, the reference voltage. When the
voltage at the positive terminal becomes just greater than this reference voltage, the
output is driven to V
sat
.At this instant, the voltage on the capacitor is +Vsat. It begins
to discharge toward -V
sat
. When the output voltage switches to V
sat
the capacitor charges
more and more negatively until its voltage just exceeds V
sat
. The cycle repeats itself.
The frequency is determined by the time it takes the capacitor to charge from V
sat
to
+V
sat
and vice versa. The voltage across the capacitor is a function of time.

MONOSTABLE MULTIVIBRATOR:
Realization of monoshable using an op-amp is shown in fig (iii). The diode D
1
is
clamping diode connected across C
1
. The diode clamps the capacitor voltage to 0.7v
when the output is at +V
sat.
. A narrow negative triggering pulse V
t
is applied to the
noninverting input terminal, through diode D
2
.. The voltage at the positive input terminal
through R
1
R
2
potential divider is +V
sat.
Now if a negative trigger of magnitude V
in
is
applied to the positive input terminal so that the effective signal at this terminal is less
than 0.7V,the output of the op-amp will switch from +V
sat
to V
sat
. The diode will now
get reverse biased and capacitor starts charging exponentially to V
sat
through the
resistance R
f
. The voltage at the positive input terminal is now V
sat
. When the capacitor
voltage V
c
becomes just slightly more negative than V
sat
the output of the op-amp
switches back to +V
sat
. The capacitor C now starts charging to +Vsat through R
f
until V
c
is 0.7V. The various waveforms are shown in fig (iv). For R
1
=R
2,
the pulse width of the
monostable multivibrator is given by,
T=0.69RC (1)


58


Fig(v) ASTABLE MULTIVIBRATOR CIRCUIT USING MULTISIM

Fig(vi) MONOSTABLE MULTIVIBRATOR CIRCUIT USING MULTISIM







59

DESIGN:
1. ASTABLE MULTIVIBRATOR:
F = 1 KHz
T = 1ms
If R1=R2 and fed back fraction =
2 1
2
R R
R
+
= 0.5
Then T = 2RC ln3
If R
1
=1.16 R
2

Then T = 2RC
Choose R
1
=R
2
=15K
Take T = 2RC ln3
Choose C = 0.1F
Therefore R
f
=
3 ln 10 1 . 0 2
10 1
6
3
x x x
x

= 4.7K

2. MONOSTABLE MULTIVIBRATOR:
T = 0.69RC
Choose C
1
=0.1uF
0.5ms=0.69 x R x 0.1uF
R=0.5 x 10
-3
/ (0.69 x 0.1 x 10
-6
)=7.2K
R 6.8K
If R = 6.8K then T = 0.46msec
Choose R
1
=R
2
=15k, R
3
=1.5k, C
2
=0.01uf
PROCEDURE:
1. Rig up the astable multivibrator, monostable multivibrator circuit as shown in fig (i)
and fig(ii) with the designed value of the components.
2. Connect the CRO probes to display the voltage across the capacitor and the output
pulse.
3. Check the correct polarity of supply voltages to the op-amp and switch ON the
power supply to the circuits.

60

Table 1: ASTABLE MULTIVIBRATOR
S.No
Square
Output
Capacitor
output
1.
Amplitude
( No. of div x Volts per div )

2.
Time period
( No. of div x Time per div )



Table 2: MONOSTABLE MULTIVIBRATOR
S.No Input
Square
Output
Capacitor
output
1.
Amplitude
( No. of div x Volts per div )

2.
Time period
( No. of div x Time per div )

















61

1. Observe the waveform across the timing capacitor and the output square waveform
simultaneously and draw them on a graph sheet to scale.
2. Measure the frequency of the output square waveform and compare with the
designed value.
PROCEDURE FOR MULTISIM:
1. Construct the circuit shown above using Multisim software.
2. Connect the oscilloscope shown in the diagram above for verifying voltage .
3. Run the circuit and double click the connected oscilloscope
4. Vary the time base in the oscilloscope to the required value.
5. Measure the frequency with square wave and compare the designed value for both
multivibrator.
PRELAB QUESTIONS:
1. What is a Multivibrator?
2. List the types of Multivibrator. Differentiate them.
3. What is the significance of trigger pulse in a multivibrator?
4. What are the applications of the various types of Multivibrator?
RESULT:



CORE - COMPETENCY LEARNED:



POSTLAB QUESTIONS:
1. How can an asymmetric square wave be generated in an Astable Multivibrator?
2. What is gating circuit?
3. How can you obtain 50% duty cycle in astable multivibrator?
4. What is free running oscillator?
5. Which component decides the value of . Give its expression.

62

























63



MARKS ALLOCATION
Details
Marks
Allotted
Marks
Awarded
Preparation 20
Conducting 20
Calculation / Graphs 15
Results 5
Basic understanding (Core
competency learned)
15
Viva 10
Record 15
Total 100

Repetition less 25% of the total marks awarded as above.


Signature of faculty











64






Fig (i): RC PHASE SHIFT OSCILLATOR

Fig (ii):MODEL GRAPH

65


AIM:
1. To design and test a RC phase shift oscillator for a frequency 1KHz
2. To design and test a Wein Bridge oscillator for a frequency 5KHz

APPARATUS REQUIRED:
S. No Apparatus Range Quantity
1. Op-amp IC741 1
2. Resistor
68, 200K , 6.8K ,
3.3K , 10K , 4.7K
Each One
3. CRO 30 MHZ 1
4. Capacitors 0.01F, 0.1 F
2
3
5. Dual RPS (0-15)V 1
6. CRO probes - 1
7. Bread Board - 1

THEORY:
An oscillator is a type of feedback amplifier in which part of the output is
fed back to the input via a feedback circuit. The input to the oscillator is set to zero. If
the signal fedback is of proper magnitude and phase, the circuit produces alternating
currents or voltage.
RC PHASE SHIFT OSCILLATOR:
The circuit of RC- phase shift oscillator, consists of an op-amp as the
amplifying stage and three RC cascaded networks as the feedback voltage from the
output to the input of the amplifier. The op-amp is used in the inverting mode and
therefore provides a 180
0
phase shift to the signal at the inverting input terminal.

EX. NO: 7

RC PHASE SHIFT AND WEIN BRIDGE OSCILLATOR
USING OP AMP
DATE:
66



Fig (iii): WEIN BRIDGE OSCILLATOR

Fig (iv):MODEL GRAPH



67

The additional 180
0
, phase shift is provided by the cascaded RC networks. At some
specific frequency when the phase, shift of the cascaded RC networks is exactly 180
0
, the
gain of the amplifier is sufficiently large and the circuit will oscillate at that frequency.
The frequency of oscillation is given by,

RC
RC
f
o
065 . 0
6 2
1
= =
t
(1)
WEIN- BRIDGE OSCILLATOR:
The Wein-Bridge circuit is connected between the amplifier input and output
terminals. The bridge has a series RC network in one arm and a parallel RC network in
the adjoining arm. In the remaining two arms of the bridge the resistors R
1
and R
f
are
connected. The phase angle criterion for oscillation is the total phase- shift around the
circuit must be zero. This condition occurs only when the bridge is balanced, ie., at
resonance, setting R
2
=R
3
=R and C
2
= C
3
=C, the resonance frequency is given by

RC RC
f
o
159 . 0
2
1
= =
t
(2)

DESIGN:
1.RC PHASE SHIFT OSCILLATOR:
Choose C=0.01 F



R= 6.5 K
Take R=680 , R
L
= 4.7K
R
1
>10R
R
1
>10R=10*680 = 6.8 K
R
f
> 29R
1
R
f
> 29*6.80=197.2 K
Take R
f
=200 K (or) 220 K

6 3
0
10 0.01 10 1
0.065
C f
0.065
R


= =
68




Fig (iii): RC PHASE SHIFT OSCILLATOR using MULTISIM





Fig (iv): WEIN- BRIDGE OSCILLATOR using MULTISIM



69

2. WEIN- BRIDGE OSCILLATOR:
f
o
=5KHz

RC RC
f
o
159 . 0
2
1
= =
t

Choose C=0.01 F
= 3.18K

Take R=3.3 K
R
f
= 2R
1
Choose R
1
=R
L
= 4.7 K
R
f
=2*4.7 K=9.4 K
Take R
f
=10 K
PROCEDURE:
1. Rig up the circuit of RC phase shift oscillator as shown in fig (i) with designed
values of the components.
2. Connect the CRO probe to the output terminal of the oscillator. Select suitable
voltage sensitivity and time base on the CRO.
3. Check the correct polarity of the supply voltage to op-amp and switch ON the
power supply to the circuit.
4. Observe the output wave form on the CRO. If necessary, adjust the gain. Measure
the frequency of oscillation and the amplitude of the output signal and draw to
scale on the graph sheet. Compare the values with the designed value. Also
compare the phase shift of the wave form at the input terminal and at the output
terminal.
5. Repeat the steps 1 to 4 for the Wein Bridge Oscillator.
PROCEDURE FOR MULTISIM:
1. Construct the circuit shown above using Multisim software.
2. Connect the oscilloscope shown in the diagram above for verifying voltage
follower circuit.
3. Run the circuit and double click the connected oscilloscope
4. Measure the time period and amplitude in the oscilloscope to the required value.
5. Check the input and output values with the designed values.
6
10 * 01 . 0 * 5000
159 . 0

= R
70

Table 1: RC PHASE SHIFT OSCILLATOR
S.No Output
1. Amplitude
( No. of div x Volts per div )

2. Time period
( No. of div x Time per div )


Table 2: WEIN- BRIDGE OSCILLATOR
S.No Output
1. Amplitude
( No. of div x Volts per div )

2. Time period
( No. of div x Time per div )















71

PRELAB QUESTIONS:
1. Define an oscillator.
2. How are oscillators classified?
3. What is Barkhausen criterion?
4. What is difference between the Wein bridge oscillator and RC phase shift
oscillator?
5. What is slew rate?
RESULT:
Thus the design and testing of RC-phase and Wein-bridge oscillator is completed
and the frequencies are noted in the following table.

Designed Frequency Observed Frequency
RC Phase shift oscillator
Wein- Bridge Oscillator

CORE - COMPETENCY LEARNED:



POSTLAB QUESTIONS:
1. When does an Inter modal oscillation occur in RC Phase shift oscillator?
2. Which type of op-amps are used for low frequencies and high frequencies?
3. When is the total phase shift around the circuit zero in the case of Wein bridge
oscillator?
4. What is frequency stability of oscillators?
5. Design a RC phase shift oscillator to oscillate at 100Hz.


72

























73

MARKS ALLOCATION
Details
Marks
Allotted
Marks
Awarded
Preparation 20
Conducting 20
Calculation / Graphs 15
Results 5
Basic understanding (Core
competency learned)
15
Viva 10
Record 15
Total 100

Repetition less 25% of the total marks awarded as above.



Signature of faculty















74


Fig. (i).INTERNAL BLOCK DIAGRAM OF 555 TIMER



Fig. (ii).PIN DIAGRAM OF 555 TIMER








75



AIM:
To design and test an astable multivibrator using 555 timer with duty cycle
ratio of 25% .

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity
1. CRO 30 MHz 1
2. Power Supply 15V, +5V 2
3. Timer IC555 1
4. Bread Board - 1
5. Resistors 3.3K, 6.8K Each one
6. Capacitors 0.1uF 1

THEORY:
The 555 timer is connected as an astable multivibrator. Initially, when the output
is high, capacitor C starts charging towards V
cc
through R
A
and R
B
. As soon as capacitor
voltage equals 2/3 V
CC
, upper comparator [UC] triggers the flip flop and the output
switches low. Now comparator C starts discharging through R
B
and transistor Q
1
. When
the voltage across C equals 1/3 V
cc
lower comparator (LC) output triggers the flip flop
and the output goes high. Then the cycle repeats.

The capacitor is periodically charged and discharges between 2/3 V
cc
and 1/3 V
cc

respectively. The time during which the capacitor charges from 1/3 V
cc
to 2/3 V
cc
is
equal to the time the output is high and is given by

c
t =0.69 (R
A
+R
B
) C (1)
When R
A
and R
B
are in ohms and C is in farads. Similarly the time during which
the capacitor discharges from 2/3 V
cc
to 1/3 V
cc
is equal to the time the output is low and
is given by

d
t =0.69 R
B
C (2)




EX. NO: 8a
ASTABLE MULTIVIBRATOR USING 555
DATE:
76


Fig.(iii) ASTABLE MULTIVIBRATOR USING 555 TIMER

Fig.(iv) MODEL GRAPH
77


The total period of the output waveform is

d c
t t T + = =0.69(R
A
+2R
B
)C (3)
The frequency of oscillation

0
f =
T
1
=
C R R
B A
) 2 (
45 . 1
+
(4)
0
f is independent of supply voltage V
cc.
The duty cycle is the ratio of the time
d
t , during which the output is low to the
total time period T. This definition is applicable to 555 astable multivibrator only.
Conventionally, duty cycle is defined as the ratio of the time during which the output is
high to the total time period.

% duty cycle =
T
t
d
X 100
=
B A
B
R R
R
2 +
X 100 (5)


To obtain 50% duty cycle, a diode should be connected across R
B
and R
A
must be
a combination of a fixed resistor and a potentiometer can be adjusted for the exact square
wave.

DESIGN:

0
f =
C R R
B A
) 2 (
45 . 1
+

Choosing C = 0.1 F
R
A
+2R
B
= 14.5 K
D =
B A
B
R R
R
2 +
= 0.25
R
A
= 2R
B

R
B
=
4
5 . 14
= 3.625K
R
B
= 3.3K; RA

= 6.8K




78

Table 1: ASTABLE MULTIVIBRATOR
S.No Square Output Capacitor output
1.
Amplitude
( No. of div x Volts per div )

2.
Time period
( No. of div x Time per div )




Fig.(v).ASTABALE MULTIVIBRATOR USING IC555 IN MULTISIM













79

PROCEDURE:
1. Rigup the circuit of 555 Astable Multivibrator as shown in figure (iii) with the
designed value of components.
2. Connect the CRO probes to pin 3 and 2 to display the output signal and the
voltage across the timing capacitor. Set suitable voltage sensitivity and time base
on the CRO.
3. Switch on the power supply to CRO and the circuit.
4. Observe the waveforms on the CRO and draw to scale on a graph sheet. Measure
the voltage levels at which the capacitor starts charging and discharging, outputs
high and low, timing and frequency. Compare the measured values with
theoretical or designed values.
5. Switch off the power supply. Connect a diode across R
B
as shown in dashed lines
in fig (iii), to make the astable multivibrator with 50% duty cycle ratio. Switch on
the power supply. Observe the output wave form. If necessary change R
A
to get
50% duty cycle.
6. Switch off the power supply; connect a variable voltage source or a potentiometer
(10K) between control voltage pin 5 and the ground terminal to operate the
astable multivibrator as a VCO. Set the voltage source or the pot to minimum
voltage levels and switch on the power supply.
7. Vary the applied voltage to pin 5 (or the pot) from zero to V
cc
in suitable steps and
measure the frequency and tabulate the readings in table 1. The frequency will be
a function of the applied voltage.
8. Plot the frequency versus the applied voltage characteristics. Note down the
minimum and the maximum frequency levels.
PROCEDURE FOR MULTISIM:
1. Construct the circuit shown above using Multisim software.
2. Connect the oscilloscope shown in the diagram above for verifying voltage
follower circuit.
3. Run the circuit and double click the connected oscilloscope
4. Measure the time period and amplitude values
5. Check the designed value with the observed values.
80









































81

PRELAB QUESTIONS:
1. What are the modes of operation of a 555 timer?
2. Explain the functions of trigger, Reset, control voltage terminals of 555 timer?
3. What are the applications of 555 timer?
4. Define duty cycle.
5. Why is a diode necessary to obtain 50% duty cycle in the case of astable
multivibrator?
RESULT:




CORE - COMPETENCY LEARNED:



POSTLAB QUESTIONS:
1. How is an astable multivibrator connected into a pulse position modulator?
2. What is the need for diode in the charging path of an Astable Multivibrator?
3. Give the methods for obtaining symmetrical square wave.
4. How does a monostable multivibrator work?
5. A 555timer is configured to run in astable mode with R
A
= 4K,R
B
= 4K and
C = 0.01F.Determine the frequency of the output and duty cycle.







82

























83

MARKS ALLOCATION
Details
Marks
Allotted
Marks
Awarded
Preparation 20
Conducting 20
Calculation / Graphs 15
Results 5
Basic understanding (Core
competency learned)
15
Viva 10
Record 15
Total 100

Repetition less 25% of the total marks awarded as above.




Signature of faculty












84


Fig. (i).INTERNAL BLOCK DIAGRAM OF 555 TIMER




Fig. (ii).PIN DIAGRAM OF 555 TIMER




85



AIM:
To design and test a Monostable circuit using 555 timer

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity
1. CRO 30 MHz 1
2. Power Supply 15V, +5V 2
3. Timer IC555 1
4. Bread Board - 1
5. Resistors 10K 1
6. Capacitors 0.01uF, 0.1uF 1,2
7. Diode IN4148 1


THEORY:
Monostable multivibrator has one stable state and other is a quasi stable state. The
circuit is useful for generating single output pulse of adjustable time duration in response
to a triggering signal. The width of the output pulse depends only on external
components, resistor and a capacitor.The stable state is output low and quasi stable state
is the output high. In the stable state, transistor Q
1
(Refer internal circuitry of 555) is ON
and capacitor C is shorted out to ground. However upon application of a negative trigger
pulse to pin 2, Q
1
is turned off, which release the short circuit, across the external
capacitor C and drives the output high. The capacitor C now starts charging up towards
V
cc
through R
A
. How ever when the voltage across C equals 2/3 V
cc
, the upper
comparator UC (Refer internal circuitry of 555) output switches from low to high, which
inturn drives the output to its low state via the out put of the flip - flop. At the same time,



EX. NO: 8b

MONOSTABLE MULTIVIBRATOR USING 555
DATE:
86




Fig.(iii) MONOSTABLE MULTIVIBRATOR USING 555 TIMER







Fig (iv): WAVE FORMS



87

the output of the flip flop turns Q
1
is

ON and hence C rapidly discharges through the
transistor. The output of the monoshot remains low until a trigger is again applied. Then
the cycle repeats. The pulse width of the trigger input must be smaller than the expected
pulse width of the output. The trigger pulse must be a negative going pulse with
amplitude larger than
3
1
V
cc
. The width of the monoshot pulse is given by
T = 1.1 R
A
C (1)

DESIGN:

A monoshot using 555 timer and IC74121 to give a pulse width (quaisistable-state)
of duration 100sec.
Choose C = 0.01F
R = 0.69RC
Take R = 15K
T = 1.1 R
A
C
R
A
= 10K
T = 0.69 RC
100 x 10
-6
= 1.1 x 0.01x10
-6
xR
A
R
A
=
01 . 0 1 . 1
100
x
=9.09K
R
A
10K

PROCEDURE:
1. Rig-up the monostable multivibrator circuit using 555 timer as shown in fig.(iii) with
the designed value of the components.
2. Connect the CRO probes to display the trigger pulse and the monoshot output
pulse. Select suitable voltage sensitivity and time base of the CRO
3. Check for the correct polarity of supply voltages to circuit, and switch on the
power supply to the circuit.
4. Observe the wave forms and draw them on a graph sheet to scale. Measure the
outputpulse width and compare with the designed value.
5. Observe the waveforms across the timing capacitor along with the trigger pulse
and draw to scale and compare with the theoretical wave form of fig (iv).


88


Table 1: MONOSTABLE MULTIVIBRATOR

S.No Input
Square
Output
Capacitor
output
1.
Amplitude
( No. of div x Volts per div )

2.
Time period
( No. of div x Time per div )








Fig.(v) MONOSTABLE MULTIVIBRATOR USING IC555 IN MULTISIM







89

PROCEDURE FOR MULTISIM:
1. Construct the circuit shown above using Multisim software.
2. Connect the Astable output as input to Monostable.
3. Connect the oscilloscope shown in the diagram
4. Run the circuit and double click the connected oscilloscope
5. Measure the time period and amplitude values
6. Check the input and square wave output values .

PRELAB QUESTIONS:
1. Tell about trigger and Reset of 555 timer.
2. What are the applications of monostable multivibrator?
3. Write the expression for time delay of a monostable multivibrator.
4. Give the methods for obtaining symmetrical square wave.
5. What are the modes of operation of a timer?
6. The 555 timer has a DIL layout.What does DIL mean?

RESULT:



CORE - COMPETENCY LEARNED:



POSTLAB QUESTIONS:
1. With 555 monostable circuit,if t
p
> 2T, ------------ operation is obtained.
2. How can the circuit be triggered to produce an output pulse?
3. How is the duration or period of the output pulse determined?
4. What is necessity of pin5 capacitor in monostable multivibrator circuit?


90

























91



MARKS ALLOCATION
Details
Marks
Allotted
Marks
Awarded
Preparation 20
Conducting 20
Calculation / Graphs 15
Results 5
Basic understanding (Core
competency learned)
15
Viva 10
Record 15
Total 100

Repetition less 25% of the total marks awarded as above.



Signature of faculty















92




Fig.(i) BLOCK DIAGRAM OF IC 565 PLL

Fig ( ii ): PHASE LOCKED LOOP USING IC 565


93

Fig (iii): CHARACTERISTICS OF PLL USING IC 565

AIM:
To measure the capture range and lock-in-range of the PLL 565
APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1. Signal Generator 3 MHz 1
2. CRO 30 MHz 1
3. Power Supply 0 30 V 1
4. PLL 565 1
5. Bread Board - 1
6. Resistors 5.6K,10K Each one
7. Capacitors 0.1uf, 0.01uf Each one
THEORY:
The basic block diagram of the phase locked loop(PLL) is shown in Figure (i).
The feed-back system consists of (i)phase detector/comparator,(ii)A low-pass filter
(iii)An error amplifier and (iv)A voltage controlled oscillator (VCO).
A phase detector compares two input signals and produces an error signal which
is proportional to their phase difference. The error signal is then low-pass filtered and
used to drive a VCO which creates an output phase. The output is fed through an optional
divider back to the input of the system, producing a negative feedback loop. If the output
phase drifts, the error signal will increase, driving the VCO phase in the opposite
direction so as to reduce the error. Thus the output phase is locked to the phase at the
other input. This input is called the reference.
The oscillator generates a periodic output signal. Assume that initially the
oscillator is at nearly the same frequency as the reference signal. If the phase from the
oscillator falls behind that of the reference, the phase detector changes the control voltage
of the oscillator so that it speeds up. Likewise, if the phase creeps ahead of the reference,
the phase detector changes the control voltage to slow down the oscillator.
Ex. No: 9

PHASE LOCKED LOOP
DATE:
94
































95

Since initially the oscillator may be far from the reference frequency, practical
phase detectors may also respond to frequency differences, so as to increase the lock-in
range of allowable inputs.
The low pass filter helps in establishing the dynamic characteristics of the PLL
circuit. The signal at V
c
shifts the VCO frequency in a direction to reduce the frequency
difference between f
in
and f
o.
. Once this action starts, the PLL is said to be in the capture
range. The VCO continues to change its frequency till its output frequency is exactly the
same as the input signal frequency. The PLL is then said to be locked. Once the PLL is
locked there will be a finite phase difference between the input and the output signals.
The phase difference is necessary to generate a corrective control voltage V
c
to shift the
VCO frequency from f
o
to f
in
and then to maintain the lock. In locked state the PLL tracks
frequency changes of the input signal. Thus the PLL goes through three stages are
(i) Free-running (ii) Capture and (iii) phase-lock.
LOCK IN RANGE:
The range of frequencies over which the PLL can maintain lock with the
incoming signal is called the lock in range
CAPTURE RANGE:
The range of frequencies over which the PLL can acquire lock with an input
signal is called the capture range. It is expressed as a percentage of f
o
.
PULL-IN-TIME:
The total time taken by the PLL to establish the lock is called pull-in-time. This
depends on the initial phase and frequency difference between the two signals as well as
on the overall loop gain and the bandwidth of the low pass filter.

DESIGN:
Let f
0
= 5f
in

And f
in
= 1.5 to 2.2 kHz
Centre frequency f
in
= (1.5+2.2)/2 =1.85 kHz
Therefore f
0
= 5 X 1.85 = 9.25 kHz
f
0
= 0.25/(R
t
C
t
)
Choosing C
t
= 0.05uf, R
t
=5.6k


96

Table (1):

Obtained Frequencies

Capture range
(f
c
)

Lock in range
(f
L
)
f
1
(KHz) f
2
(KHz) f
3
(KHz) f
4
(KHz) Theoretical
value
Practical
value
Theoretical
value
Practical
value





















97

CALCULATION:
The Lock in range f
L
= f
2
f
4
The theoretical value of the lock in range is given by
f
L
= 8f
0
/ V
Where V= +V
cc
(- V
cc
)
The capture range f
C
= f
3
f
1
The Theoretical Value of the Capture Range is given by
f
C
= {f
L
/ (2x 3.6x10
3
C
2
)}
1/2
Where C
2 is
the filter capacitor in farads.

PROCEDURE:
1. Calculate the values of timing capacitor and resistor, for the PLLs free-
running frequency of 25 KHz using the following equations.

fo = 0.25/R
f
C
t


Choose C
t
= 0.001F
R
f
= 0.25/ (25x10
3
x0.001x10
-6
)
= 10K
2. Rig-up the PLL circuit as shown in Figure(ii) with the designed value of the
R
t
and C
t
Connect a capacitor is C
1
= 0.001F between pins 7 and 8 of the
PLL to eliminate possible oscillations. The filter capacitor is C
2
=1F, it must
be large enough to stabilize the VCO frequency.
3. Connect the CRO probe to Pin(4), to measure the free-running frequency of
VCO.
4. Set the voltage sensitivity and time base on the CRO.
5. Check for the correct polarity of supply voltages to PLL and switch on the
power supply.
6. Set the input signal to PLL at zero, and measure the free running frequency.
Compare it with the calculated value. Measure the demodulated output
voltages at Pin 7.

98































99

7. Apply an input signal of 1
V
peak to peak square wave at a frequency of 1KH
Z

to pin 2 and display this signal on one channel of the CRO.
8. Gradually increase the input signal frequency, till the PLL is locked, to the
input frequency. This frequency f
1,
gives the lower end of the capture range.
Note down f
1
and

measure the demodulated output voltage at pin 7.
9. Further continue to increase the input signal frequency, till the PLL tracks the
input signal up to a frequency f
2
. This frequency f
2
gives the upper end of the
lock in range. If the input frequency is increased further, the PLL will get
unlocked. Note down f
2,
and measure the demodulated output voltage at pin 7.
10. Now gradually decrease the input frequency till the PLL is again locked. This
frequency f
3
.is the upper end of the capture range. Note the frequency f
3,
and
measure the demodulated output voltage at pin 7 and note it down.
11. Further decrease the input frequency until the PLL is unlocked. This
frequency f
4
. is the lower end of the lock-in-range. Note down f
4
. Measure the
demodulated output voltage at pin 7.
12. Tabulate the readings and Draw the control voltage versus frequency curve.

PRELAB QUESTIONS:
1. What is PLL?
2. What is the major difference between digital and analog PLL?
3. List the basic building blocks of PLL?
4. Define lock-in and capture range of PLL?
5. What are the applications of PLL?
6. List out the filters are used in PLL.
RESULT:


CORE - COMPETENCY LEARNED:



100
































101

POSTLAB QUESTIONS:
1. Define pull in time?
2. What is the range of modulating input voltage applied to a VCO?
3. What are the advantages of PLL AM detector compared to conventional AM
detector?
4. Which is greater Capture range or Lock range?
5. A PLL has free-running frequency Wc=500KHz. Bandwidth of
LPF=10KHz,suppose an input signal of frequency 600KHz.Will the loop acquire
lock? What is VCO output frequency?
MARKS ALLOCATION
Details
Marks
Allotted
Marks
Awarded
Preparation 20
Conducting 20
Calculation / Graphs 15
Resu lts 5
Basic understanding (Core
competency learned)
15
Viva 10
Record 15
Total 100

Repetition less 25% of the total marks awarded as above.






Signature of faculty



102



Fig.(i) Block diagram of frequency multiplier



Fig.(ii) CIRCUIT DIAGRAM FOR FREQUENCY MULTIPLIER USING PLL




103



EX. NO: 10
FREQUENCY MULTIPLIER USING PLL

DATE:

AIM:
To construct and test the frequency multiplier using PLL 565

APPARATUS REQUIRED:

S.NO APPARATUS NAME RANGE QUANTITY
1. RPS (0-30) Volts 2
2. Signal generator 1MHz 1
3. CRO 20MHz 1
4. Resistors 20KO,2KO,4.7KO,10KO Each Two
5. PLL COUNTER IC565,IC7490 1
6. Capacitors 0.01F, 0.001F, 10F 1
7. TRANSISTOR 2N2222 1

THEORY:

The basic block diagram of frequency multilier as shown fig(i). In the frequency
multiplier using PLL565, a divided by N network is inserted between the VCO output
and the phase comparator input. Since the output of the comparator is locked to the input
frequen incy f
in
, the VCO is running at a multiple of the input frequency. Therefore in the
locked state the VCO output frequency f
o
is given by,

By selecting proper divider by N network, we can obtain desired multiplication. For
example, to obtain output frequency fo = 6 fi, a divide by N should be equal to 6.LM565
IC used as a frequency multiplier circuit. It is configured as a divide by 10 circuit.Pin
diagram is as shown in fig.(iii).

104


Fig.(iii) PIN DIAGRAM

TABLE (1):
V
in
=
f
in
(Hz) f
o
(Hz) Multiple Factor
Designed Obtained


Fig.(iv) MODEL WAVEFORM

105

PROCEDURE:
1. Rig up the circuit of frequency multiplier
2. Connect the signal generator output to the input terminal of PLL
3. Connect the CRO probes to display the input and output signals
4. Set the input signal at 1Vpp square wave at 1KHz
5. Vary the VCO frequency by adjusting the 20KO potentiometer till the PLL is
locked
6. Measure the output frequency, it should be 5 times that of the input frequency
7. Repeat the steps for different range of frequencies

PRELAB QUESTIONS:
1. List the basic building blocks of a PLL.
2. Define Capture range.
3. Define lock range.
4. Define pull in time.
5. Which is greater Capture range or pull in time?

RESULT:




CORE - COMPETENCY LEARNED:







106
































107


POSTLAB QUESTIONS:

1. What is the major difference between digital and analog PLLs?
2. List the application of PLL.
3. What is the range of modulating input voltage applied to a VCC?
4. What is meant by VCO? What is the need of it in PLL?
5. Why the low pass filter circuit is need in the PLL?
MARKS ALLOCATION
Details
Marks
Allotted
Marks
Awarded
Preparation 20
Conducting 20
Calculation / Graphs 15
Results 5
Basic understanding (Core
competency learned)
15
Viva 10
Record 15
Total 100

Repetition less 25% of the total marks awarded as above.



Signature of faculty







108















































109



AIM:
To design and test the 5V, 100mA regulated power supply with current fold back
using 723 general purpose voltage regulators.

APPARATUS REQUIRED:
S.No Apparatus required Range
Quantity

1 General Purpose Regulator IC 723 1
2 Resistor 1K, 2.2K, 2.7K, 5.6K, 33ohm Each one
3 Capacitors 0.1uF, 1uF Each One
4 Ammeter 0-100mA 1
5 Voltmeter (0-10V) & (0-2V) Each One
6 RPS (0-30V) 1
7 Bread Board - 1


THEORY:
The unregulated power supply has two undesirable characteristics (i) the d.c
voltage decreases and (ii) the a.c ripple voltage increases as load current increases. Both
these disadvantages can be minimized by using a voltage regulator. The resulting power
supply is called as a voltage regulated supply. The voltage regulators are classified as

i) Series Regulator
ii) Shunt Regulator
iii) Switch Regulator

EX. NO:11
VOLTAGE REGULATOR POWER SUPPLY
DATE:
110


Fig (i): VOLTAGE REGULATED POWER SUPPLY USING IC 723




Fig (ii): Fold back charactertics








111

723 GENERAL PURPOSE REGULATORS:

The three terminal regulators 78XX / 79XX series have the following limitations
(i) No short circuit protection and (ii) The output voltage is fixed. These limitations have
been over come in 723 voltage regulator. The IC is inherently a low current device but
can be boosted to provide more current by connecting external pass transistor. The
limitation of 723 is that it has no built in thermal protection and has no short circuit
current limits. It can be used either as a linear regulator or as a switching regulator.

The functional block diagram of 723 voltage regulator is as shown in fig (i). It has
two separate sections. The zener diode, a constant current source and reference amplifier
produce a fixed voltage of about 7.1V at the terminal V
ref.
The IC 723 is provided with
current fold back facility to limit the load current and short circuit current respectively.

The characteristics curve of a current limited power supply is shown in fig. 2.The
ratio of rated load current and the short circuit current can be adjusted by selecting proper
value of k.Typically k is selected to produce a maximum load current of 2 to 3 times the
short circuit load current. The output voltage remains constant for load current below
limit. As current approaches the limit the output voltage drops. The current limit is set by
connecting an external resistor R
sc
between the terminal C
1
and C
s
.As current demand
increases, the output is held constant, till a present level (I
Knee
) is reached. If current
demand exceeds this level, both the output voltage and current decreases and therefore
the short circuit current are limited..







112


Fig. (iii) PIN DIAGRAM


Table (1): VOLTAGE REGULATED POWER SUPPLY USING IC 723

V
sense
=
Current Foldback
I
l
(mA) V
1
(V)

113

DESIGN:
For the given values of V
0
, R
3
and R
4
the knee current depends on the current
sense resistor R
sc
. The knee current is given by,

4
4 3
4
3
) (
R R
R R V
R R
R V
I
sc
sense
sc
o
knee
+
+ =
(1)
The short circuit current is given by,
4
4 3
) (
R R
R R
R
V
Isc
sc sc
sense
+
=
(2)
Calculate the values of
knee
I & Isc using equation 1 & 2 and compare with the
measured values.

PROCEDURE:
i) Rig up the 5V, regulated supply circuit using LM 723 as shown in Fig (i).
ii) Connect the variable dc supply to circuit.
iii) Keeping the load rheostat for maximum resistance, switch ON the variable
dc supply and adjust to 10V.
iv) Note down the ammeter and voltmeter readings. Increase the load current
at suitable step up to a maximum of 100mA and note down the values of I
1

and V
1
in table 1.
v) Further decrease in load resistance would cause a decrease in current as
well as voltage. Note down the meter readings until the voltage is
approximately zero.
vi) Keep the load current constant at a value, vary the input dc voltage from
9V to 25V, at suitable steps, note that the output voltageV
0
and load
current I
L
remain constant. Tabulate the readings in table (i). Switch off
the power supply.
vii) Plot the current fold back characteristics output voltage versus load
current. Mark the knee current and short circuit current on the graph.



114
































115

PRELAB QUESTIONS:
1. Define voltage regulators?
2. What are the types of voltage regulators?
3. Distinguish between unregulated and regulated dc power supplies?
4. What do you mean by ripple in power supplies?
5. What is a voltage reference? Why is it needed?
RESULT:



CORE - COMPETENCY LEARNED:



POSTLAB QUESTIONS:
1. How can you select the values of k.
2. What to you understood by foldback charactertics
3. Draw the basic diagram for three terminal regulators?
4. What is the advantage of current fold back over current limit protection?
5. The expression for load regulation is -------------.








116

























117


MARKS ALLOCATION
Details
Marks
Allotted
Marks
Awarded
Preparation 20
Conducting 20
Calculation / Graphs 15
Results 5
Basic understanding (Core
competency learned)
15
Viva 10
Record 15
Total 100

Repetition less 25% of the total marks awarded as above.



Signature of faculty


















118






Fig.(i) BLOCK DIAGRAM FOR SMPS



Fig.(ii) PIN DIAGRAM

119

EX. NO: 12
SWITCHED MODE POWER SUPPLY
DATE:

AIM:
To study switched mode power supply.


GENERAL DESCRIPTION:

The LM1524 series of regulating pulse width modulation contains all the control
circuitry ,necessary to important switching regulators of either polarity, transformer
coupled AC to DC converters ,transformer polarity connectors .This device includes a 5
volt voltage regulator capable of supplying up to 50mA to internal circuitry..It consists of
control amp, an oscillator, a pulse width modulator, a phase splitting flip flop and
shutdown circuit. The regulator output is limited and to limit the junction temperature an
internal thermal shutdown.. The LM1524 is rated for operation from -55C to 125 C and
is packaged in a hermeteric is lead output.


THEORY:
A switched-mode power supply (switching-mode power supply, SMPS, or
switcher) is an electronic power supply that incorporates a switching regulator to convert
electrical power efficiently. Like other power supplies, an SMPS transfers power from a
source, like mains power, to a load, such as a personal computer, while converting
voltage and current characteristics. An SMPS is usually employed to efficiently provide a
regulated output voltage, typically at a level different from the input voltage.
Unlike a linear power supply, the pass transistor of a switching-mode supply continually
switches between low-dissipation, full-on and full-off states, and spends very little time
in the high dissipation transitions (which minimizes wasted energy). Ideally, a switched-
mode power supply dissipates no power. Voltage regulation is achieved by varying the
ratio of on-to-off time. In contrast, a linear power supply regulates the output voltage by
continually dissipating power in the pass transistor. This higher power conversion
120


Fig.(iv) MODEL AC, HALF-WAVE AND FULL-WAVE RECTIFIED SIGNALS







121

efficiency is an important advantage of a switched-mode power supply. Switched-mode
power supplies may also be substantially smaller and lighter than a linear supply due to
the smaller transformer size and weight.
Switching regulators are used as replacements for the linear regulators when higher
efficiency, smaller size or lighter weight are required. They are, however, more
complicated, their switching currents can cause electrical noise problems if not carefully
suppressed, and simple designs may have a poor power factor.
The main advantage of this method is greater efficiency because the switching transistor
dissipates little power when it is outside of its active region (i.e., when the transistor acts
like a switch and either has a negligible voltage drop across it or a negligible current
through it). Other advantages include smaller size and lighter weight (from the
elimination of low frequency transformers which have a high weight) and lower heat
generation due to higher efficiency. Disadvantages include greater complexity, the
generation of high-amplitude, high-frequency energy that the low-pass filter must block
to avoid electromagnetic interference (EMI), a ripple voltage at the switching frequency
and the harmonic frequencies thereof.
Very low cost SMPSs may couple electrical switching noise back onto the mains power
line, causing interference with A/V equipment connected to the same phase. Non-power-
factor-corrected SMPSs also cause harmonic distortion
FEATURES:

Complex PWM power control circuitry frequency adjustable to greater than 100
KHz,2%frequency stability with temperature. Total quiescent current less than
10mA.Dual alternating o/p switches for the both push pull or single ended operation on
chip protection against excessive junction temperature and the output current 5v,50mA
linear regulator output available to use.




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123

ABSOLUTE MAXIMUM RATINGS:

Input voltage=40v, Reference voltage =6v, Reference o/p current=50Ma
Output current=100mA,Oscillator charge current= 5mA
Internal power range = LM1524-55C to 125C, LM2524 and 35240C to 70C
Maximum junction temperature = J package 15 C , N package 120C
Storage temperature range = 65C to 150


FUNCTIONAL DISCRIPTION:

INTERNAL VOLTAGE REGULATOR:

The LM3525 has a chip, 5v and 50mA short circuit protection voltage regulator,
This voltage regulator provides the supply for all the internal circuitry of the device and
can be used to as an external reference. For input voltage of less than 8v to 150v, output
should be shorted the input voltage must there to pin15.V
in
which disable the 5v regulator
with there pins shorted the input voltage must 6-8 v is to be used.
OSCILLATOR:
The oscillator its frequency is split by an external resistor R
T
and capacitor C
T
.
The oscillators output provides the signals for triggering internal flipflop,which direct
the PWM information to output and a blanking pulse to turn off both output during the
transistors to ensure that cross conduction does not occur. The width of the blanking
pulse or dead time is controlled by value of C
T.
ERROR AMPLIFER:
The error amplifier is a differential input amplifier. Its gain is normally 80 dB, is
set by either feedback or output loading. This output loading can be done with either
purely resistor or combination of resistive and reactive components. The output of the
amplifier or input to the PWM can be overridden easily. As its output impedance is very
high. For this reason DC voltage can be applied to pin9 .




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CURRENT LIMITING:
The function of current limit amplifier is to override the error amplifier output and
takes the control of first pulse switch. The output duty cycle drops to about 25%.when the
current limit sense voltage of 200mV is applied between the positive C
L
and negative C
L
terminals.
OUTPUT STAGES:
The output of SMPS are PNP transistor it is capable of maximum current of
100mA.There transistor are drawn 180 out of phase .

RESULT:


CORE - COMPETENCY LEARNED:


MARKS ALLOCATION

Details Marks Allotted Marks
Awarded
Preparation 20
Conducting 20
Calculation / Graphs 15
Results 5
Basic understanding (Core
competency learned)
15

Viva 10
Record 15
Total 100

Repetition less 25% of the total marks awarded as above.


Signature of faculty