Mission

Hardware Reference Manual for Mission
10x-Unified Learning Kit

R3.0

iWave Systems Technologies Pvt. Ltd. Page 1 of 119
(Confidential)

iW-EMDBY-UM-01-R2.0-REL3.0-RMHW
12
th
Feb 11

Authors Rahul Karkera

APPROVAL

Name Function Organisation Date Signature
Mr. Sebikumar
Kuruvilla
Wipro
Mr. Bhagavath Project Manager iWave Systems
Technologies Pvt. Ltd.

Distribution iWave Systems Technologies Pvt. Ltd

Contact Info

Name Telephone e-mail
iWave Systems Tech. Pvt. Ltd.
7/B, 29
th
Main,
BTM Layout, 2
nd
Stage,
Bangalore 560 076, India.
+91-80-2668-3700
+91-80-2678-1643
emdby@iwavesystems.com

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DOCUMENT IDENTIFICATION
Project Name iW-EMDBY
Document Name iW-EMDBY-UM-01-R2.0-REL3.0-RMHW
Document Home iWave Server
Release No 3.0
Status Engineering version
Audience Wipro

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DOCUMENT REVISION HISTORY

Release Date Change Description Author
1.0 10
th
July. 10 Initial Draft version Rahul Karkera
2.0 10
th
Dec. 10 Updated version
The following tables are updated with FPGA pin-
out details:
Table 22 to Table 29,
Table 41 to Table 44,
Table 47 & Table 51.
Rahul Karkera
3.0 12
th
Feb. 11 Engineering Version Rahul Karkera
PROPRIETARY NOTICE: This document contains proprietary material for the sole use of the
intended recipient(s). Do not read this document further if you are not the intended recipient.
Any review, use, distribution or disclosure by others is strictly prohibited. If you are not the
intended recipient (or authorized to receive for the recipient), you are hereby notified that any
disclosure, copy or distribution or use of any of the information contained within this document
is STRICTLY PROHIBITED. Thank you. iWave Systems Tech. Pvt. Ltd.

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Table of Contents
1. Introduction ......................................................................................................11
1.1 Purpose ........................................................................................................................... 11
1.2 About Unified Learning Kit ............................................................................................. 11
1.3 Acronyms and Abbreviations........................................................................................... 11
2. Functional Description ......................................................................................14
2.1 Board Architecture .......................................................................................................... 14
2.1.1 Board Features .......................................................................................................... 15
2.2 ULK Board ...................................................................................................................... 17
2.2.1 TOP VIEW ............................................................................................................... 17
2.2.2 BOTTOM VIEW ...................................................................................................... 18
3. Processor Interface ............................................................................................19
3.1 NAND Flash interface ..................................................................................................... 19
3.2 Mobile DDR interface ..................................................................................................... 20
3.3 3.5inch LCD interface ..................................................................................................... 22
3.4 Touch panel interface ...................................................................................................... 25
3.5 Audio interface ................................................................................................................ 26
3.6 Ethernet controller interface............................................................................................. 28
3.7 RS232 interface ............................................................................................................... 30
3.8 RTC interface .................................................................................................................. 31
3.9 USB2.0 Host interface ..................................................................................................... 32
3.10 USB2.0 OTG interface .................................................................................................. 34
3.11 VGA interface ............................................................................................................... 36
3.12 I2C EEPROM interface ................................................................................................. 38
3.13 FPGA interface .............................................................................................................. 38
3.14 JTAG interface .............................................................................................................. 40
3.15 MMC/SD1 interface ...................................................................................................... 42
3.16 SD2 interface ................................................................................................................. 43
3.17 Character LCD interface ................................................................................................ 46
3.18 TV out interface............................................................................................................. 48
4. FPGA interface .................................................................................................50
4.1 DDR2 SDRAM interface ................................................................................................. 50
4.2 Ethernet PHY interface .................................................................................................... 53
4.3 Serial configuration PROM interface ............................................................................... 56
4.4 RS232 interface ............................................................................................................... 57
4.5 Charater LCD interface.................................................................................................... 59
4.6 ADC interface ................................................................................................................. 61
4.7 DAC interface ................................................................................................................. 63
4.8 7 Segment LED interface ................................................................................................. 65
4.9 I2C EEPROM interface ................................................................................................... 66

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4.10 JTAG interface .............................................................................................................. 68
5. External Interfaces ............................................................................................70
5.1 Processor Keypad interface.............................................................................................. 70
5.2 I/O expansion connector .................................................................................................. 73
5.3 Simple digital interface .................................................................................................... 76
5.4 Control sensor interface ................................................................................................... 79
5.5 Bluetooth or Modem interface ......................................................................................... 81
5.6 External LCD interface .................................................................................................... 83
5.7 Camera interface ............................................................................................................. 86
5.8 I2C GPS interface ............................................................................................................ 88
5.9 IrDA interface ................................................................................................................. 90
5.10 FPGA Keypad interface ................................................................................................. 91
5.11 FPGA I/O connectors interface ...................................................................................... 94
5.11.1 20-Pin FPGA IO header .......................................................................................... 94
5.11.2 38-pin Mictor Connector ......................................................................................... 97
5.11.3 70-Pin Expansion connector .................................................................................... 99
6. Operation & Maintenance Features ................................................................. 103
6.1 Power & Reset LEDs ................................................................................................... 103
6.2 LEDs for OMAP3530 .................................................................................................. 103
6.3 LEDs for FPGA ........................................................................................................... 105
6.4 Major Test points........................................................................................................... 106
7. Switches & Jumpers ........................................................................................ 108
7.1 Reset Switch .................................................................................................................. 108
7.2 Toggle Switches ............................................................................................................ 110
7.2.1 Mode switch ........................................................................................................... 110
7.2.2 Power Switch .......................................................................................................... 110
7.3 DIP Switches ................................................................................................................. 111
7.3.1 System information for OMAP processor ............................................................... 111
7.3.2 Boot Configuration for OMAP processor ................................................................ 112
7.3.3 System information for FPGA ................................................................................ 113
7.4 Push button switches for OMAP processor & FPGA ..................................................... 114
7.5 Jumpers for Processor UART ........................................................................................ 115
7.6 Jumper for USB OTG .................................................................................................... 116
8. Dos & Donts................................................................................................. 117
9. Technical Support ........................................................................................... 119

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List of Figures

Figure 1: ULK board Architecture .............................................................................................. 14
Figure 2: ULK board Top View ................................................................................................. 17
Figure 3: ULK board Bottom View ............................................................................................ 18
Figure 4: OMAP3530 with NAND flash interface ...................................................................... 19
Figure 5: NAND Flash circuit schematic .................................................................................... 20
Figure 6: OMAP3530 interface with Mobile DDR ..................................................................... 21
Figure 7: Mobile DDR circuit schematic .................................................................................... 21
Figure 8: OMAP3530 interface with 3.5inch LCD ..................................................................... 22
Figure 9: 3.5inch LCD circuit schematic .................................................................................... 23
Figure 10: OMAP3530 interface withTouch panel ..................................................................... 25
Figure 11: Touch panel circuit schematic. .................................................................................. 25
Figure 12: OMAP3530 interface with Audio ............................................................................. 26
Figure 13: Headset & MIC in circuit schematic .......................................................................... 27
Figure 14: Speaker out circuit schematic .................................................................................... 27
Figure 15: OMAP3530 interface with Ethernet controller ........................................................... 29
Figure 16: Ethernet Controller circuit schematic ......................................................................... 29
Figure 17: OMAP3530 interface with RS232 interface ............................................................... 30
Figure 18: RS232 interface circuit schematic .............................................................................. 31
Figure 19: OMAP3530 interface with RTC interface .................................................................. 32
Figure 20: RTC interface circuit schematic................................................................................. 32
Figure 21: OMAP3530 Processor USB Host Interface ............................................................. 33
Figure 22: USB host circuit schematic ........................................................................................ 33
Figure 23: OMAP3530 interface with OTG transceiver .............................................................. 34
Figure 24: USB OTG circuit schematic ...................................................................................... 35
Figure 25: OMAP3530 interface with VGA ............................................................................... 36
Figure 26: VGA interface circuit schematic ................................................................................ 37
Figure 27: OMAP3530 interface with I2C EEPROM ................................................................. 38
Figure 28: I2C EEPROM circuit schematic. ............................................................................... 38
Figure 29: OMAP3530 interface with FPGA .............................................................................. 39
Figure 30: OMAP-FPGA interface circuit schematic .................................................................. 40
Figure 31: OMAP3530 interface with JTAG .............................................................................. 41
Figure 32: OMAP JTAG circuit schematic ................................................................................. 41
Figure 33: OMAP3530 interface with SD1 ................................................................................. 42
Figure 34: SD1 interface circuit schematic ................................................................................. 43
Figure 35: OMAP3530 interface with SD2 ................................................................................. 44
Figure 36: SD2 interface with transceiver circuit schematic ........................................................ 45
Figure 37: OMAP3530 interface with Character LCD ................................................................ 46
Figure 38: Character LCD circuit schematic ............................................................................... 47
Figure 39: OMAP interface with TV Out ................................................................................... 48

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Figure 40: TV Out circuit schematic ........................................................................................... 49
Figure 41: FPGA-DDR2 SDRAM interface ............................................................................... 50
Figure 42: FPGA DDR2 SDRAM circuit schematic ................................................................... 51
Figure 43: FPGA-Ethernet PHY interface .................................................................................. 53
Figure 44: FPGA Ethernet Phy Circuit Schematic ...................................................................... 55
Figure 45: FPGA-SPI PROM interface ....................................................................................... 57
Figure 46: FPGA SPI PROM circuit schematic .......................................................................... 57
Figure 47: FPGA-RS232 interface .............................................................................................. 58
Figure 48: FPGA-RS232 circuit schematic ................................................................................. 58
Figure 49: FPGA-Character LCD interface ................................................................................ 59
Figure 50: FPGA-Character LCD circuit schematic .................................................................... 60
Figure 51: FPGA-ADC interface ................................................................................................ 61
Figure 52: ADC circuit schematic .............................................................................................. 62
Figure 53: FPGA-DAC interface ................................................................................................ 63
Figure 54: DAC circuit schematic .............................................................................................. 64
Figure 55: FPGA-7segment LED interface ................................................................................. 65
Figure 56: 7 segment LED circuit schematic .............................................................................. 66
Figure 57: FPGA-I2C EEPROM interface .................................................................................. 67
Figure 58: FPGA-I2C EEPROM circuit schematic ..................................................................... 67
Figure 59: FPGA interface with JTAG ....................................................................................... 68
Figure 60: FPGA JTAG circuit schematic .................................................................................. 68
Figure 61: OMAP-FPGA JTAG interface through buffer circuit schematic ................................ 69
Figure 62: OMAP3530 interface with Keypad ............................................................................ 70
Figure 63: 6x6 Processor Keypad circuit schematic & layout ..................................................... 72
Figure 64: OMAP3530 interface with I/O expansion connector .................................................. 73
Figure 65: IO Expansion connector circuit schematic ................................................................. 74
Figure 66: OMAP3530 interface with Simple Digital Interface connector .................................. 76
Figure 67: Simple Digital Interface circuit schematic ................................................................. 78
Figure 68: OMAP3530 interface with Control Sensor header ..................................................... 79
Figure 69: Control Sensor Header circuit schematic ................................................................... 80
Figure 70: OMAP3530 interface with Bluetooth or Modem Interface ......................................... 81
Figure 71: Bluetooth or Modem interface circuit schematic ........................................................ 82
Figure 72: OMAP3530 interface with External LCD .................................................................. 83
Figure 73: External LCD circuit schematic ................................................................................. 84
Figure 74: OMAP3530 interface with Camera ............................................................................ 86
Figure 75: Camera Interface circuit schematic ............................................................................ 87
Figure 76: OMAP interface with GPS Header ............................................................................ 89
Figure 77: GPS header circuit schematic .................................................................................... 89
Figure 78: OMAP interface with IrDA Connector ...................................................................... 90
Figure 79: IrDA connector circuit schematic .............................................................................. 91
Figure 80: FPGA-Keypad interface ............................................................................................ 92
Figure 81: 4x4 FPGA Keypad circuit schematic ......................................................................... 93

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Figure 82: FPGA-I/O connectors interface ................................................................................ 94
Figure 83: 20-pin FPGA IO header circuit schematic ................................................................. 95
Figure 84: 38-pin Mictor connector circuit schematic ................................................................. 97
Figure 85: 70-pin FPGA Expansion connector circuit schematic ...............................................100
Figure 86: Power & Reset LEDs circuit schematic ...................................................................103
Figure 87: Processor LEDs circuit schematic ...........................................................................105
Figure 88: FPGA LEDs circuit schematic ................................................................................106
Figure 89: Manual Reset Circuit Schematic ...............................................................................108
Figure 90: Warm Reset Circuit Schematic .................................................................................109
Figure 91: Reset Buffer Circuit Schematic ................................................................................109
Figure 92: Mode Switch circuit schematic .................................................................................110
Figure 93: Power Switch Circuit Schematic ..............................................................................111
Figure 94: OMAP DIP Switch Circuit Schematic ......................................................................112
Figure 95: OMAP Boot Configuration Circuit Schematic ..........................................................113
Figure 96: FPGA DIP Switch Circuit Schematic .......................................................................114
Figure 97: Lab interrupt Circuit Schematic ................................................................................115
Figure 98: Push Button Switches Circuit Schematic ..................................................................115
Figure 99: UART Jumper setting Circuit Schematic ..................................................................116
Figure 100: USB OTG Jumper setting Circuit Schematic ..........................................................116

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List of Tables
Table 1: Acronyms & Abbreviations .......................................................................................... 11
Table 2: 3.5inch LCD connector ................................................................................................. 23
Table 3: 4 Pin Touch panel connector ......................................................................................... 26
Table 4: 3 Pin Stereo connector for MIC IN ............................................................................... 28
Table 5: 3 Pin Stereo connector for Headset OUT ...................................................................... 28
Table 6: 3 Pin Stereo connector for left speaker Out ................................................................... 28
Table 7: 3 Pin Stereo connector for right speaker Out ................................................................. 28
Table 8: RJ 45 connector Pin Description ................................................................................... 30
Table 9: DB-9 Male connector ................................................................................................... 31
Table 10: Type A connector Pin Description .............................................................................. 34
Table 11: Type mini AB connector Pin Description.................................................................... 35
Table 12: 15 Pin VGA connector................................................................................................ 37
Table 13: 14 Pin JTAG connector for Processor ......................................................................... 41
Table 14: SD1 Connector Pin Description .................................................................................. 43
Table 15: SD2 Connector Pin Description .................................................................................. 45
Table 16: 16 Pin Character LCD connector ................................................................................ 47
Table 17: TV out connector (RCA jack) ..................................................................................... 49
Table 18: FPGA pin-out details for DDR2 SDRAM interface .................................................... 51
Table 19: RJ 45 connector Pin Description ................................................................................. 55
Table 20: FPGA pin-out details for Ethernet interface ................................................................ 56
Table 21: FPGA pin-out details for SPI PROM interface ............................................................ 57
Table 22: DB-9 Male connector ................................................................................................. 58
Table 23: 16 Pin Character LCD connector ................................................................................ 60
Table 24: 3 Pin Stereo connector for ADC input......................................................................... 62
Table 25: FPGA pin-out details for ADC ................................................................................... 62
Table 26: 3 Pin Stereo connector for DAC output ....................................................................... 64
Table 27: FPGA pin-out details for DAC ................................................................................... 64
Table 28: FPGA pin-out details for 7 segment LED ................................................................... 66
Table 29: FPGA pin-out details for I2C EEPROM ..................................................................... 67
Table 30: 14 Pin JTAG connector for FPGA .............................................................................. 69
Table 31: 15 pin Keypad connector ............................................................................................ 72
Table 32: 28-pin I/O expansion connector .................................................................................. 75
Table 33: 25-pin Simple Digital Interface connector................................................................... 78
Table 34: 15-pin Control Sensor Header ..................................................................................... 80
Table 35: Bluetooth or Modem connector .................................................................................. 82
Table 36: External LCD connector1 ........................................................................................... 84
Table 37: External LCD connector2 ........................................................................................... 85
Table 38: Camera connector ....................................................................................................... 87
Table 39: 5 pin GPS header ........................................................................................................ 90
Table 40: 6 pin IrDA Header ...................................................................................................... 91

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Table 41: 12 pin FPGA Keypad connector ................................................................................. 93
Table 42: 20-Pin FPGA IO header .............................................................................................. 96
Table 43: 38-pin Mictor connector ............................................................................................. 97
Table 44: 70-pin FPGA Expansion connector ............................................................................101
Table 45: Power & Reset LEDs ...............................................................................................103
Table 46: LEDs for OMAP3530 ..............................................................................................104
Table 47: LEDs for FPGA .......................................................................................................105
Table 48: Test Points in ULK ....................................................................................................106
Table 49: OMAP DIP Switch details .........................................................................................111
Table 50: Boot Configuration DIP Switch details ......................................................................112
Table 51: FPGA DIP Switch details ..........................................................................................114

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1.Introduction
1.1 Purpose
The purpose of this document is to briefly describe the user interfaces & external interfaces of the
Unified Learning Kit.
1.2 About Unified Learning Kit
Unified Learning Kit is based on Texas Instruments OMAP3530 application processor & Spartan-
6 FPGA. The OMAP3530 processor supports interfaces such as Mobile DDR, Nand Flash, Audio
in & out, TV out, Touch screen LCD, VGA out, Ethernet, Keypad, USB OTG, 2 SD cards &
external interface connectors such as Control sensor header, I/O expansion connector, I2C Header
for GPS, Bluetooth & Modem Connector, Simple Digital interface connector, IrDA Connector,
Camera Connector & LCD connector.
The Spartan-6 FPGA supports interfaces such as DDR2 SDRAM, Ethernet, ADC, DAC, character
LCD & external interfaces such as 70-pin IO expansion connector & 20-pin IO header.
1.3 Acronyms and Abbreviations
Table 1: Acronyms & Abbreviations
Term Meaning
ADC Analog to Digital Convertor
ALC Automatic Level Control
ALE Address Latch Enable
ARM Advanced RISC Machine
ASIC Application Specific Integrated Circuit
BGA Ball Grid Array
CAS Column Address Strobe
CCD Charge Coupled Device
CE Chip Enable
CEA Consumer Electronics Association
CLE Command Latch Enable
CIR Consumer Infrared
CMOS Complementary Metal Oxide Semiconductor
CPLD Complex Programmable Logic Device
CTS Clear To Send
DAC Digital to Analog Converter
DDR2 SDRAM Dual Data Rate two Synchronous Dynamic RAM
DSP Digital Signal Processing
EDMA Enhanced Direct-Memory-Access
EEPROM Electrically Erasable Programmable Read Only Memory

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EMC Electro Magnetic Compatibility
EMI Electro Magnetic Interference
EPC Embedded Power Control
ESD Electro Static Discharge
FBGA Fine pitch Ball Grid Array
FPGA Field Programmable Gate Array
GPIO General Purpose Input Output
GPMC General Purpose Memory Controller
HD High Definition
HS High Speed
HTSSOP Heat sink Thin-Shrink Small Outline Package
IEEE Institute of Electrical & Electronics Engineers
I2C Inter-Integrated Circuit
I2S Inter Ic sound
IP Intellectual Property
IrDA Infrared Data Association
I/O Input Output
JTAG Joint Test Action Group
LAN Local Area Network
LDO Low Drop Out
LED Light Emitting Diode
LPDDR Low power Double Data Rate
LS Low Speed
MAC Media Access Controller
McBSP Multichannel Buffered Serial Port
McSPI Multichannel Serial Peripheral Interface
mDDR mobile Double Data Rate
MDIO Management Data Input Output
MII Media Independent Interface
MIPS Million Instructions Per Second
NC No Connect
NTSC National Television System Committee
OMAP Open Multimedia Application Platform
OTG On The Go
PAL Phase Alternating Line
PCB Printed Circuit Board
PGA Programmable Gain Amplifier
PHY Physical Transceiver
PLL Phase Locked Loop
PMIC Power Management Integrated Chip
POR Power On Reset

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PWM Pulse Width Modulator
QFN Quad Flat Nolead
RAM Random Access Memory
RCA Radio Corporation of America
RE Read Enable
RoHS Restriction of Hazardous Substances
RS Register Select
RTC Real Time Clock
RTO Real Time Out
RTS Request To Send
RXD Receive Data
SD Secure Digital
SDIO Secure Digital Input Output
SDRAM Synchronous Dynamic Random Access Memory
SIMD Single Instruction Multiple Data
SMD Surface Mount Device
SPI Serial Peripheral Interface
SRAM Static Randam Access Memory
TBD To Be Decided
TDM Time Division Multiplexing
TI Texas Instruments
TQFP Thin Quad Flat Package
TSOP Thin Small Outline Package
TSSOP Thin-Shrink Small Outline Package
TXD Transmit data
UART Universal Asynchronous Receiver Transmitter
USB Universal Serial Bus
ULK Unified Learning Kit
ULPI UTMI+Low Pin Interface
UTMI USB2.0 Transceiver Macrocell Interface
VFBGA Very Fine Pitch Ball Grid Array
VGA Video Graphics Array
WE Write Enable
# or n Active low signal

Note: Before using the ULK board, please refer to the Dos & Donts section.

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2. Functional Description
2.1 Board Architecture
The Block level architecture of the Mission 10x-unified learning kit is shown in Figure 1.

iWave Systems Technologies
TI OMAP
3530
Spartan 6
FPGA
Expansion
conn(28pins)
FPGA
Expansion
Conn
Video
DAC
UART
Trans(x2)
PROM
JTAG
LEDs /
Switch
ADC
DAC
16x2
Char LCD
Mission 10x-unified learning kit
DDR2
SDRAM
(64MB)
UART
Transceiver
NAND Flash
(128MB)
Mobile
DDR (128MB)
RJ45 with
Magnetics
MAC & PHY
(Ethernet)
EEPROM
(256Kb)
I2C to I/O
Expander
Power regulators,
Clock
& reset circuit
PMIC (TPS65930)
(USB OTG Tx/Rx, Keypad, RTC, Audio)
16x2
Char LCD
Ethernet
PHY
RJ45 with
Magnetics
7 segment
LEDs (x4)
Oscillators
10&100MHz
Keypad
Conn(4x4)
HSUSB2
RTC
I2C1 I2C4 HSUSB0 McBsp2
SDRAMC
GPMC
MMC1
External
Transceiver
MMC2
DSS[24:0]
Touch
controller
McSPI1
Bluetooth &
Modem Conn
CAM[7:0], I2C2
UART1 &3
UART2, McBSP1,I2C2
I2C2
McSPI3,CS _PWM(x4)
Simple digital IF
(DB25 conn-5V)
MMC3
UART3
Mictor conn
(38 pins)
USB Host
ULPI Phy
USB Type A
Conn
SD2 (X4bit)
Conn
VGA
Conn
LCD conn
(2x20=40 pins)
4pin header
Camera conn
(34pins)
DB-9
Conn
IrDA
conn
SD1 (x4bit)
conn
I2C header
(GPS)
UART2, McBSP1,I2C2, MMC2
USB mini -AB
Conn
Speaker
Battery
Conn
Headset
Out
Class-D
Amp
Keypad
IF (6x6)
Level Tx-5V
Control sensor
Header
PWM, Mc SPI3/BSP1,I2C3
Level Tx-5V
I2C3
Stereo
Audio Jacksx2
Stereo
Audio Jacksx2
FPGA HDR2
20 pin Header
Level Tx-5V
DB-9
conn
Major components related to processor
External Connectors
Major components related to FPGA
MMC3,UART2,BSP1
UART1 as GPIOs
Video out
CVBS (RCA)
Level Tx-5V
USB OTG
DSS[17:0]
I2C3
Level Tx-3V
XDS510
JTAG
Mic
3.5 inch
LCD Conn
Level Tx-3V
DSS[24:0]
Level Tx
3V
LEDs /
Switch
Level Tx-3V

Figure 1: ULK board Architecture

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2.1.1 Board Features
The ULK board supports the following features

OMAP 3530 Processor
- TIs OMAP3530 application processor with CUS package
- TIs TPS65930 Power management IC
- NAND Flash Memory of 128Mbytes
- Mobile DDR SDRAM of 128Mbytes
- Ethernet controller with 10/100Mbps PHY and RJ45 LAN connector
- USB2.0 OTG interface
- 2no.s of SD interface
- RS232 Console using UART1&3
- Real Time Clock
- VGA
- CMOS sensor interface
- 24 bit RGB LCD interface
- Mic in and speaker out
- Touch panel controller through SPI interface
- 3.5inch LCD interface
- I2C EEPROM of 256Kbits
- IrDA support using UART3
- Bluetooth & modem connector (3.3V compatible)
- 16x2 Character LCD using I2C to I/O bus expander
- JTAG interface
- 6x6 Keypad interface (Using PMIC)
- Simple digital interface with 5V compatible
- Control sensor connector with 5v compatible
- I/O Expansion connector as same as beagle board through level translators (1.8 to
3.3V/5V) for 3.3V & 5V compatible
- One I2C,SPI & GPIO signals between processor and FPGA
- GPMC bus between processor and FPGA
- DIP switches & Status LEDs
- Reset device and manual reset button
- Single 5V Power Supply

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Spartan-6 FPGA
- Xilinxs XC6SLX25T FPGA
- SPI PROM from Atmel (2Mbyte)
- DDR2 SDRAM of 64Mbytes
- I2C EEPROM of 256Kbits
- 10/100Mbps ethernet PHY and RJ45 LAN connector
- UART transceiver
- 4x4 Keypad interface
- 16x2 chracter LCD through parallel interface
- 10bit ADC with parallel interface
- 12bit DAC with parallel interface
- JTAG interface
- 7 segment LEDs
- DIP switches & Status LEDs
- 20-pin header with 5V compatible
- 70-pin I/O expansion connector

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2.2 ULK Board
Figure 2 and Figure 3 shows the TOP view & BOTTOM view of ULK board respectively.
2.2.1 TOP VIEW
GPS HEADER
BLUETOOTH
CONN (3.3V)
SDI CONN
(5V)
USB OTG
CONN
RESET
SWITCH
5V
JACK
POWER ON/OFF
SWITCH
CONTROL
SENSOR
HEADER
SD2
CONN
IO EXP
CONN
16X2
CHAR LCD
PMIC
PROCESSOR
DB9 CONN
for FPGA
RIGHT
SPEAKER
LEFT
SPEAKER
FPGA
DDR2
SDRAM
NAND
FLASH
FPGA
IO
CONN (5V)
3.5 INCH
LCD
ADC
INPUT
MODE
SWITCH
FPGA
EXP
CONN
(3.3V)
EXTERNAL
LCD
CONN
CAMERA
CONN
VGA
CONN
7 SEGMENT
LEDs
EXTERNAL
TOUCH
CONN
RJ45 CONN
for FPGA
RJ45 CONN
for PROCESSOR
DAC
OUTPUT
DB9 CONN
for PROCESSOR
HEADSET
OUT
MIC
IN TV OUT
MDDR
DIP SWITCH for
PROCESSOR GPIOs
DIP SWITCH for
PROCESSOR BOOT
DIP SWITCH for
FPGA IOs

Figure 2: ULK board Top View

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2.2.2 BOTTOM VIEW

IRDA
CONN
SD1
CONN
6 X 6
KEYPAD
CONN
RTC
BATTERY

Figure 3: ULK board Bottom View

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3.Processor Interface
The following sections briefs out each of the interfaces connected to the OMAP3530 processor on
the ULK board.
3.1 NAND Flash interface
The 128Mbyte NAND flash (MT29F1G16ABCHC) from Micron is used to boot the OMAP3530
processor in 16-bit mode. It uses 16-bit bus to transfer data, addresses, and instructions. The five
command pins (CLE, ALE, CE#, WE#, RE#) used to implement the NAND flash command bus
interface protocol.
The OMAP3530 processor interface with NAND flash block diagram is shown in Figure 4 &
schematics is shown in Figure 5.
OMAP3530
WE#
NAND Flash
(128MB)
ALE
RE#
GPMC_ALE
CLE
GPMC_CLE
GPMC_CS0#
GPMC_WE#
GPMC_OE#
GPMC_WAIT
R/B#
CE#
IO[15:0] GPMC_D[15:0]
GPMC_WP#
WP#

Figure 4: OMAP3530 with NAND flash interface

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Figure 5: NAND Flash circuit schematic

3.2 Mobile DDR interface
The mobile DDR device will be configured through SDRAM controller subsystem of OMAP3530
processor. The 128 Mbyte mobile DDR (K4X1G323PD-8GC6) from Samsung will be operating
at 166MHz speed with CAS latency of 3. The device is configured in 32Mx32 organization with
13 row address (A0-A12) lines and 10 column address lines (A0-A9) and total bank of 4.
The OMAP3530 interface with Mobile DDR SDRAM is shown in Figure 6 & schematics is
shown in Figure 7.

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OMAP3530
Mobile DDR
(128MB)
CK
CS#
SDRC_CLK
CK# SDRC_CLK#
RAS# SDRC_RAS#
CAS# SDRC_CAS#
WE# SDRC_WE#
SDRC_CS0#
CKE
SDR_CKE0
SDRC_DM[3:0]
SDRC_DQS[3:0]
SDRC_BA[1:0]
SDRC_A[12:0]
SDRC_D[31:0]
DM[3:0]
BA[1:0]
A[12:0]
D[31:0]
DQS[3:0]

Figure 6: OMAP3530 interface with Mobile DDR

Figure 7: Mobile DDR circuit schematic

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3.3 3.5inch LCD interface
The 24bit RGB Out signals and LCD control signals of OMAP3530 processor is taken out to
interface with 3.5inch LCD. Since voltage levels of these signals are 1.8V, level translators are
used to convert the 1.8V level signals to 3.3V level signals. TFT QVGA LCD KWH035ST12-F02
from Formike is used.
The 3.5inch LCD interface is shown in Figure 8 & schematics is shown in Figure 9.
Table 2 lists the 3.5inch LCD connector pin details.
OMAP3530
3.5inch
LCD Conn
(54 pin)
DSS_HSYNC
DSS_PCLK
DSS_DE
DSS_VSYNC
Level Tx
3.3V
Level Tx
3.3V
DSS_D[15:0]
DSS_D[23:16]
DSS_HSYNC
DSS_PCLK
DSS_DE
DSS_VSYNC
DSS_D[15:0]
DSS_D[23:16]

Figure 8: OMAP3530 interface with 3.5inch LCD

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Figure 9: 3.5inch LCD circuit schematic
Table 2: 3.5inch LCD connector
Pin No. Signal Description
Voltage level
1 VBL1- Back light LED ground 0V
2 VBL2- Back light LED ground 0V
3 VBL1+ Back light LED power 19.8V
4 VBL2+ Back light LED power 19.8V
5 Y1 Top electrode 3.3V
6 X1 Right electrode 3.3V
7 NC No connect
8 RESET Hardware reset 3.3V
9 SPENA SPI interface data enable 3.3V
10 SPCLK SPI interface clock 3.3V
11 SPDAT SPI interface data 3.3V
12 B0 Blue data bit 0 3.3V

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20 G0 Green data bit 0 3.3V
28 R0 Red data bit 0 3.3V
36 HSYNC Horizontal sync input 3.3V
37 VSYNC Vertical sync input 3.3V
38 DCLK Data clock 3.3V
39 NC No connect
40 NC No connect
41 VCC 3.3V power
42 VCC 3.3V power
43 Y2 Bottom electrode 3.3V
44 X2 Left electrode 3.3V
45 NC No connect
46 NC No connect
47 NC No connect
48 SEL2 Input data format 3.3V
51 NC No connect
52 DE Data enable input 3.3V
53 GND Ground 0V
54 GND Ground 0V

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3.4 Touch panel interface
The SPI interface of the OMAP processor is used to communicate with serial interface based
touch screen controller (TSC2046). The touch screen analog signals from the external LCD will
be interfaced with touch screen controller through 4 pin 2.54mm pitch header. The touch screen
analog signals from the 3.5inch LCD will be interfaced with touch screen controller through the
54 pin LCD connector itself. The 4-wire,12bit resolution, low voltage touch screen controller
TSC2046IPWR from TI is used.
The OMAP3530 interface with touch panel controller is shown in Figure 10 & schematics is
shown in Figure 11.
Table 3 lists the Touch panel connector pin details.
OMAP3530
Touch controller
(TSC2046)
McSPI1_CS0
4Pin
header
X+
X-
Y+
Y-
McSPI1_SCLK
McSPI1_Din
McSPI1_Dout
3.5inch
LCD conn

Figure 10: OMAP3530 interface withTouch panel

Figure 11: Touch panel circuit schematic.

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Table 3: 4 Pin Touch panel connector
1 TP_X+ Left electrode
2 TP_Y- Bottom electrode
3 TP_X- Right electrode
4 TP_Y+ Top electrode

3.5 Audio interface
To support the Audio interface, the McBSP2 interface of OMAP3530 processor will be
communicating with I2S interface of the PMIC. It supports 16bit linear audio stereo DAC & ADC
(48, 44.1 & 32 KHz derivatives). Analog single ended Mic configuration will be supported for
audio in support. For speaker output, class-D amplifier will be used externally to drive the speaker
and for headset output the ac coupled headset will be interfaced with class-D predrivers of PMIC.
Audio interface support for OMAP3530 processor is shown in Figure 12, Headset & Mic in
schematic is shown in Figure 13 & Speaker out schematic is shown in Figure 14.

Table 4 & Table 5 lists the MIC in & headset out connector pin details and Table 6 & Table 7 lists
the Left & Right speaker out pin details respectively.
PMIC
(TPS65930)
OMAP3530
I2C1_SDA
I
2
C
I2C1_SCLK
I2C4_SDA
I2C4_SCLK
I
2
C
M
c
B
S
P
2
M
c
B
S
P
2
MCBSP2_CLKX
MCBSP2_FSX
MCBSP2_DR
MCBSP2_DX
P
o
w
e
r
D
C
&
L
D
O
VDD1,VDD2
VMMC1
VPLL1
VDAC,VIO_OUT
A
u
d
i
o
Mic
Speaker
Class-D
Amp
(TPA2010D1)
Mic_Main_P
Mic_Main_M
PreDriv-L
PreDriv-R
Stereo jack
(SJ1-3535NG)

Figure 12: OMAP3530 interface with Audio

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Figure 13: Headset & MIC in circuit schematic

Figure 14: Speaker out circuit schematic

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Table 4: 3 Pin Stereo connector for MIC IN
1 GND Ground
2 MIC_IN Mic input
3 AUXR Auxiliary audio input right or Mic input
Table 5: 3 Pin Stereo connector for Headset OUT
1 GND Ground
2 PreD.Left Predriver Left Out
3 PreD.Right Predriver Right out
Table 6: 3 Pin Stereo connector for left speaker Out
1 GND Ground
2 OUTL+ Class-D amp speaker OutL+
3 OUTL- Class-D amp speaker OutL-
Table 7: 3 Pin Stereo connector for right speaker Out
1 GND Ground
2 OUTR+ Class-D amp speaker OutR+
3 OUTR- Class-D amp speaker OutR-

3.6 Ethernet controller interface
The 10/100 Ethernet controller (LAN9220) from SMSC is a peripheral chip that performs the
functions of translating parallel data from the host controller into Ethernet packets. It supports
both MAC and PHY transceiver. The variable voltage I/O signals of the LAN9220 accommodate
lower voltage I/O signaling without the need for the voltage level translators. The GPMC
controller of processor configured in non-multiplexed mode and interfaced with Ethernet
controller.
The OMAP3530 processor interface with ethernet controller is shown in Figure 15 & schematics
is shown in Figure 16.
Table 8 lists the RJ45 Ethernet connector pin details.

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OMAP3530
WR#
LAN9220
D[15:0]
INT
GPMC_D[15:0]
A[7:1]
GPMC_A[7:1]
GPMC_CS3#
GPMC_WE#
GPMC_OE#
RD#
CE#
GPIO
RJ45 Conn
+Mag
TX+
TX-
RX-
RX+
LED2
LED1
25MHz
Reset Out# Reset#

Figure 15: OMAP3530 interface with Ethernet controller

Figure 16: Ethernet Controller circuit schematic

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Table 8: RJ 45 connector Pin Description
1 TXD+ Transmit data+
2 TXD- Transmit data-
3 RXD+ Receive data+
4 TXD-CT
Connected to 2.5V output of Ethernet controller 5 RXD-CT
6 RXD- Receive data-
7 NC No Connection
8 GND Ground
9 LED1+ Connect to VCC_3V3
10 LED1- Speed LED
11 LED2- Link/Active LED

3.7 RS232 interface
The MAX3386ECPWG4 from Texas Instruments is a three driver and two receiver RS232
Transceiver. It is capable of running at data rates up to 250kbps. It has unique VL pin that allows
operation in mixed logic voltage systems. Both driver in and receiver out logic levels are pin
programmable through VL (1.8V) Pin. The UART3 signals (TXD, RXD) of OMAP3530
processor is used for debugging purpose. Since UART3 signals are multiplexed with IrDA
signals, when IrDA interface is used, optional UART1 signals will be used for debugging
interface. The DB-9 male connector is provided on the board.
The OMAP3530 processor interface with RS232 transceiver is shown in Figure 17 & schematics
is shown in Figure 18. Table 9 lists the RS232 connector pin details.
OMAP3530
RS232
Transceiver
(MAX3386)
UART3_TXD
DB-9
UART3_RXD
U3_TXD
U3_RXD
UART1_RXD
UART1_TXD
U1_TXD
U1_RXD

Figure 17: OMAP3530 interface with RS232 interface

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Figure 18: RS232 interface circuit schematic
Table 9: DB-9 Male connector
1 NC No connect
2 RXD Receive data
3 TXD Transmit data
4 NC No connect
5 GND Ground
6 NC No connect
7 NC No connect
8 NC No connect
9 NC No connect

3.8 RTC interface
The PMIC TPS65930 contains an RTC to provide clock and timekeeping functions and an EPC to
provide battery supervision and control. It also implements backup mode in which backup battery
can keep the RTC running to maintain clock and time information even if main supply is not
present.
RTC provides the following basic functions:
- Time information (seconds/minutes/hours) directly in binary-coded decimal (BCD) code
- Calendar information (day/month/year/day of the week) directly in BCD code

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- Interrupt generation periodically (1 second/1 minute/1 hour/1 day) or at a precise time
(alarm function)
- 32-kHz oscillator drift compensation and time correction
RTC interface is shown in Figure 19 & schematics is shown in Figure 20.

PMIC
(TPS65930)
OMAP3530
I2C1_SDA
I
2
C
I2C1_SCLK
I2C4_SDA
I2C4_SCLK
I
2
C
P
o
w
e
r
D
C
&
L
D
O
VDD1,VDD2
VMMC1
VPLL1
VDAC,VIO_OUT
R
T
C
RTC battery
(CR2032)

Figure 19: OMAP3530 interface with RTC interface

Figure 20: RTC interface circuit schematic

3.9 USB2.0 Host interface
The OMAP 3530 Processor of CUS package supports 2 USB host ports (HSUSB1 & HSUSB2) at
high speed, full speed and low speed. The USB host port2 of OMAP3530 is interfaced with ULPI
transceiver in high speed (480Mbps) operation with 8 bit mode. ULPI transceiver ISP1505ABS
from NXP will be used to interface with USB host system of processor. It is offered in HVQFN24

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package.
The OMAP3530 interface with USB2.0 host transceiver is shown in Figure 21 & schematics is
shown in Figure 22.
Table 10 lists the USB Type A connector pin details.
OMAP3530
ULPI Transceiver
(ISP1505)
USB_ULPI_CLK
USB
Type A
D+
D-
USB_ULPI_DIR
USB_ULPI_STP
USB_ULPI_NXT
USB_ULPI_DATA[7:0]
19.2MHz
VBUS
Power Distribution
Switch
FAULT
+5V
EN
VIN
VBUS

Figure 21: OMAP3530 Processor USB Host Interface

Figure 22: USB host circuit schematic

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Table 10: Type A connector Pin Description
Note: Currently this interface is not supported in the Unified Learning Kit.

3.10 USB2.0 OTG interface
The OMAP 3530 Processor has high speed USB OTG subsystem HSUSB0 port. It operates either
in USB host at high speed (480Mbps), full speed (12Mbps) and low speed (1.5Mbps) or in USB
peripheral at high speed or full speed. The PMIC device includes USB OTG transceiver with CEA
carkit interface. USB host port0 (HSUSB0) of processor is interfaced with OTG transceiver
(PHY) in high speed (480Mbps) through ULPI mode. When OTG configured as Host, the power
to VBUS will be generated from charge pump circuit of PMIC chip (nominal 4.8V).
The OMAP3530 processor interface with OTG transceiver is shown in Figure 23 & schematics is
shown in Figure 24.
Table 11 lists the USB OTG connector pin details.
PMIC
(TPS65930) OMAP3530
I2C1_SDA
I
2
C
I2C1_SCLK
I2C4_SDA
I2C4_SCLK
I
2
C
U
S
B

O
T
G
HSUSB0_DIR
HSUSB0_CLK
HSUSB0_D[7:0]
USB Mini-AB
(VSM-C-UMAB)
DP
DM
U
S
B

O
T
G
HSUSB0_STP
HSUSB0_NXT
P
o
w
e
r
D
C
&
L
D
O
VDD1,VDD2
VMMC1
VPLL1
VDAC,VIO_OUT
P
H
Y
ID
VBUS

Figure 23: OMAP3530 interface with OTG transceiver

1 VCC +5V (VBUS_HS)
2 D- Data-
3 D+ Data+
4 GND Ground

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Figure 24: USB OTG circuit schematic
Table 11: Type mini AB connector Pin Description
1 VCC +5V (VBUS_OTG or VCC_OTG)
2 D- Data-
3 D+ Data+
4 ID OTG ID signal

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5 GND Ground

3.11 VGA interface
The triple 10bit, 240MSPS speed video DAC (THS8135PHP) from TI will be used to convert the
24 bit digital parallel RGB signals into analog RGB signals to display in the VGA monitors
through DB-15pin VGA cable. The Horizontal and vertical sync signals (Hsync, Vsync) of
processor will be converted from 1.8 into 5V and will be given to VGA connector.
The VGA interface is shown in Figure 25 & schematics is shown in Figure 26.
Table 12 lists the VGA connector pin details.
OMAP3530
Video DAC
(THS8135B)
DSS_D[17:0]
VGA Conn
(DB-15)
R
G
B
DSS_PCLK
GPIO for blank
DSS_Hsync
DSS_Vsync
Level Tx-5V
Hsync
Vsync

Figure 25: OMAP3530 interface with VGA

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Figure 26: VGA interface circuit schematic
Table 12: 15 Pin VGA connector
1 Red Red Video
2 Green Green Video
3 Blue Blue Video
4 NC No connect
5 GND Ground
6 RGND Red Ground
7 GGND Green Ground
8 BGND Blue Ground
9 NC No connect
10 SGND Sync Ground
11 NC No connect
12 SDA I2C data
13 HSYNC Horizontal Sync
14 VSYNC Vertical Sync
15 SCL I2C clock

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3.12 I2C EEPROM interface
The 32Kx8 (256Kbits) serial electrically erasable PROM (24AA256-I/SM) from Microchip is
used to interface with OMAP processor through I2C interface. It operates at either 100 KHz or
400 KHz clock. For VCC<2.5V, It operates at 100 KHz speed. The I2C3 of the processor is
interfaced with EEPROM at 100 KHz operation.
The OMAP3530 interface with I2C EEPROM is shown in Figure 27 & schematics is shown in
Figure 28.
OMAP3530
I2C EEPROM
(24AA256-I/SM)
I2C3_CLK
I2C3_SDA

Figure 27: OMAP3530 interface with I2C EEPROM

Figure 28: I2C EEPROM circuit schematic.

3.13 FPGA interface
The GPMC bus of the OMAP3530 processor is used to communicate with Spartan-6 FPGA for
register read/write and for programming the FPGA. In this case GPMC controller signals of
OMAP3530 Processor will be Configuring in address/data non-multiplexed mode. As well as

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Chip select signals (CS0-4), SPI3, I2C3 and GPIO signals will be connected to FPGA for misc
communication. To generate interrupt from FPGAProcessor (GPIO127) and ProcessorFPGA
(GPIO126) two dedicated GPIO signals are used.
The GPMC & other interface signals between FPGA and OMAP processor is shown in Figure 29
& schematics is shown in.Figure 30.
OMAP3530
SPARTAN-6
FPGA
GPMC_ADV#_ALE
GPMC_BE0#_CLE
GPMC_CS[7:4]# mux with PWM
GPMC_WE#
GPMC_OE#
GPMC_A[26:17]
GPMC_A[16:1]/D[15:0]
GPMC_Wait[3:0]
GPMC_BE1#
GPMC_CLK
McSPI3_CS0,McSPI3_Dout
McSPI3_SCLK
McSPI3_Din
I2C3_SCLK;I2C3_SDA
GPIO126 for interrupt
GPIO127 for interrupt
Reset#

Figure 29: OMAP3530 interface with FPGA

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Figure 30: OMAP-FPGA interface circuit schematic

3.14 JTAG interface
The IEEE1149.1 JTAG interface is used for software and hardware debugging. The test emulation
signals of processor EMU0 & EMU1 will be pulled high at POR to configure the initial scan chain
of OMAP processor to TAP router-only mode. The 2.54mm pitch dual row (7x2) 14-pin header
for XDS510 JTAG IF is used on the board.
The OMAP3530 interface with JTAG is shown in Figure 31 & schematics is shown in Figure 32.
Table 13 lists the JTAG connector pin details.

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ARM
JTAG IF
OMAP3530 XDS510 JTAG
TCK
TDI
TRST
TMS
TDO
RTCK
EMU0
EMU1

Figure 31: OMAP3530 interface with JTAG

Figure 32: OMAP JTAG circuit schematic
Table 13: 14 Pin JTAG connector for Processor
Voltage level
1 TMS Test Mode Select 1.8V
2 TRSTn JTAG Test Reset 1.8V
3 TDI JTAG Test Data Input 1.8V
4 GND Ground
5 PD Presence Detect 1.8V
6 NC No Connect

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7 TDO JTAG Test Data Out 1.8V
8 GND Ground
9 TCK RET JTAG Test Clock Return 1.8V
10 GND Ground
11 TCK JTAG Test Clock 1.8V
12 GND Ground
13 EMU0 Emulation Pin0 1.8V
14 EMU1 Emulation Pin1 1.8V

3.15 MMC/SD1 interface
The MMC1/SD/SDIO interface of the OMAP3530 processor is configured in 4bit SD mode to
interface with SD memory cards. It supports both 1.8V & 3V without external transceiver. To
support the Card detect signal, the GPIO0 of PMIC is configured as input and interrupt to the
processor will be given through Sys_nIRQ.
The SD signals of OMAP3530 is interfaced with SD connector as shown in Figure 33 &
schematics is shown in Figure 34.
Table 14 lists the SD1 connector pin details.
OMAP3530
MMC/SD1_CLK
MMC/SD1_CMD
MMC/SD1_DATA0
MMC/SD1_DATA1
MMC/SD1_DATA2
MMC/SD1_DATA3
SD1 Connector
(DM1AA-SF-PEJ )
GPIO for write protect
GPIO0
For CD
PMIC
Sys_nirq

Figure 33: OMAP3530 interface with SD1

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Figure 34: SD1 interface circuit schematic
Table 14: SD1 Connector Pin Description
Voltage level
1 MMC1_DATA3 Data3 signal 1.8 or 3.3V
2 MMC1_CMD Command signal 1.8 or 3.3V
3 VSS Ground
4 VDD 3.3V
5 MMC1_CLK Clock signal 1.8 or 3.3V
6 VSS Ground
10 CD1 Card detect signal 1.8V
11 COM Ground
12 WP Write protect 3.3V

3.16 SD2 interface
The MMC2/SD/SDIO interface of the OMAP3530 processor is configured in 4bit SD mode to
interface with Wi-Fi / Bluetooth cards. The SD signals of OMAP3530 is interfaced with SD
connector through external transceiver SN74AVCA406DGGR from TI to support 1.8 & 3.3V
cards. To support the Card detect signal, the GPIO1 of PMIC is configured as input and interrupt

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to the processor will be given through Sys_nIRQ.
The SD2 signals of OMAP3530 is interfaced with SD2 connector through transceiver as shown in
Figure 35 & schematics is shown in Figure 36.
Table 15 lists the SD2 connector pin details.
OMAP3530
SD2_CLK
SD2_CMD
SD2_DATA[3:0]
SD2_Dir_DATA[3:0]
SD2_CLK
SD2_CMD
SD2_DATA0
SD2_DATA1
SD2_DATA2
SD2_DATA3
Card detect
SD2 Connector
(DM1AA-SF-PEJ)
Transceiver
(SN74AVCA406)
SD2_CLKin
SD2_Dir_CMD
1.8V 3.3V or 1.8V
GPIO1
For CD
PMIC
Sys_nirq

Figure 35: OMAP3530 interface with SD2

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Figure 36: SD2 interface with transceiver circuit schematic
Table 15: SD2 Connector Pin Description
Voltage level
1 MMC2_DATA3 Data3 signal 3.3V
2 MMC2_CMD Command signal 3.3V
3 VSS Ground
4 VDD 3.3V
5 MMC2_CLK Clock signal 3.3V
6 VSS Ground
10 CD2 Card detect signal 1.8V
11 COM Ground
12 WP Write protect 3.3V

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3.17 Character LCD interface
The HD44780 based character LCD will be supported by using I2C3 interface of processor
through I2C to I/O expander chip (MCP23017-E/SO) from Microchip tech. The chip will be
configured by using I2C3. It operates in 1.8V. The 16x2 character LCD from oriole electronics
will be used to interface with processor. The supply voltage range is 5V.
Character LCD interface is shown in Figure 37 & schematic is shown in Figure 38.
Table 16 lists the Character LCD connector pin details.
OMAP3530
D[7:0]
R/W
RS
Clock (E)
+5V
I2C to I/O
Expander
I2C3_SDA
I2C3_SCL
INT_Out

Figure 37: OMAP3530 interface with Character LCD

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Figure 38: Character LCD circuit schematic
Table 16: 16 Pin Character LCD connector
1 VSS Ground
2 VDD Power (3.3V or 5V)
3 VL Power supply for LCD drive
4 RS Register selection
5 RW Read/Write selection
6 EN Starts data read/write
7 P_D0 Data bit 0
8 P_D1 Data bit 1
9 P_D2 Data bit 2
10 P_D3 Data bit 3
11 P_D4 Data bit 4
12 P_D5 Data bit 5

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13 P_D6 Data bit 6
14 P_D7 Data bit 7
15 LED+ Back light power (5V)
16 LED- Back light ground

3.18 TV out interface
The OMAP 3530 processor has in built display subsystem that support TV out in Composite video
(CVBS) & Separate video (S-Video) formats.
The TV display path includes the following modules:
Display controller
Video encoder
Dual 10-bit DAC with video amplifiers
The output data to the TV set are the analog composite data from the DAC. The following video
standards are supported:
NTSC-J, M
PAL-B, D, G, H, I, N
PAL-M
PAL-N
PAL-Nc
TV out interface is shown in Figure 39 & schematic is shown in Figure 40.
Table 17 lists the TV out connector pin details.
OMAP3530
TV_VFB1
TV out
(RCA jack)
TV_OUT1
Discrete
components

Figure 39: OMAP interface with TV Out

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Figure 40: TV Out circuit schematic
Table 17: TV out connector (RCA jack)
1 TV_OUT1 DAC1 video output (Composite output)
2 GND Ground
3 GND Ground
4 GND Ground

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4. FPGA interface
4.1 DDR2 SDRAM interface
The DDR2 SDRAM controller will be implemented inside the FPGA. The DDR2 SDRAM
(EDE5116AJBG-8E-E) from Elpida will be operating at 200MHz speed with CAS latency of 5.
The device is configured in 8Mx16x4banks. The device will be configured either through DDR2
SDRAM controller supported by FPGA or through DDR2 controller which will be implemented
in FPGA.
The FPGA interface with DDR2SDRAM are shown in Figure 41 & schematics is shown in Figure
42. Table 18 lists the FPGA pin-out details.
FPGA
DDR2
SDRAM
(64MB)
CK
CS#
DDR_CLK
DDR_CLK#
RAS# DDR_RAS#
CAS#
DDR_CAS#
WE#
DDR_WE#
DDR_CS#
CKE DDR_CKE
DDR_DQM0
DDR_DQS[0]
DDR_BA[1:0]
DDR_A[12:0]
DDR_DQ[15:0]
LDM
DDR_DQM1 UDM
BA[1:0]
A[12:0]
DQ[15:0]
LDQS
DDR_DQS[1]
UDQS
CK#

Figure 41: FPGA-DDR2 SDRAM interface

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Figure 42: FPGA DDR2 SDRAM circuit schematic

Table 18: FPGA pin-out details for DDR2 SDRAM interface
FPGA Pin
No.
FPGA Signal Description
R3 M3_DQ0 DDR2 data0
R1 M3_DQ1 DDR2 data1
P2 M3_DQ2 DDR2 data2
P1 M3_DQ3 DDR2 data3
L3 M3_DQ4 DDR2 data4
L1 M3_DQ5 DDR2 data5
M2 M3_DQ6 DDR2 data6

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M1 M3_DQ7 DDR2 data7
T2 M3_DQ8 DDR2 data8
T1 M3_DQ9 DDR2 data9
U3 M3_DQ10 DDR2 data10
U1 M3_DQ11 DDR2 data11
W3 M3_DQ12 DDR2 data12
W1 M3_DQ13 DDR2 data13
Y2 M3_DQ14 DDR2 data14
Y1 M3_DQ15 DDR2 data15
K2 M3_A0 DDR2 address0
M6 M3_A3 DDR2 address3
H3 M3_A4 DDR2 address4
M3 M3_A5 DDR2 address5
L4 M3_A6 DDR2 address6
G3 M3_A8 DDR2 address8
G1 M3_A9 DDR2 address9
J4 M3_A10 DDR2 address10
E1 M3_A11 DDR2 address11
F1 M3_A12 DDR2 address12
J6 M3_A13 DDR2 address13
H5 M3_A14 DDR2 address14
H2 M3_WEn Write enable (active low)
M5 M3_RASn Row Address Strobe (active low)
M4 M3_CASn Column Address Strobe (active low)
J3 M3_BA0 Bank select0
J1 M3_BA1 Bank select1
H1 M3_BA2 Bank select2
F2 M3_CKE Clock enable
N4 M3_LDM Lower Write data mask
P3 M3_UDM Upper Write data mask
N3 M3_LDQS Lower data strobe (positive)
N1 M3_LDQSn Lower data strobe (negative)
V2 M3_UDQS Upper data strobe (positive)
V1 M3_UDQSn Upper data strobe (negative)
K4 M3_CLK Clock input (positive)
K3 M3_CLKn Clock input (negative)
L6 M3_ODT On-die termination

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4.2 Ethernet PHY interface
The MAC controller will be implemented inside the FPGA to support 10 or 100 Mbps Ethernet /
IEEE 802.3 networks. An external PHY transceiver IP101A from IC+ is required to complete the
interface to the media. So External PHY transceiver is used to communicate with network.
FPGAs MII will be connected to PHY transceiver. RJ45 connector with magnetics will be
provided in the board for Ethernet Interface.
The FPGA Interface with Ethernet PHY transceiver is shown in Figure 43 & schematics is shown
in Figure 44.
Table 19 lists the RJ45 Ethernet connector pin details & Table 20 lists the FPGA pin-out details.

FPGA
Ethernet PHY
(IP101A)
TX_EN
RJ45 Conn
With Magnetics
TX+
RX+
TX-
RX-
TX_ER
TX_CLK
TXD[0:3]
MDC
MDIO
RX_CLK
RX_DV
RXD[0:3]
CRS
COL
25MHz

Figure 43: FPGA-Ethernet PHY interface

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Figure 44: FPGA Ethernet Phy Circuit Schematic
Table 19: RJ 45 connector Pin Description
1 TXD+ Transmit data+
2 TXD- Transmit data-
3 RXD+ Receive data+
4 TXD-CT Connected to 2.5V output of
Ethernet controller 5 RXD-CT
6 RXD- Receive data-
7 NC No Connection
8 GND Ground
10 LED1- Speed LED
11 LED2- Link/Active LED

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Table 20: FPGA pin-out details for Ethernet interface
FPGA Pin
No.
F10 FPGA_MDC Management Data Interface Clock
D3 FPGA_MDIO Management Data interface Input/Output
D4 FPGA_TXD0 Transmit Data0
D5 FPGA_TXD1 Transmit Data1
B2 FPGA_TXD2 Transmit Data2
A2 FPGA_TXD3 Transmit Data3
E5 FPGA_TXEN Transmit Enable
G9 FPGA_TXCK Transmit Clock
E6 FPGA_RXDV Receive Data Valid
B3 FPGA_RXD0 Receive Data0
A3 FPGA_RXD1 Receive Data1
C4 FPGA_RXD2 Receive Data2
A4 FPGA_RXD3 Receive Data3
H12 FPGA_RXCK Receive Clock
F7 FPGA_COL Collision Detect
F8 FPGA_CRS Carrier Sense
C5 FPGA_RXER Receive error
A5 LAN_INT_OUT Interrupt

4.3 Serial configuration PROM interface
The Spartan-6 FPGA supports SPI Flash interface for the configuration of FPGA in Master serial
SPI Mode. The Configuration mode is selected suitably by FPGA Mode select pins. The
AT45DB161D-SU from ATMEL is used for the same. It is supported with 2Mega Byte or 16
Mega Bit size.
The SPI PROM interface with FPGA is shown in Figure 45 & schematics is shown in Figure 46.
Table 21 lists the FPGA pin-out details.

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FPGA
SPI Flash
(AT45DB161D)
CCLK
CSO_B
MOSI
DIN

Figure 45: FPGA-SPI PROM interface

Figure 46: FPGA SPI PROM circuit schematic
Table 21: FPGA pin-out details for SPI PROM interface
FPGA Pin
No.
Y20 CCLK Serial Clock
AB20 MOSI Master Output Slave Input
AA20 MISO Master Input Slave Output
AA3 CSO_B Chip Select

4.4 RS232 interface
The UART controller will be implemented inside the FPGA and will be interfaced with RS232

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transceiver. The right angle, through hole DB-9 connector is provided on the board. The
MAX3232IPWR from Texas Instruments is served as RS232 Transceiver on the board.
The FPGA interface with RS232 is shown in Figure 47 & schematics is shown in Figure 48
Table 22 lists the RS232 UART connector pin details & FPGA pin-out details.
FPGA
RS232
Transceiver
(MAX3232)
FPGAIO_UART_TXD
DB-9
FPGAIO_UART_RXD
TXDOUT
RXDIN

Figure 47: FPGA-RS232 interface

Figure 48: FPGA-RS232 circuit schematic
Table 22: DB-9 Male connector
FPGA Pin
No.
FPGA Signal Connector Pin
No.
Connector Signal Description
1 NC No connect
G13 FPGA_RXD 2 RXD Receive data
H13 FPGA_TXD 3 TXD Transmit data
4 NC No connect

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5 GND Ground
6 NC No connect
7 NC No connect
8 NC No connect
9 NC No connect

4.5 Charater LCD interface
The 8-bit parallel interface logic will be developed inside the FPGA to configure the HD44780
based dot matrix LCD controller for the character LCD support. The 16x2 character LCD from
oriole electronics will be used to interface with FPGA through 8 bit parallel mode using FPGA
I/Os. The supply voltage range is 5V.
The FPGA interface with character LCD is shown in Figure 49 & schematics is shown in Figure
50.
Table 23 lists the character LCD pin details & FPGA pin-out details.
FPGA
D[7:0]
R/W
Register Select(RS)
Clock (E)
Power (+5V)

Figure 49: FPGA-Character LCD interface

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Figure 50: FPGA-Character LCD circuit schematic
Table 23: 16 Pin Character LCD connector
FPGA
Pin No.
FPGA Signal Connector
Pin No.
1 VSS Ground
2 VDD Power (3.3V or 5V)
3 VL Power supply for LCD drive
W11 CHAR_RS 4 RS Register selection
T10 CHAR_RWn 5 RW Read/Write selection
U10 CHAR_EN 6 EN Starts data read/write
Y10 CHAR_D0 7 P_D0 Data bit 0
AB9 CHAR_D2 9 P_D2 Data bit 2
AA8 CHAR_D4 11 P_D4 Data bit 4
U6 CHAR_D7 14 P_D7 Data bit 7
W9 FPGA_CHAR_BL 15 LED+ Back light power (5V)
16 LED- Back light ground

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4.6 ADC interface
The 10-bit, 20MSPS sampling analog to digital converter AD9200 from Analog devices is used to
interface with FPGA through 10 bit parallel interface. The AD9200 is configured Top/Bottom
mode by connecting mode pin to AVDD and analog input level is set by using REFTS, REFBS
signals. In our application, it is configured for 0 to 2VP-P analog input.
The internal reference voltage (Vref) is configured in 2V mode by connecting REFSENSE pin to
ground as shown in Figure 51 & schematic is shown in Figure 52.

Table 24 lists the ADC connector pin details & Table 25 lists the FPGA pin-out details.
FPGA
ADC
(AD9200)
D[9:0]
Ain (0 to 2V)
Refsense
Mode
AVDD
Refbs
Refts
Vref

Figure 51: FPGA-ADC interface

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Figure 52: ADC circuit schematic

Table 24: 3 Pin Stereo connector for ADC input
Connector Pin No. Connector Signal Description
1 GND Ground
2 & 3 ADC_IN Analog input

Table 25: FPGA pin-out details for ADC
FPGA Pin No. FPGA Signal Description
R13 FPGA_ADC_D0 ADC data0
V11 FPGA_ADC_D1 ADC data1
U14 FPGA_ADC_D2 ADC data2
T14 FPGA_ADC_D3 ADC data3
W13 FPGA_ADC_D4 ADC data4
U13 FPGA_ADC_D5 ADC data5
AA14 FPGA_ADC_D6 ADC data6
W14 FPGA_ADC_D7 ADC data7

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Y14 FPGA_ADC_D8 ADC data8
AB14 FPGA_ADC_D9 ADC data9
T12 ADC_CLK ADC clock

4.7 DAC interface
The 12-bit, 10MSPS sampling digital to analog converter DAC7821 from TI is used to interface
with FPGA through 12 bit parallel interface. It provides single channel current output. The
bidirectional bus is controlled with CS# and R/W# signal to read/write into/from DAC. The
control signals will be generated from FPGA. Op Amp OPA348 is used to convert the current
output of DAC to voltage output.
The FPGA interface with DAC is shown in Figure 53 & schematics is shown in Figure 54.
Table 26 lists the DAC connector pin details & Table 27 lists the FPGA DAC pin-out details.
FPGA
DAC
(DAC7821)
D[11:0]
Iout1
Iout2
VDD
3.3V
Vref
-3.3V
CS#
R/W#
Op Amp
(OPA348)
-IN
+IN
Vout
Out

Figure 53: FPGA-DAC interface

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Figure 54: DAC circuit schematic

Table 26: 3 Pin Stereo connector for DAC output
Connector Pin No. Connector Signal Description
1 GND Ground
2 & 3 DAC_RFB DAC output

Table 27: FPGA pin-out details for DAC
V13 FPGA_DAC_D0 DAC data0
AA16 FPGA_DAC_D1 DAC data1
Y16 FPGA_DAC_D2 DAC data2
W15 FPGA_DAC_D3 DAC data3
AA18 FPGA_DAC_D4 DAC data4

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W17 FPGA_DAC_D5 DAC data5
AB19 FPGA_DAC_D6 DAC data6
Y15 FPGA_DAC_RWn DAC Read/Write enable
AB15 FPGA_DAC_CSn DAC chip select

4.8 7 Segment LED interface
To display 4 digit 7 segment LEDs, LTC-4627JR device is used from Lite-On electronics. LTC-
4627JR is a common anode device. FPGA I/O's are used to drive the cathodes and common
anodes of the 7 segment LED display.
7 segment LED interface is shown in Figure 55 & schematics is shown in Figure 56.
Table 28 lists the FPGA 7 segment LED interface pin-out details.
FPGA
Common Anode_Digit1
4-digit 7 Segment
(LTC-4627JR)
Common Anode_Digit2
Common Anode_Digit3
Common Anode_Digit4
Cathode A
Cathode B
Cathode C
Cathode D
Cathode E
Cathode F
Cathode G
Cathode DP

Figure 55: FPGA-7segment LED interface

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Figure 56: 7 segment LED circuit schematic
Table 28: FPGA pin-out details for 7 segment LED
U12 FPGA_AN1 Common Anode digit1
Y13 FPGA_AN2 Common Anode digit2
AB13 FPGA_AN3 Common Anode digit3
W10 FPGA_AN4 Common Anode digit4
B20 FPGA_CA Cathode A
A20 FPGA_CB Cathode B
D17 FPGA_CC Cathode C
C18 FPGA_CD Cathode D
G16 FPGA_CE Cathode E
F15 FPGA_CF Cathode F
G11 FPGA_CG Cathode G
Y19 FPGA_DP Cathode DP

4.9 I2C EEPROM interface
The I2C controller will be implemented inside the FPGA to access the EEPROM. The 32Kx8
(256Kbits) serial electrically erasable PROM (24AA256-I/SM) from Microchip is used to
interface with FPGA through I2C interface. It operates at either 100 KHz or 400 KHz clock. For

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VCC<2.5V, It operates at 100 KHz speed. The I2C of the FPGA is interfaced with EEPROM at
100 KHz operation. It is common to both processor and FPGA.
The I2C EEPROM interface with FPGA is shown Figure 57 & schematic is shown in Figure 58.
Table 29 lists the FPGA I2C EEPROM interface pin-out details.
FPGA
I2C EEPROM
(24AA256-I/SM)
I2C_CLK
I2C_SDA

Figure 57: FPGA-I2C EEPROM interface

Figure 58: FPGA-I2C EEPROM circuit schematic

Table 29: FPGA pin-out details for I2C EEPROM
V22 FPGA_I2C_SCL I2C Clock
V21 FPGA_I2C_SDA I2C data

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4.10 JTAG interface
Spartan-6 devices support the IEEE 1532 standard for In-System Configuration (ISC), based on
the IEEE 1149.1 standard. The IEEE 1149.1 Test Access Port and Boundary-Scan Architecture
are commonly referred to as JTAG. JTAG interface is used to directly load the configuration data
into the internal memory of the FPGA. To configure the FPGA through processor, 4 GPIO signals
of processor are level translated and connected to the JTAG pins.
The FPGA interface with JTAG is shown in Figure 59 & schematic is shown in Figure 60 &
Figure 61. Table 30 lists the FPAG JTAG connector pin details.
FPGA
JTAG
TCK
TMS
TDI
TDO
Level
Tx
3V
TI OMAP
3530

Figure 59: FPGA interface with JTAG

Figure 60: FPGA JTAG circuit schematic

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Figure 61: OMAP-FPGA JTAG interface through buffer circuit schematic
Table 30: 14 Pin JTAG connector for FPGA
Voltage level
1 GND Ground
2 VCC_3V3 Power
3 GND Ground
4 TMS Test Mode Select 3.3V
5 GND Ground
6 TCK JTAG Test Clock 3.3V
7 GND Ground
8 TDO JTAG Test Data Out 3.3V
9 GND Ground
10 TDI JTAG Test Data Input 3.3V
11 GND Ground
12 NC No Connect
13 GND Ground
14 NC No Connect
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5.External Interfaces
5.1 Processor Keypad interface
6x6 keypad is supported through keypad controller of PMIC chip which has built-in scanning
algorithm to decode hardware based key presses and its signals will be taken out to the 15 pin
2.54mm pitch external header provided in the board.
Keypad interface is shown in Figure 62 and schematic & layout is shown in Figure 63.
Table 31 lists the pin details of the Keypad connector.

Please refer to OMAP 3530 technical reference manual (Literature Number: SPRUF98C)
CH18 page 2630 for details on I2C.
Please refer to TPS65930 technical reference manual (Literature Number: SWCU052C)
Chapter 9 page 459 for details on Keypad controller.
PMIC
(TPS65930)
OMAP
I2C1_SDA
I
2
C
I2C1_SCLK
I2C4_SDA
I2C4_SCLK
I
2
C
Keypad Conn
(15pin header)
KPD_ROW[4:0]
KPD_COL[4:0]
P
o
w
e
r
D
C
&
L
D
O
VDD1,VDD2
VMMC1
VPLL1
VDAC,VIO_OUT
K
e
y
p
a
d

Figure 62: OMAP3530 interface with Keypad

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Figure 63: 6x6 Processor Keypad circuit schematic & layout
Table 31: 15 pin Keypad connector
1 KPD_ROW0 Keypad Row input 0 signal
7 1.8V 1.8V power
8 GND Ground
9 KPD_COL0 Keypad column out0 signal
15 GND Ground

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5.2 I/O expansion connector
The MMC2,UART2 with flow control, MCBSP1, I2C2, reset signals of OMAP processor &
power signals are brought out to the 28 pin expansion connector as same as beagle board
expansion connector to allow for the connection to various expansion cards that could be
developed by users. The 28-Pin (14x2 dual row) standard 2.54mm pitch is provided for I/O
expansion connector.
The OMAP3530 interface with I/O expansion connector is shown in Figure 64 & schematics is
shown in Figure 65.
Table 32 lists the Processor pins assigned to the I/O expansion connector.
Note: While using I/O Expansion connector, keep the dip switch SW11.8 in OFF position.

Please refer to OMAP 3530 technical reference manual (Literature Number: SPRUF98C) -
CH22 page 3019 for details on MMC
CH17 page 2512 for details on UART
CH21 page 2852 for details on McBSP
OMAP3530
28Pin I/O
Expansion
MMC2_DAT[7:0]
UART2_CTS
UART2_TX
McBSP1_DX
UART2_RX
UART2_RTS
McBSP1_CLKX
McBSP1_FSX
McBSP1_DR
McBSP1_CLKR
MMC2_CMD
MMC2_CLK
McBSP1_FSR
I2C2_SCL
I2C2_SDA
5V,1.8V,GND
Reset
REGEN

Figure 64: OMAP3530 interface with I/O expansion connector

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Figure 65: IO Expansion connector circuit schematic

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Table 32: 28-pin I/O expansion connector
Pin
No.
Signal Description Voltage
level
1 1.8V Power signal 1.8V
2 5V Power signal 5V
3 MMC2_Dat7 MMC2 dataline7 1.8V
4 UART2_CTS UART clear to send 1.8V
5 MMC2_DIR_CMD Direction control for CMD signal 1.8V
6 UART2_TX UART transmit data 1.8V
7 MMC2_DIR_DAT1 Direction control for DAT1 and DAT3 signals 1.8V
8 UART2_RX UART receive data 1.8V
9 MMC2_DIR_DAT0 Direction control for DAT0 signal 1.8V
10 UART2_RTS UART request to send 1.8V
12 McBSP1_DX Multichannel buffered serial port1 transmit data 1.8V
14 McBSP1_CLKX Multichannel buffered serial port1 transmit clock 1.8V
16 McBSP1_FSX Multichannel buffered serial port1 transmit frame sync 1.8V
18 McBSP1_DR Multichannel buffered serial port1 receive data 1.8V
19 MMC2_CMD MMC2 command/response 1.8V
20 McBSP1_CLKR Multichannel buffered serial port1 receive clock 1.8V
21 MMC2_CLKO MMC2 clock out 1.8V
22 McBSP1_FSR Multichannel buffered serial port1 receive frame sync 1.8V
23 I2C2_SDA I2C2 serial data 1.8V
24 I2C2_SCL I2C2 serial clock 1.8V
25 REGEN Regulator enable signal for LDO 3.3V
26 Reset# Active low reset 1.8V
27 GND Ground
28 GND Ground

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5.3 Simple digital interface
Simple Digital interface is used for simple LAB examples including stepper motor control. It
contains the following signals: 20GPIOs (UART2, McBSP1 & MMC3 interface signals will be
configured as GPIO for input or output & for interrupt), 1GPT_PWM_EVT, VCC (5V) & GND
(2 pins). All the signals are 5V level converted using the level translators and taken out to the DB-
25 parallel port connector. Please note that GPIO signals can be shared with 28 pin expansion
connector, Bluetooth connector and control sensor header.
Simple digital interface is shown in Figure 66 & schematic is shown in Figure 67.
Table 33 lists the Processor pins assigned to the Simple Digital interface connector.
Note:
While using Simple Digital interface, keep the dip switch SW11.8 in ON position.
Also keep the dip switches SW11.1, SW11.2, SW11.3, SW11.4, & SW11.5 in OFF position.

CH22 page 3391 for details on GPIO
CH16 page 2435 for details on PWM
OMAP3530
Simple Digital IF
(DB-25)
UART2 as GPIOs Level Tx
5V
McBSP1 as GPIOs
MMC3 as GPIOs
MMC3 as GPIOs
UART2 as GPIOs
McBSP1 as GPIOs
GPT8_PWM_EVT GPT8_PWM_EVT
5V , GND

Figure 66: OMAP3530 interface with Simple Digital Interface connector

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Figure 67: Simple Digital Interface circuit schematic

Table 33: 25-pin Simple Digital Interface connector
Pin
No.
Signal Description Voltage level
1 GPIO140 (UART2_CTS) Configured as GPIO140 5V
2 GPIO141 (UART2_RTS) Configured as GPIO141 5V
3 GPIO142 (UART2_TX) Configured as GPIO142 5V
4 GPIO143 (UART2_RX) Configured as GPIO143 5V
5 GPT8_PWM_EVT Configured as PWM signal 5V
6 GPIO158 (McBSP1_DX) Configured as GPIO158 5V
7 GPIO162 (McBSP1_CLKX) Configured as GPIO162 5V
8 GND Ground
9 GPIO161 (McBSP1_FSX) Configured as GPIO161 5V
10 GPIO159 (McBSP1_DR) Configured as GPIO159 5V
11 GPIO156 (McBSP1_CLKR) Configured as GPIO156 5V
12 GND Ground
13 GPIO157 (McBSP1_FSR) Configured as GPIO157 5V
14 GPIO12 (MMC3_CLK) Configured as GPIO12 5V
15 GPIO13 (MMC3_CMD) Configured as GPIO13 5V
16 GPIO14 (MMC3_D4) Configured as GPIO14 5V
21 GND Ground
24 5V 5V power signal 5V
25 5V 5V power signal 5V

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5.4 Control sensor interface
Control sensor header is used to interface with many of the sensors & ADC/DAC for control
system applications. It contains the following signals: SPI interface McSPI3 with CS1 (mux with
MMC3) signals for external ADC/DAC support, I2C interface (I2C3), GPT_PWM_EVT (mux
with CS [7:4]), and 5V VCC, GND. All the Signals are 5V level converted using level translators
and taken out to the connector. Please note that interface signals are shared with FPGA & simple
digital interface. The 15 pin, 2.54mm pitch connector will be used.
OMAP3530 interface with Control sensor interface is shown in Figure 68 & schematics is shown
in Figure 69.
Table 34 lists the Processor pins assigned to the Control sensor header.
Note: While using Control sensor interface, keep the dip switch SW11.8 in OFF position.

CH19 page 2726 for details on McSPI
CH16 page 2435 for details on PWM
OMAP3530
Control sensor IF
(15pin)
CS[4:0]_PWM_EVT
Level Tx
5V
McSPI3 IF with CS1
I2C3_SCL & I2C3_SDA I2C3_SCL & I2C3_SDA
CS[4:0]_PWM_EVT
McSPI3 IF with CS1
5V,GND
GPIO22 &23
GPIO22 &23

Figure 68: OMAP3530 interface with Control Sensor header

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Figure 69: Control Sensor Header circuit schematic

Table 34: 15-pin Control Sensor Header
Pin
No.
1 I2C3_SCL I2C3 serial clock 5V
2 I2C3_SDA I2C3 serial data 5V
3 nCS4_GPT9_PWM_EVT Configured as PWM 5V
7 GND Ground
8 McSPI3_CS1 (mux with MMC3) SPI3 chip select1 5V
9 McSPI3_CLK (mux with MMC3) SPI3 clock 5V

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10 McSPI3_SIMO (mux with MMC3) SPI3 slave in master out 5V
11 McSPI3_SOMI (mux with MMC3) SPI3 master in slave out 5V
13 GPIO20 (MMC3_D2) Configured as GPIO20 (I/P) 5V
14 5V 5V power 5V
15 5V 5V power 5V

5.5 Bluetooth or Modem interface
It is used to support the external Bluetooth or modem modules. It contains the following interface
signals: UART2, I2C2, McBSP1.The external modules either Bluetooth or modem will be
plugged into the Bluetooth header. All the signals are 3.3V compatible by using level translators.
Please note that the interface signals can be shared with I/O expansion connector & simple digital
interface. The dual row 10x2 pin, 2.54mm pitch connector will be used.
OMAP processor interface with Bluetooth connector is shown in Figure 70 & schematics is
shown in Figure 71.
Table 35 lists the Processor pins assigned to the connector.

CH17 page 2512 for details on UART
CH21 page 2852 for details on McBSP
OMAP3530
Bluetooth Conn
(20 pin header)
Level Tx
3.3V
UART2_CTS
UART2_TX
McBSP1_DX
UART2_RX
UART2_RTS
McBSP1_CLKX
McBSP1_FSX
McBSP1_DR
McBSP1_CLKR
McBSP1_FSR
I2C2_SCL
I2C2_SDA
UART2_CTS
UART2_TX
McBSP1_DX
UART2_RX
UART2_RTS
McBSP1_CLKX
McBSP1_FSX
McBSP1_DR
McBSP1_CLKR
McBSP1_FSR
I2C2_SCL
I2C2_SDA
3.3V,5V &GND

Figure 70: OMAP3530 interface with Bluetooth or Modem Interface

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Figure 71: Bluetooth or Modem interface circuit schematic

Table 35: Bluetooth or Modem connector
Pin
No.
1 UART2_CTS UART clear to send 3.3V
2 UART2_TX UART transmit data 3.3V
3 UART2_RX UART receive data 3.3V
4 UART2_RTS UART request to send 3.3V
5 GND Ground
6 McBSP1_DX Multichannel buffered serial port1 transmit data 3.3V
7 McBSP1_CLKX Multichannel buffered serial port1 transmit clock 3.3V
8 GND Ground
9 McBSP1_FSX Multichannel buffered serial port1 transmit frame sync 3.3V

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10 McBSP1_DR Multichannel buffered serial port1 receive data 3.3V
11 McBSP1_CLKR Multichannel buffered serial port1 receive clock 3.3V
12 GND Ground
13 McBSP1_FSR Multichannel buffered serial port1 receive frame sync 3.3V
14 I2C2_SDA I2C2 serial data 3.3V
15 I2C2_SCL I2C2 serial clock 3.3V
16 3.3V Power 3.3V
17 3.3V Power 3.3V
18 GND Ground
19 5V Power 5V
20 GND Ground

5.6 External LCD interface
The 24bit RGB Out signals and LCD control signals of OMAP3530 processor is taken out to the
two 20 pin LCD connectors as same as beagle board LCD connector. The voltage levels of these
signals are 1.8V. To support different types of LCD, Add-on card has to be developed and
plugged into the two LCD connectors provided in the ULK.
The External LCD interface is shown in Figure 72 & schematics is shown in Figure 73.
Table 36 & Table 37 lists the Processor pins assigned to the External LCD connector.

Please refer to OMAP 3530 technical reference manual (Literature Number: SPRUF98C)
CH15 page 2015 for details on LCD controller
OMAP3530
DSS_D[23:0]
LCD Conn1
(10x2)
DSS_HSYNC
DSS_VSYNC
LCD Conn2
(10x2)
DSS_PCLK
I2C3_SDA
DSS_DE
I2C3_SCL

Figure 72: OMAP3530 interface with External LCD

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Figure 73: External LCD circuit schematic

Table 36: External LCD connector1
Pin
No.
1 5V 5V power 5V
2 5V 5V power 5V
3 DSS_DAT1 LCD pixel data bit 1.8V

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15 I2C3_SDA I2C Serial data 1.8V
17 DSS_VSYNC LCD vertical sync signal 1.8V
18 DSS_PUP Control signal for DVI controller GND
19 GND Ground signal
Table 37: External LCD connector2
Pin
No.
1 3.3V 3.3V power signal 3.3V
2 1.8V 1.8V power signal 1.8V
12 NC No connect
14 I2C3_SCL I2C Serial clock 1.8V
16 DSS_CLK LCD Pixel clock 1.8V
17 DSS_DEN Data Enable (GPIO 69) 1.8V
18 DSS_HSYNC Horizontal sync 1.8V

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5.7 Camera interface
The camera interface subsystem is used for imaging and video application such as video preview,
video record, and still image capture with or without digital zooming. It provides system interface
and the processing capability to connect RAW image sensor modules. It operates in two modes
sync mode and ITU mode. It supports most image sensors (resolutions up to 4096x4096).
SYNC mode supports progressive and interlaced image-sensor modules. ITU mode supports only
progressive image-sensor modules.
The 17x2 dual rows, 1.27mm pitch header is used to support the external camera modules.
It will be configured through I2C2 controller of the processor. The external camera modules will
be plugged into the connector provided in the ULK.
Camera interface is shown in Figure 74 & schematic is shown in Figure 75.
Table 38 lists the Processor pins assigned to the Camera connector.

CH12 page 1360 for details on Camera interface

OMAP3530
CAM_D[11:0]
CAM_Hs
I2C2_SCL
Camera Conn
(17x2)
Reset
CAM_Vs
CAM_PCLK
CAM_WEn
CAM_Xclka
I2C2_SDA
Power signals

Figure 74: OMAP3530 interface with Camera

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Figure 75: Camera Interface circuit schematic

Table 38: Camera connector
Pin
No.
1 CAM_D11_GPIO110 Camera digital image data bit 11 or GPIO110 1.8V
2 CAM_XLKA Camera Clock Output a 1.8V
4 GND Ground 1.8V
6 I2C2_SDA I2C data 1.8V
8 I2C2_SCL I2C clock 1.8V
9 CAM_D7 Camera digital image data bit 7 1.8V
10 CAM_FLD_GLOBAL_
RESET
Global reset is used strobe synchronization 1.8V

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12 CAM_WE Camera Write Enable 1.8V
14 GND Ground 1.8V
16 VCC_2V8 2.8V power
20 GND Ground
22 GND Ground
24 VCC_3V3 3.3V power 3.3V
27 CAM_PCLK Camera pixel clock 1.8V
28 GND Ground
29 CAM_HS Camera Horizontal Synchronization 1.8V
31 CAM_VS Camera Vertical Synchronization 1.8V
33 GND Ground
34 GND Ground

5.8 I2C GPS interface
The I2C3 signals from processor are brought out to the 5 pin GPS connector to allow for the
connection of various GPS modules. I2C bus level translator is used to convert the processor 1.8V
signals to 5V signals.
The 5-Pin (5x1 single row) standard 2.54mm pitch is provided for GPS header.
I2C GPS interface is shown in Figure 76 & schematic is shown in Figure 77.
Table 39 lists the Processor pins assigned to the GPS header.


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OMAP3530
GPS HEADER
I2C bus
Level Tx
5V
I2C3_SDA_5V
I2C3_SCL_5V
3.3V, 5V , GND
I2C3_SDA
I2C3_SCL

Figure 76: OMAP interface with GPS Header

Figure 77: GPS header circuit schematic

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Table 39: 5 pin GPS header
Voltage level
1 I2C2_SCL Clock signal 5V
2 GND Ground
3 12C_SDA Data signal 5V
4 5V Power
5 3.3V Power

5.9 IrDA interface
The IrDA interface is supported through UART3, which adds infrared communication support,
and pinned out for use as a UART, infrared data association (IrDA), or consumer infrared (CIR)
device, and can be programmed to any available operating mode. The IrDA signals from
processor are brought out to the 6 pin IrDA connector to interface with IrDA modules.
The 6-Pin (6x1 single row) standard 2.54mm pitch is provided for IrDA header.
IrDA interface is shown in Figure 78 & schematic is shown in Figure 79. Table 40 lists the
Processor pins assigned to the IrDA connector.

CH17 page 2512 for details on UART & IrDA.
OMAP3530
UART3_RX_IRRX
IrDA_SD
IrDA
Conn
UART3_TX_IRTX
CIR_RCTX
1.8V, GND

Figure 78: OMAP interface with IrDA Connector

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Figure 79: IrDA connector circuit schematic

Table 40: 6 pin IrDA Header
Voltage level
1 UART3_CTS_RCTX Remote Transmit 1.8V
2 UART3_RTS_SD IR enable 1.8V
3 GND Ground
4 UART3_RX_IRRX IR and Remote Receive 1.8V
5 UART3_TX_IRTX IR transmit 1.8V
6 VCC_1V8 Power

5.10 FPGA Keypad interface
To support 4rows x 4columns keypad interface, keypad scanning and debouncing logic is

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developed inside the FPGA. The I/O signals of FPGA will be used and signals are taken out to the
12pin 2.54mm pitch header.
Keypad interface support is shown in Figure 80 and schematic is shown in Figure 81.
Table 41 lists the FPGA Keypad connector details & FPGA pin-out details.
FPGA
Keypad
Conn
(12pin header)
FPGA_IO_Row[4:0]
FPGA_IO_Col[4:0]
Power signals

Figure 80: FPGA-Keypad interface

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Figure 81: 4x4 FPGA Keypad circuit schematic

Table 41: 12 pin FPGA Keypad connector
FPGA
Pin No.
Pin No.
H14 FPGA_ROW1 2 FPGA_ROW1 Keypad Row input 1 signal
G15 FPGA_ROW2 3 FPGA_ROW2 Keypad Row input 2 signal
C17 FPGA_ROW3 4 FPGA_ROW3 Keypad Row input 3 signal
A17 FPGA_ROW4 5 FPGA_ROW4 Keypad Row input 4 signal
6 GND Ground
7 GND Ground
G8 FPGA_COL1 9 FPGA_COL1 Keypad column out1 signal
F9 FPGA_COL2 10 FPGA_COL2 Keypad column out2 signal
H10 FPGA_COL3 11 FPGA_COL3 Keypad column out3 signal
H11 FPGA_COL4 12 FPGA_COL4 Keypad column out4 signal

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5.11 FPGA I/O connectors interface
There are 3 I/O connectors used to interface with FPGA I/Os. It is named as Mictor connector
(38pin), FPGA-HDR2 (20pin) with 5V compatible through level translators, and FPGA
Expansion connector (70 pin).
Please note that all the FPGA Mictor connector signals are shared with 70pin Expansion
connector. Block diagram is shown in Figure 82.
FPGA
38 pin Mictor
Connector
FPGA HDR2
(20 pin)
FPGA
Expansion Conn
(70 pin)
FPGA I/Os
FPGA I/Os
Level Tx-5V
Level Tx-3V
FPGA I/Os
FPGA I/Os

Figure 82: FPGA-I/O connectors interface
5.11.1 20-Pin FPGA IO header
Level Translators are used to convert the 1.8V FPGA signals to 5V compatible signals.
Circuit schematic is shown in Figure 83.
Table 42 lists the 20-pin FPGA IO header details & FPGA pin-out details.

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Figure 83: 20-pin FPGA IO header circuit schematic

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Table 42: 20-Pin FPGA IO header
FPGA
Pin No.
Pin No.
Connector
Signal
Description Voltage
level
F18 FPGA_IO1 1 FPGA I/O 1 FPGA input/Output Signal 5V
J16 FPGA_IO3 3 FPGA I/O 3 FPGA input/Output Signal 5V
J17 FPGA_IO4 4 FPGA I/O 4 FPGA input/Output Signal 5V
C20 FPGA_IO5 5 FPGA I/O 5 FPGA input/Output Signal 5V
K19 FPGA_IO7 7 FPGA I/O 7 FPGA input/Output Signal 5V
N19 FPGA_IO8 8 FPGA I/O 8 FPGA input/Output Signal 5V
9 5V 5V power 5V
10 GND Ground
D2 FPGA_IO9 11 FPGA I/O 9 FPGA input/Output Signal 5V
D1 FPGA_IO10 12 FPGA I/O 10 FPGA input/Output Signal 5V
E4 FPGA_IO12 14 FPGA I/O 12 FPGA input/Output Signal 5V
16 NC No connect
P5 FPGA_IO15 17 FPGA I/O 15 FPGA input/Output Signal 5V
P4 FPGA_IO16 18 FPGA I/O 16 FPGA input/Output Signal 5V
19 5V 5V power 5V
20 GND Ground

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5.11.2 38-pin Mictor Connector
3.3V FPGA IO signals are brought out to the Mictor connector.
Table 43 lists the 38-pin Mictor connector details & FPGA pin-out details.
Note: Currently this interface is not supported in the Unified Learning Kit.

Figure 84: 38-pin Mictor connector circuit schematic

Table 43: 38-pin Mictor connector
FPGA Pin
No.
Pin No.
Connector Signal Description Voltage
level
1 GND Ground
2 GND Ground
3 GND Ground
4 GND Ground
D19 FPGA_EXP_IO3 5 FPGA_EXP_IO3 FPGA input/Output Signal 3.3V
AA10 FPGA_EXP_IO19 6 FPGA_EXP_IO19 FPGA input/Output Signal 3.3V
A19 FPGA_EXP_IO7 7 FPGA_EXP_IO7 FPGA input/Output Signal 3.3V
W8 FPGA_EXP_IO21 8 FPGA_EXP_IO21 FPGA input/Output Signal 3.3V
C19 FPGA_EXP_IO6 9 FPGA_EXP_IO6 FPGA input/Output Signal 3.3V

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Y6 FPGA_EXP_IO25 10 FPGA_EXP_IO25 FPGA input/Output Signal 3.3V
B18 FPGA_EXP_IO4 11 FPGA_EXP_IO4 FPGA input/Output Signal 3.3V
T7 FPGA_EXP_IO30 14 FPGA_EXP_IO30 FPGA input/Output Signal 3.3V
F17 FPGA_EXP_IO1 15 FPGA_EXP_IO1 FPGA input/Output Signal 3.3V
R8 FPGA_EXP_IO23 16 FPGA_EXP_IO23 FPGA input/Output Signal 3.3V
V17 FPGA_EXP_IO9 19 FPGA_EXP_IO9 FPGA input/Output Signal 3.3V
AB5 FPGA_EXP_IO27 20 FPGA_EXP_IO27 FPGA input/Output Signal 3.3V
F16 FPGA_EXP_IO34_
PUSH
21 FPGA_EXP_IO34_
PUSH
FPGA input/Output Signal 3.3V
Y5 FPGA_EXP_IO 22 FPGA_EXP_IO FPGA input/Output Signal 3.3V
23 GND Ground

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5.11.3 70-Pin Expansion connector
Most of FPGA signals are directly driven by FPGA which are 3.3V voltage level. For some
signals, level translators are used to convert the 1.8V FPGA signals to 3.3V compatible signals.
Table 44 lists the FPGA 70-pin Expansion connector details & FPGA pin-out details.

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Figure 85: 70-pin FPGA Expansion connector circuit schematic

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Table 44: 70-pin FPGA Expansion connector
FPGA
Pin No.
Pin No.
Connector Signal Description Voltage
level
B18 FPGA_EXP_IO4 5 FPGA_EXP_IO4 FPGA input/Output Signal 3.3V
V17 FPGA_EXP_IO9 8 FPGA_EXP_IO9 FPGA input/Output Signal 3.3V
12 GND Ground
T7 FPGA_EXP_IO30 22 FPGA_EXP_IO30 FPGA input/Output Signal 3.3V
24 GND Ground
36 GND Ground

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F16 FPGA_EXP_IO34_P
USH
40 FPGA_EXP_IO34_P
USH
FPGA input/Output Signal 3.3V
D11 MGTREFCLK1N 42 MGTREFCLK1N Negative differential
reference clock1
NA
C11 MGTREFCLK1P 44 MGTREFCLK1P Positive differential
reference clock1
NA
K19 FPGA_EXP_IO41 45 FPGA_EXP_IO41 FPGA input/Output Signal 3.3V
P4 FPGA_EXP_IO50 46 FPGA_EXP_IO50 FPGA input/Output Signal 3.3V
P5 FPGA_EXP_IO49 47 FPGA_EXP_IO49 FPGA input/Output Signal 3.3V
48 GND Ground
49 VCC_5V 5V power 5V
50 VCC_5V 5V power 5V
N19 FPGA_EXP_IO42 53 FPGA_EXP_IO42 FPGA input/Output Signal 3.3V
54 NC NA
D9 MGTRXP1 56 MGTRXP1 Positive differential receive
port1
NA
J17 FPGA_EXP_IO38 57 FPGA_EXP_IO38 FPGA input/Output Signal 3.3V
C9 MGTRXN1 58 MGTRXN1 Negative differential receive
port1
NA
J16 FPGA_EXP_IO37 59 FPGA_EXP_IO37 FPGA input/Output Signal 3.3V
60 GND Ground
E4 FPGA_EXP_IO46 61 FPGA_EXP_IO46 FPGA input/Output Signal 3.3V
B8 MGTTXP1 62 MGTTXP1 Positive differential transmit
port1
NA
A8 MGTTXN1 64 MGTTXN1 Negative differential
transmit port1
NA
65 GND Ground
66 GND Ground
68 GND Ground
70 GND Ground

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6. Operation & Maintenance Features
6.1 Power & Reset LEDs
Power LEDs are provided in the board for the ON/OFF indication of major powers. Also reset
LED is provided to indicate the board in reset condition.
Table 45 lists the details of power signals connected to LEDs & schematic is shown in Figure 86

Table 45: Power & Reset LEDs
S.No Voltage/Signal Color Remarks
1. VCC_5V Red 5V power is on
2. VCC_3V3 Red 3.3V power is on
5. VIO_1V8 Red 1.8V power is on
6. Reset Yellow Board is in reset condition

Figure 86: Power & Reset LEDs circuit schematic

6.2 LEDs for OMAP3530
General purpose LEDs are connected to processor & PMIC GPIO pins for lab experiment &
testing purpose.
Table 46 lists the details of processor & PMIC GPIO pins connected to LEDs & schematic is
shown in Figure 87.

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Table 46: LEDs for OMAP3530
S.No Voltage/Signal Color Remarks
1. GPIO107 Green For lab experiment & testing
8. PMIC_GPIO13 Green For lab experiment & testing
9. PMIC_GPIO15 Green For lab experiment & testing

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Figure 87: Processor LEDs circuit schematic

6.3 LEDs for FPGA
General purpose LEDs are connected to FPGA IO pins for lab experiment & testing purpose.
Table 47 lists the details of FPGA IO pins connected to LEDs & schematic is shown in Figure
88.
Table 47: LEDs for FPGA
FPGA Pin
No.
FPGA Signal Color Remarks
Y8 FPGA_LED1 Green For lab experiment & testing
AA6 FPGA_LED2 Green For lab experiment & testing

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AB6 FPGA_LED3 Green For lab experiment & testing
U9 FPGA_LED4 Green For lab experiment & testing
V9 FPGA_LED5 Green For lab experiment & testing
T8 FPGA_LED6 Green For lab experiment & testing
U8 FPGA_LED7 Green For lab experiment & testing
V7 FPGA_LED8 Green For lab experiment & testing
AB21 FPGA_DONE Yellow Indicate the status of the DONE pin when
the FPGA is successfully configured.

Figure 88: FPGA LEDs circuit schematic

6.4 Major Test points
The Test points used on the ULK is shown in Table 48.
Table 48: Test Points in ULK
S.No. Test Points Description
1. TP3, TP42 VCC_5V power signal
2. TP4, TP10 VCC_3V3 power signal

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5. TP15, TP38 VIO_1V8 power signal
6. TP13, TP20 VBATT power signal
7. TP1, TP2, TP40 Ground

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7. Switches & Jumpers
7.1 Reset Switch
The Supervisor circuits TLC7701ID & TPS3307-18 will be used to generate reset to the processor
& other peripherals under the following conditions.
o Power on Reset
o Out of Tolerance in Power
o Manual Reset
One of the supervisory circuit (TLC7701ID) is used to monitor 1.2V core voltage of the FPGA.
The reset output of this supervisory circuit will be given to sense3 input of the another supervisory
chip TPS3307-18. The supervisory circuit (TPS3307-18) is used to sense the 1.8V & 3.3V output
from the regulators and will give the reset to the poweron reset pin of OMAP processor. The
warm resetout from processor is connected to all peripherals through reset buffer & level
translator.
A reset switch SW2 shown in Figure 89 is be used for manual reset of the ULK board. Also
optionally, warm reset switch SW3 shown in Figure 90 can be used to reset the ULK board. All
the major interfaces are reset by using a reset buffer shown in Figure 91.

Figure 89: Manual Reset Circuit Schematic

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Figure 90: Warm Reset Circuit Schematic

Figure 91: Reset Buffer Circuit Schematic

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7.2 Toggle Switches
7.2.1 Mode switch
The toggle switch (SW10) is used to control the ULK in either Lab mode or normal operating
mode of the board by using single GPIO (GPIO 128) of the processor. Schematic is shown in
Figure 92.

Figure 92: Mode Switch circuit schematic

7.2.2 Power Switch
The toggle switch (SW1) is used to power on/off the main power supply (VCC_5V). Main power
is given through 5V adaptor jack (J9).
Schematic is shown in Figure 93.

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Figure 93: Power Switch Circuit Schematic

7.3 DIP Switches
7.3.1 System information for OMAP processor
A 8 Position DIP switch is used to operate in LAB mode for students learning. 8 GPIOs from
OMAP processor and PMIC are configured as digital inputs.
Table 49 lists the different GPIOs used & schematic is shown in Figure 94.
Table 49: OMAP DIP Switch details
S.No GPIO used Remarks
1. GPIO12 For lab experiment & testing
6. GPIO2 of PMIC For lab experiment & testing

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Figure 94: OMAP DIP Switch Circuit Schematic

7.3.2 Boot Configuration for OMAP processor
A 6 Position DIP switch is used to select the booting configuration for OMAP processor.
If SYS_BOOT [4:0] 01111, NAND flash booting
If SYS_BOOT5 0, memory booting
1, peripheral booting
If SYS_BOOT6 External clock source is selected
Table 50 lists the details of processor system boot pins & schematic is shown in Figure 95.
Table 50: Boot Configuration DIP Switch details
S.No Pin description Remarks
1. SYS_BOOT0 Boot configuration mode bit 0

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Figure 95: OMAP Boot Configuration Circuit Schematic

7.3.3 System information for FPGA
A 10 Position DIP switch is used to operate in LAB mode for students learning. 10 IOs from
FPGA is configured as digital inputs. The position of the DIPswitch will be decided during the
software testing.
Table 51 lists the FPGA dipswitch details & schematic is shown in Figure 96.

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Table 51: FPGA DIP Switch details
FPGA Pin No. FPGA Signal Remarks
T20 FPGA_DIPSW1 For lab experiment & testing
N16 FPGA_DIPSW2 For lab experiment & testing
P16 FPGA_DIPSW3 For lab experiment & testing
M17 FPGA_DIPSW4 For lab experiment & testing
V19 FPGA_DIPSW6 For lab experiment & testing
V20 FPGA_DIPSW7 For lab experiment & testing
AA2 FPGA_DIPSW8 For lab experiment & testing
AA1 FPGA_DIPSW9 For lab experiment & testing

Figure 96: FPGA DIP Switch Circuit Schematic

7.4 Push button switches for OMAP processor & FPGA
The push button swithes are provided for the following functions
1. Momentary type push button switches for Lab interrupt & schematic is shown in Figure
97.

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Figure 97: Lab interrupt Circuit Schematic

2. 4no.s of momentary type push button switches for FPGA & schematic is shown in Figure
98

Figure 98: Push Button Switches Circuit Schematic

7.5 Jumpers for Processor UART
In ULK board, 2 UART signals (UART1 & UART3) are provided for serial communication
between the host PC & the ULK board.
By default UART3 is used by shorting the jumper JP10 & JP8 as shown in Figure 99

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Figure 99: UART Jumper setting Circuit Schematic

7.6 Jumper for USB OTG
USB OTG connector is provided in the ULK board which can act as either as host or device
depending on the jumper JP5 setting as shown in Figure 100.

Figure 100: USB OTG Jumper setting Circuit Schematic

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8. Dos & Donts

During testing, only top wooden enclosure has to be removed & keep the board on bottom
wooden enclosure.
It is recommended to use the supplied cables / accessories along with the kit. If different
cables / mating connectors are used, ensure to use the compatible ones.
Use only the 5V power supply adaptor that has been provided along with the kit.
Providing different voltage could damage the board.
Dont insert the power cable when the power switch is in ON position.
The devices used in the board are sensitive to ESD. To prevent ESD, dont touch any ICs
or external connectors with bare hand. Ensure to have ESD protection in the lab. Use the
ESD protective wrist strap when connecting the accessories to the board.
Power off the board before connecting the speakers at J15 & J17 connectors.
For good speaker output quality, connect speakers with the following specification: 720
mW/Ch Into 8 .
Power off the board before connecting any external modules.
For ADC, analog signal ranging from 0 to 2V max. can be applied. Applying more than
2V signal may damage the board.
While using J2 connector, pin no. 5 & 8 of switch SW11 should be in OFF position. Also
J13 connector should not be used at the same time.
While using J3 connector, all the pins of switch SW11 should be in OFF position. Also J8
& J13 connector should not be used at the same time.
While using J8 connector, all the pins of switch SW11 should be in OFF position. Also J3
& J13 connector should not be used at the same time.
While using J13 connector, pin no. 8 of switch SW11 should be in ON position rest all
pins of switch SW11 should be in OFF position. Also J3 & J8 connector should not be
used at the same time.
LCD is pasted to the acrylic. Do not try to remove the LCD or the LCD connecting cable.

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As LCD surface is prone for physical damage, handle it carefully and ensure that no
foreign object falls on it & no load is applied to that. Use only the stylus for touch
operation.
Ensure that no foreign materials falls inside the board as it could damage the board
electrically / physically
Do not close the Control Panel while doing the operations on ULK board. If user close the
ULK control Panel then restart the ULK board.
Once the connection is established, do the Disconnect before closing the ULK Control
Panel. If user close the ULK control Panel then restart the ULK board.

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9. Technical Support

iWave Systems Technologies Pvt. Ltd.
# 7/B, 29
th
Main,
BTM Layout 2
nd
Stage,
Bangalore - 560 076
Phone : +91-80-26781643, 26786243
Fax : +91-80-26685200
Email : emdby@iwavesystems.com
Web : www.iwavesystems.com

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Hardware Reference Manual for Mission

10x-Unified Learning Kit

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