Notes on Computer System’s Hardware Review

By: Bahram Abe di

UNITEN
1.1. The Main Components of a Computer System

A computer system is constructed from 5 main sub-systems. They are:

• Input Unit (or input sub-system)
• Output Unit (or output sub-system)
• Central Processing and Control Unit, “CPU” (or CPU sub-system)
• Memory Unit (or memory sub-system), consisting of RAM (inclusive of memory mapped I/O ports) and ROM
• Storage Unit (or Storage Sub-system)

The BASIC COMPUTER consists of Memory and Ports interfaced and interconnected to the CPU through the SYSTEM BUS. Such a
basic computer can execute Programs that are somehow loaded into the memory. Such a system needs a mechanism to sense the external
world and to communicate with it. The I/O subsystems provide such a function. I/O devices are interfaced to the basic computer via their
respective INTERFACES (adopters), which are connected to the basic computer through the LOCAL BUS and a respective PORT. (As an
example, these local busses on the Workstation and PC domain are: Legacy ISA, EISA, PCI, SCSI,...).
To provide a Long term Storage of DATA and PROGRAMS, the Storage sub-systems are also interfaced to the basic system.
Fig 1 and 2 represent a basic computer and a complete computer system respectively.

Display
CPU &Control RAM CPU & RAM
Sub System Memory Control
Subsystem

Disk
ROM
Memory ROM Keyboard
SYSTEM
BUS SYSTEM
BUS I / O and
Storage I / O & Storage
Fig 1: The basic Computer Ports Interfaces and
Consisting CPU, Short Term RAM Memory and Adopters
ROM Fig 2: A complete Computer System Local Bus
1.2 The Main Functionality of a CPU

A CPU is micro-programmed to carry out some primitive instructions, one-at-a-time. These instructions form the Instruction Set
of a particular CPU and it usually includes the following main categories:
• Input / Output and Data movement Instructions (for example: MOV AX,BX or MOV BL,10 or IN 208 or OUT
30F,etc..)
• Arithmetic Operations Instructions (such as ADD AH,BH or SUB AX, BX, etc..)
• Logical Operations Instructions (such as AND AX,A600 or SHR AL, etc..)
• Branch and Control Transfer Instructions (such as JNZ 200 or JMP [SI] or INT 21 or, CALL 300, etc..)

As one can conclude these instructions alone and on their own do not offer much in terms of real world data processing demand.
However, orderly arrangement of them into a sequence of instructions to form a program produces a functional routine that can
achieve something useful when executed.

Therefor, the CPU is connected to a memory subsystem by a computer vendor and some essential programs are written into ROM
and added to it as the Firmware (ROM BIOS). This is to enable the basic computer to execute the program which is already in the
ROM when it is turned-on and also can be further utilised to load other programs into RAM. Such a Wired-In program is called
The Instruction Cycle. It is the infinite loop that a computer goes through over and over and as the result the resident programs
are executed.

1.3 The Simple Instruction Cycle

The following Figure represents a simple instruction cycle:

Interpret the
Fetch the Next Increment the Instruction’s OP- Execute the
Start Instruction CODE and Generate Decoded
Instruction Pointer
(Turn On) From Memory the needed Micro-Code Instruction
Signals for Execute
this Instruction

Fig. 3: The Implementation of a Simple Instruction Cycle

1.4 The Details of the Events taking Place In the Instruction Cycle

Once the computer is turned on, the System Clock starts ticking and provides the time base for each stage of the instruction cycle
that stops only after the computer is turned off.
During each cycle of this simple instruction cycle, one instruction is fetched from the memory and brought to the CPU and is
executed there.
Here we look at this process in more details. We look at the role of the system bus in the cycle.

1.5 The Components of the System Bus

In figure 1 and 2 we observe the system bus interconnects the memory, ports and the CPU.
In the following figure. (Fig. 4 ), the system bus is broken down into 3 buses. They are:

• Address Bus It is a unidirectional bus to indicate the addressed memory location.

• Data Bus A Bi-directional bus to carry instructions and data from memory to CPU and otherwise.
• Control Bus To convey the timing and control signals

From Programmer’s view point, the details of the cycle is as follows:

1. FETCH ==> Get the instruction addressed by IP in the memory and load it into MBR , thus:
1.1 IP ==>MAR
1.2 [MAR] ==> DATA BUS
1.3 DATA BUS ==> MBR

2. INCREMENT ==> Increment the IP by the increment factor interpreted from the instruction’s OPERATION
CODE (OP CODE) to get ready for next fetch, thus:
2.1 IP = IP + <INCREMENT FACTOR>

3. DECODE ==> Send the Instruction code in the MBR to IR so that IR interpret it and generate the
EXECUTION CONTROL SIGNALS needed for its execution, thus:
3.1 MBR ==> IR
3.2 IR ==> <Produce the micro code needed for the execution control at the IR’s output>

4. EXECUTE ==> Send the IR’s Output to the Seuencer to starts the execution sequence, thus:
4.1 IR ==> Sequencer
Fig. 4 A SIMPLIFIED BUS ARCITECTURED COMPUTER SYSTEM NNNN:0000

MOV AL,20 NNNN:0100 RAM Memory used for

SYSTEM and USER
NNNN:0101 Programs & Data
General Purpose AH AL
Pair Registers MOV BL,25 NNNN:0102
BH BL
AX,BX,CX, and DX M UNIDIRECTIONAL
ADDRESS BUS
NNNN:0103
CH CL A
ADD AL,BL NNNN:0104
DH DL R
NNNN:0105
CS
SUB AL,BL NNNN:0106
DS
Segment NNNN:0107
Registers SS
MOV AH,4C NNNN:0108
ES NNNN:0109
Index & Pointer SP
NT 21 NNNN:010A
Registers
DI NNNN:010B ROM Memory used for
Start Up Boot Program,
SI
M BIOS and other FIRM
Instruction Execution WARE such as C-MOS
Control Signals For IP ( PC ) B
Register Transfer Routines
R ROM
( Micro-code ) FFFF::0000
IR
FFFF:FFFF
CONTROL BUS

SEQUENCER

DISPLA
Display Y UNIT
Adapter
Display Port
The Simplified View of the
internal bus and main registers
of an INTEL-LIKE Micro Disk Port
Disk
Processor
Interface DISK
UNIT
INPUT / OUTPUT Keyboard
BI-DIRECTIONAL PORTS Port
DATA BUS
Local Bus Keyboard KEYBOARD
( ISA, PCI,...) Interface UNIT
Now let's view the whole process of the execution of this resident program on the following event vs entity diagram. The System Clock starts ticking and each tick is a CLK pulse (signal) that initiate the START of an EVENT. Each
event lasts a fraction of a second and termination of it is pulsed by the next CLK tick which in -turn is the start of the next event in the cycle. In the given notes titled: Notes On the Instruction Cycle, these events are enumerated as
1.1, 1.2, 1.3 for FETCH, 2.1 for INCREMENT, 3.1 and 3.2 for Decode and finally 4.1 for EXECUTE. Note that the following diagram represents 2 full cycle for execution of 2 instructions.

BL 25

AL ???? 20

EXEC ???? EXEC EXEC

IR-OUT ??? MICRO- CODE FOR (BO20) MICRO-CODE FOR (B325)

IR MOV BL,25 ( B325 )

???? MOV AL,20 ( B020 )

??? MOV AL.20 ( BO20 ) MOV BL,25 ( B325 )

MBR

D-BUS ??? MOV AL,20 ( BO20 ) MOV BL,25 ( B325 )

MAR ??? 100 102

IP 100 102 104

CLK

FETCH DECODE
2.1 INC.

EXECUTE

1.1 1.2 1.3 3.1 3.2

4.1
Exercises:

1- What is a program made of ?

2- State 3 different categories of the Instructions
3- What are the components of the system bus ?
4- What are the main stages of the instruction cycle?
5- What is the basic capability of a CPU? Can we execute a program in a CPU alone?(without Memory)
6- Can an instruction be executed while still in memory?
7- What is the role of the Instruction Register “IR” ?
8- Refer to the Diagram 4 and try to execute the given Memory resident program by following the details of the instruction
cycle. Assume the IP holds the value of 100 when the cycle starts .
9- What is the value of the CPU registers, MAR and MBR at the end of the execution of the above program?
10- The given instruction cycle in Fig. 3 do not allow any external event communicate with the running program. It is the running program that
INITIATES any input from the external programs (processes) or starts any output to the outside world. Reason why it is so. And argue how interrupt
mechanism can solve the problem.