E-CAD LAB 1.

LOGIC GATES AIM: To Design the following Logic Gates and verify the functionality using software and hardware. 1.AND Gate 2.OR Gate 3.NOT Gate .NAND Gate !.NOR Gate ".#$%OR Gate &.#$%NOR Gate APPARATUS: '. (ilin$ ise ).2i 2. Digital *+%& ,-.& 32.& , .& ,,.& ,2.& -".& '3! 3. /ower cards. interfacing cards AND GATE I.DESIGN PROCEDURE: ' .Def:%A circuit whose out0ut is ' if 1oth of its in0uts are ' and out0ut is , if any of it2s in0ut is ,. 2 Deter3ine the re4uired nu31er of in0ut and out0ut fro3 s0ecification Nu31er of in0uts:2 Nu31er of out0uts:' 3. Assign a sy31ol to each in0ut5out0ut *n0uts:x,y Out0uts:z 3. Derive the truth ta1le fro3 the re4uired relationshi0 *n0uts $ , , ' ' y , ' , ' Out0ut 6 , , , '

-'

E-CAD LAB

. O1tain the si30lified 7oolean functions

!. Draw the logic diagra3 and verify design correctness

II PIN DIAGRAM OF IC7408: The a1ove logic diagra3 can 1e re0resented using co33ercially availa1le *+ & $,- as shown:

III VERIFICATION USING SOFTWARE: VHDL CODE: Li1rary *###8 use *###.std9logic9''" .all8 -2

E-CAD LAB

entity AND2 is 0ort: $ : in ;TD9LOG*+8 y : in ;TD9LOG*+8 6 : out ;TD9LOG*+ <8 end AND28 --Dataflow model architecture 1ehav' of AND2 is 1egin =>? $ and y8 end 1ehav'8 --Signal Assignment Statement

-- Behavioral model architecture 1ehav2 of AND2 is 1egin 0rocess :$. y< 1egin if :$?@'@ and y?@'@< then -- Compare with truth table = >? @'@8 else = >? @,@8 end if8 end 0rocess8 end 1ehav28
PROCEDURE :

'. O0en (ilin$ /roAect Navigator 2. O0en New /roAect 3. ;elect Target Device details . #nter BCDL /rogra3 !. +o30ile for ;ynta$ errors ". ;i3ulate design using Dodel ;i3 -3

E-CAD LAB &. Berify the functionality of design with e$0ected results -. ;ynthesi6e design using (;T :(ilin$ ;ynthesis Tool< ). Erite Fser +onstrain Gile to fi$ in5out 0orts on Target device ',. Generate 0rogra33ing file ''. Down load design to the target device on G/GA5+/LD de3o 1oard '2. Berify the functionality of design with e$0ected results OUT PUT WAVE FORM:

--

E-CAD LAB

OR ga !
I.DESIGN PROCEDURE: ' .Def:%A circuit whose out0ut is , when all the in0uts are , otherwise the out0ut will 1e '. 2 Deter3ine the re4uired nu31er of in0ut and out0ut fro3 s0ecification Nu31er of in0uts:2 Nu31er of out0uts:' 3. Assign a sy31ol to each in0ut5out0ut *n0uts:x,y Out0uts:z 3. Derive the truth ta1le fro3 the re4uired relationshi0 *n0uts $ , , ' ' y , ' , ' Out0ut 6 , ' ' '

. O1tain the si30lified 7oolean functions -!

E-CAD LAB

!. Draw the logic diagra3 and verify design correctness

II PIN DIAGRAM OF IC7432: The a1ove logic diagra3 can 1e re0resented using co33ercially availa1le *+ & $32 as shown:

III VERIFICATION USING SOFTWARE: VHDL CODE: Li1rary *###8 use *###.std9logic9''" .all8 entity OR2 is 0ort: $ : in ;TD9LOG*+8 y : in ;TD9LOG*+8 6 : out ;TD9LOG*+ -"

E-CAD LAB <8 end OR28 --Dataflow model architecture 1ehav' of OR2 is 1egin = >? $ or y8 end 1ehav'8 --Signal Assignment Statement

-- Behavioral model architecture 1ehav2 of OR2 is 1egin 0rocess :$. y< 1egin if :$?@,@ and y?@,@< then -- Compare with truth table = >? @,@8 else =>? @'@8 end if8 end 0rocess8 end 1ehav28
PROCEDURE:

'. O0en (ilin$ /roAect Navigator 2. O0en New /roAect 3. ;elect Target Device details . #nter BCDL /rogra3 !. +o30ile for ;ynta$ errors ". ;i3ulate design using Dodel ;i3 -&

E-CAD LAB &. Berify the functionality of design with e$0ected results -. ;ynthesi6e design using (;T :(ilin$ ;ynthesis Tool< ). Erite Fser +onstrain Gile to fi$ in5out 0orts on Target device ',. Generate 0rogra33ing file ''. Down load design to the target device on G/GA5+/LD de3o 1oard '2. Berify the functionality of design with e$0ected results

OUTPUT WAVEFORM:

--

E-CAD LAB

NOT ga ! I.DESIGN PROCEDURE: ' .Def:%A circuit whose out0ut is co30li3ent of the in0ut. 2 Deter3ine the re4uired nu31er of in0ut and out0ut fro3 s0ecification Nu31er of in0uts:' Nu31er of out0uts:' 3. Assign a sy31ol to each in0ut5out0ut *n0uts:x Out0uts:y 3. Derive the truth ta1le fro3 the re4uired relationshi0 *n0ut Out0ut $ , ' y ' ,

. O1tain the si30lified 7oolean functions -)

E-CAD LAB

!. Draw the logic diagra3 and verify design correctness

II PIN DIAGRAM OF IC7404: The a1ove logic diagra3 can 1e re0resented using co33ercially availa1le *+& $, as ;hown:

III VERIFICATION USING SOFTWARE: VHDL CODE: Li1rary *###8 use *###.std9logic9''" .all8 entity not' is 0ort: (: in ;TD9LOG*+8 =: out ;TD9LOG*+ -',

E-CAD LAB <8 end not'8 --Dataflow model architecture 1ehav' of not' is 1egin =>? not (8 --Signal Assignment Statement end 1ehav'8

-- Behavioral model architecture 1ehav2 of not' is 1egin 0rocess :(< 1egin if :$?@,@< then -- Compare with truth table = >? @'@8 else =>? @,@8 end if8 end 0rocess8 end 1ehav28
PROCEDURE:

'. O0en (ilin$ /roAect Navigator 2. O0en New /roAect 3. ;elect Target Device details . #nter BCDL /rogra3 -''

E-CAD LAB !. +o30ile for ;ynta$ errors ". ;i3ulate design using Dodel ;i3 &. Berify the functionality of design with e$0ected results -. ;ynthesi6e design using (;T :(ilin$ ;ynthesis Tool< ). Erite Fser +onstrain Gile to fi$ in5out 0orts on Target device ',. Generate 0rogra33ing file ''. Down load design to the target device on G/GA5+/LD de3o 1oard '2. Berify the functionality of design with e$0ected results

OUTPUT WAVEFORM:

-'2

E-CAD LAB

NAND ga ! I.DESIGN PROCEDURE: ' .Def:%A circuit whose out0ut is , when all the in0uts are ' otherwise the out0ut will 1e '. 2 Deter3ine the re4uired nu31er of in0ut and out0ut fro3 s0ecification Nu31er of in0uts:2 Nu31er of out0uts:' 3. Assign a sy31ol to each in0ut5out0ut *n0uts:x,y Out0uts:z 3. Derive the truth ta1le fro3 the re4uired relationshi0 *n0uts $ , , ' ' -'3 y , ' , ' Out0ut 6 ' ' ' ,

E-CAD LAB

. O1tain the si30lified 7oolean functions

!. Draw the logic diagra3 and verify design correctness

II PIN DIAGRAM OF IC7400: The a1ove logic diagra3 can 1e re0resented using co33ercially availa1le *+ & $,, as shown:

-'

E-CAD LAB

III VERIFICATION USING SOFTWARE: VHDL CODE: Li1rary *###8 use *###.std9logic9''" .all8 entity nand2 is 0ort: $ : in ;TD9LOG*+8 y : in ;TD9LOG*+8 6 : out ;TD9LOG*+ <8 end nand28 --Dataflow model architecture 1ehav' of nand2 is 1egin 6>? $ nand y8 end 1ehav'8 -- Behavioral model architecture 1ehav2 of nand2 is 1egin /rocess :$. y< 7egin *f :$?@'@ and y?@'@< then -- Compare with truth table = >? @,@8 else = >? @'@8 end if8 end 0rocess8 end 1ehav2
PROCEDURE:

--Signal Assignment Statement

-'!

E-CAD LAB '. O0en (ilin$ /roAect Navigator 2. O0en New /roAect 3. ;elect Target Device details . #nter BCDL /rogra3 !. +o30ile for ;ynta$ errors ". ;i3ulate design using Dodel ;i3 &. Berify the functionality of design with e$0ected results -. ;ynthesi6e design using (;T :(ilin$ ;ynthesis Tool< ). Erite Fser +onstrain Gile to fi$ in5out 0orts on Target device ',. Generate 0rogra33ing file ''. Down load design to the target device on G/GA5+/LD de3o 1oard '2. Berify the functionality of design with e$0ected results

OUTPUT WAVEFORM:

-'"

E-CAD LAB

NOR ga ! I.DESIGN PROCEDURE: ' .Def:%A circuit whose out0ut is ' when all the in0uts are , otherwise the out0ut will 1e ,. 2 Deter3ine the re4uired nu31er of in0ut and out0ut fro3 s0ecification Nu31er of in0uts:2 Nu31er of out0uts:' 3. Assign a sy31ol to each in0ut5out0ut *n0uts:x,y Out0uts:z 3. Derive the truth ta1le fro3 the re4uired relationshi0

-'&

E-CAD LAB *n0uts $ , , ' ' y , ' , ' Out0ut 6 ' , , ,

. O1tain the si30lified 7oolean functions

!. Draw the logic diagra3 and verify design correctness

II PIN DIAGRAM OF IC7402: The a1ove logic diagra3 can 1e re0resented using co33ercially availa1le *+ & $,2 as shown:

-'-

E-CAD LAB

III VERIFICATION USING SOFTWARE: VHDL CODE: Li1rary *###8 use *###.std9logic9''" .all8 entity nor2 is /ort : (: in ;TD9LOG*+8 H: in ;TD9LOG*+8 =: out ;TD9LOG*+ <8 end nor28 --Dataflow model architecture 1ehav' of nor2 is 1egin =>? $ nor y8 --Signal Assignment Statement end 1ehav'8 -- Behavioral model architecture 1ehav2 of nor2 is 1egin -')

E-CAD LAB 0rocess :$. y< 1egin *f :$?@,@ and y?@,@< then -- Compare with truth table = >? @'@8 else = >? @,@8 end if8 end 0rocess8 end 1ehav28
PROCEDURE:

'. O0en (ilin$ /roAect Navigator 2. O0en New /roAect 3. ;elect Target Device details . #nter BCDL /rogra3 !. +o30ile for ;ynta$ errors ". ;i3ulate design using Dodel ;i3 &. Berify the functionality of design with e$0ected results -. ;ynthesi6e design using (;T :(ilin$ ;ynthesis Tool< ). Erite Fser +onstrain Gile to fi$ in5out 0orts on Target device ',. Generate 0rogra33ing file ''. Down load design to the target device on G/GA5+/LD de3o 1oard '2. Berify the functionality of design with e$0ected results

OUTPUT WAVEFORM:

-2,

E-CAD LAB

E"-OR ga ! I.DESIGN PROCEDURE:

-2'

E-CAD LAB ' .Def:%A circuit whose out0ut is , when all the in0uts are sa3e otherwise the out0ut will 1e '. 2 Deter3ine the re4uired nu31er of in0ut and out0ut fro3 s0ecification Nu31er of in0uts:2 Nu31er of out0uts:' 3. Assign a sy31ol to each in0ut5out0ut *n0uts:x,y Out0uts:z 3. Derive the truth ta1le fro3 the re4uired relationshi0 *n0uts $ , , ' ' y , ' , ' Out0ut 6 , ' ' ,

. O1tain the si30lified 7oolean functions

!. Draw the logic diagra3 and verify design correctness

-22

E-CAD LAB

II PIN DIAGRAM OF IC7486: The a1ove logic diagra3 can 1e re0resented using co33ercially availa1le *+ & $-" as shown:

III VERIFICATION USING SOFTWARE: VHDL CODE: Li1rary *###8 use *###.std9logic9''" .all8 entity $or2 is /ort : (: in ;TD9LOG*+8 H: in ;TD9LOG*+8 =: out ;TD9LOG*+ <8 end $or28 --Dataflow model architecture 1ehav' of $or2 is 1egin =>? $ $or y8 --Signal Assignment Statement -23

E-CAD LAB end 1ehav'8 -- Beh !"#$ % &#'e% architecture 1ehav2 of $or2 is 1egin 0rocess :$. y< 1egin *f :$5?y< then = >? @'@8 else =>? @,@8 end if8 end 0rocess8 end 1ehav28
PROCEDURE:

-- Compare with truth table

'. O0en (ilin$ /roAect Navigator 2. O0en New /roAect 3. ;elect Target Device details . #nter BCDL /rogra3 !. +o30ile for ;ynta$ errors ". ;i3ulate design using Dodel ;i3 &. Berify the functionality of design with e$0ected results -. ;ynthesi6e design using (;T :(ilin$ ;ynthesis Tool< ). Erite Fser +onstrain Gile to fi$ in5out 0orts on Target device ',. Generate 0rogra33ing file ''. Down load design to the target device on G/GA5+/LD de3o 1oard '2. Berify the functionality of design with e$0ected results -2

E-CAD LAB

OUTPUT WAVEFORM:

-2!

E-CAD LAB

E"-NOR ga ! I.DESIGN PROCEDURE: ' .Def:%A circuit whose out0ut is ' when all the in0uts are sa3e otherwise the out0ut will 1e ,. 2 Deter3ine the re4uired nu31er of in0ut and out0ut fro3 s0ecification Nu31er of in0uts:2 Nu31er of out0uts:' 3. Assign a sy31ol to each in0ut5out0ut *n0uts:x,y Out0uts:z 3. Derive the truth ta1le fro3 the re4uired relationshi0 *n0uts $ , , ' ' y , ' , ' Out0ut 6 ' , , '

. O1tain the si30lified 7oolean functions

-2"

E-CAD LAB !. Draw the logic diagra3 and verify design correctness

II PIN DIAGRAM OF IC74(3): The a1ove logic diagra3 can 1e re0resented using co33ercially availa1le *+ & $'3! as shown:

III VERIFICATION USING SOFTWARE: VHDL CODE: Li1rary *###8 use *###.std9logic9''" .all8 entity $nor2 is /ort : (: in ;TD9LOG*+8 H: in ;TD9LOG*+8 =: out ;TD9LOG*+ <8 end $nor28 -2&

E-CAD LAB

--Dataflow model architecture 1ehav' of $nor2 is 1egin =>? $ $nor y8 --Signal Assignment Statement end 1ehav'8 -- Beh !"#$ % &#'e% architecture 1ehav2 of $nor2 is 1egin 0rocess :$. y< 1egin *f :$?y< then = >? @'@8 else =>? @,@8 end if8 end 0rocess8 end 1ehav28
PROCEDURE:

-- Compare with truth table

'. O0en (ilin$ /roAect Navigator 2. O0en New /roAect 3. ;elect Target Device details . #nter BCDL /rogra3 !. +o30ile for ;ynta$ errors ". ;i3ulate design using Dodel ;i3 &. Berify the functionality of design with e$0ected results -. ;ynthesi6e design using (;T :(ilin$ ;ynthesis Tool< ). Erite Fser +onstrain Gile to fi$ in5out 0orts on Target device -2-

E-CAD LAB ',. Generate 0rogra33ing file ''. Down load design to the target device on G/GA5+/LD de3o 1oard '2. Berify the functionality of design with e$0ected results

OUTPUT WAVEFORM:

-2)

E-CAD LAB

#. $x% DECODER *+& '3AIM: To Design the 3$- Decoder and verify the functionality using software and hardware. APPARATUS: '. (ilin$ ise ).2i 2. Digital *+%& '33. /ower cards. interfacing cards DESIGN PROCEDURE: '.Def:% A n%to%2n decoder taIes an n%1it in0ut and 0roduces 2n out0uts. The n in0uts re0resent a 1inary nu31er that deter3ines which of the 2n out0uts is uni4uely true. 2.Deter3ine the re4uired nu31er of in0ut and out0ut fro3 s0ecification Nu31er of in0uts: 38 #na1le *n0uts:3 Nu31er of out0uts: 3. Assign a sy31ol to each in0ut5out0ut *n0uts : A.7.+.G'.G2A9L.G279L Out0uts : H&9L. H"9L. H!9L. H 9L. H39L. H29L. H'9L. H,9L . Derive the truth ta1le fro3 the re4uired relationshi0 G' G2A9L G279L + , $ $ $ $ ' $ $ $ $ ' $ ' , , , ' , , , ' , , , ' , , , -7 A H&9L H"9L H!9L H 9L H39L H29L H'9L H,9L $ $ ' ' ' ' ' ' ' ' $ $ ' ' ' ' ' ' ' ' $ $ ' ' ' ' ' ' ' ' , , ' ' ' ' ' ' ' , , ' ' ' ' ' ' ' , ' ' , ' ' ' ' ' , ' ' ' ' ' ' ' ' , ' ' ' 3,

E-CAD LAB ' ' ' ' , , , , , , , , ' ' ' ' , , ' ' , ' , ' ' ' ' , ' ' , ' ' , ' ' , ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '

!. O1tain the si30lified 7oolean functions &' ( G1 . G#A . G#B . C . B . A 7ecause of the inversion 1u11les. we have the following relations 1etween internal and e$ternal signals: G#A( G#A)L* G#B( G#B)L* &' ( &')L* Therefore.we can write the following e4uation for the e$ter%nal out0ut signal H!9Lin ter3s of e$ternal in0ut signals: &')L ( &'* ( +G1 . G#A)L* . G#B)L* . C. B. A,* &-)L ( &-* ( +G1 . G#A)L* . G#B)L* . C. B. A*,* &.)L ( &.* ( +G1 . G#A)L* . G#B)L* . C. B*. A,* &/)L ( &/* ( +G1 . G#A)L* . G#B)L* . C. B*. A*,* &$)L ( &$* ( +G1 . G#A)L* . G#B)L* . C*. B. A,* &#)L ( &#* ( +G1 . G#A)L* . G#B)L* . C*. B. A*,* &1)L ( &1* ( +G1 . G#A)L* . G#B)L* . C*. B*. A,* &0)L ( &0* ( +G1 . G#A)L* . G#B)L* . C*. B*. A*,* ". Draw the logic diagra3 and verify design correctness

-3'

E-CAD LAB

II PIN DIAGRAM OF IC74(38: The a1ove logic diagra3 can 1e re0resented using co33ercially availa1le *+ & $'3- as shown:

The & $'3- has active%low out0uts. and it has three ena1le in0uts :G'. 5G2A. 5G27<. all of which 3ust 1e asserted for the selected out0ut to 1e asserted. The logic function of the 2'3- is straightforwardJan out0ut is asserted if and only if the decoder is ena1led and the out0ut is selected. III VERIFICATION USING SOFTWARE: -32

E-CAD LAB

VHDL CODE: --Behavioral model li1rary *###8 use *###.std9logic9''" .all8 entity decoder3(- is 0ort : g' : in ;TD9LOG*+8--g1, g2a_l, g2b_l cascade i ps g2a9l : in ;TD9LOG*+8 g219l : in ;TD9LOG*+8 a : in ;TD9LOG*+9B#+TOR :2 downto ,<8 y9l : out ;TD9LOG*+9B#+TOR :, to &< <8 end decoder3(-8 architecture deco3- of decoder3(- is 1egin 0rocess :a.g'.g2a9l.g219l< 1egin if :g' and not g2a9l and not g219l<?@'@then if a >? K,,,Kthen y9l>? K,'''''''K8 elsif a >? K,,'Kthen y9l >? K',''''''K8 elsif a >? K,',Kthen y9l>? K'','''''K8 elsif a >? K,''Kthen y9l >? K''',''''K8 elsif a >? K',,Kthen y9l >? K'''','''K8 elsif a >? K','Kthen y9l >? K''''',''K8 elsif a >? K'',Kthen y9l >? K'''''','K8 elsif a >? K'''Kthen y9l >? K''''''',K8 else y9 l>? K''''''''K8 end if8 else y9l >? K''''''''K8 end if8 end 0rocess8 end deco3-8 --Data flow model li1rary *###8 use *###.std9logic9''" .all8 entity B& $'3- is 0ort :G'. G2A9L. G279L: in ;TD9LOG*+8 %% ena1le in0uts A: in ;TD9LOG*+9B#+TOR :2 downto ,<8 %% select in0uts H9L: out ;TD9LOG*+9B#+TOR :, to &< <8 %% decoded out0uts -33

E-CAD LAB end B& $'3-8 architecture B& $'3-9a of B& $'3- is signal H9L9i: ;TD9LOG*+9B#+TOR :, to &<8 1egin with A select H9L9i >? K,'''''''K when K,,,K. K',''''''K when K,,'K. K'','''''K when K,',K. K''',''''K when K,''K. K'''','''K when K',,K. K''''',''K when K','K. K'''''','K when K'',K. K''''''',K when K'''K. K''''''''K when others8 H9L >? H9L9i when :G' and not G2A9L and not G279L<?@'@ else K''''''''K8 end B& $'3-9a8

PROCEDURE:

'. O0en (ilin$ /roAect Navigator 2. O0en New /roAect 3. ;elect Target Device details . #nter BCDL /rogra3 !. +o30ile for ;ynta$ errors ". ;i3ulate design using Dodel ;i3 &. Berify the functionality of design with e$0ected results -. ;ynthesi6e design using (;T :(ilin$ ;ynthesis Tool< ). Erite Fser +onstrain Gile to fi$ in5out 0orts on Target device ',. Generate 0rogra33ing file ''. Down load design to the target device on G/GA5+/LD de3o 1oard -3

E-CAD LAB '2. Berify the functionality of design with e$0ected results WAVEFORMS:

3. %x1 MULTIPLE"ER *+& '!' AIM: To Design the -$' Dulti0le$er and verify the functionality using software and hardware. APPARATUS: '. (ilin$ ise ).2i 2. Digital *+%& '33. /ower cards. interfacing cards DESIGN PROCEDURE: '.Def:A 3ulti0le$eris a digital switchJit connects data fro3 one of n sources to its n out0ut. There are s in0uts that select a3ong the n sources. so s?log2 . An ena1le in0ut #N allows the 3ulti0le$er to Ldo its thingM8 when #N ? ,. all of the out0uts are ,. A 3ulti0le$er is often called a 3u$ for short. 2.Deter3ine the re4uired nu31er of in0ut and out0ut fro3 s0ecification Nu31er of in0uts: -8 #na1le *n0uts:'.;election lines:3 Nu31er of out0uts: 2 -3!

E-CAD LAB

3. Assign a sy31ol to each in0ut5out0ut ;election *n0uts : A.7.+ 8 Data *n0uts : D,.D'.D2.D3.D .D!.D".D& Out0uts : H.H@ . Derive the truth ta1le fro3 the re4uired relationshi0

!. O1tain the si30lified 7oolean functions ". Draw the logic diagra3 and verify design correctness

-3"

E-CAD LAB

II PIN DIAGRAM OF IC74()(: The a1ove logic diagra3 can 1e re0resented using co33ercially availa1le *+ & $'!' as shown:

-3&

E-CAD LAB

The & $'!'. selects a3ong eight '%1it in0uts. The select in0uts are na3ed +. 7. and A. where +is 3ost significant nu3erically. The ena1le in0ut #N9L is active low81oth active%high :H< and active%low :H9L< versions of the out0ut are 0rovided. III VERIFICATION USING SOFTWARE: VHDL CODE: ---Behavioral model li1rary *###8 use *###.std9logic9''" .all8 entity 3u$'!' is 0ort : * :in ;TD9LOG*+9B#+TOR :& downto ,<8 --! i p lines ; :in ;TD9LOG*+9B#+TOR :2 downto ,<8 --" data select lines en9l:in ;TD9LOG*+8 --active low enable i p y :out ;TD9LOG*+ --output line <8 end 3u$'!'8

architecture 3u$'!' of 3u$'!' is 1egin 0rocess :*.s.en9l< 1egin -3-

E-CAD LAB if en9l?@,@ then case s is when K,,,K ?N y >? *:,<8 when K,,'K ?N y >? *:'<8 when K,',K ?N y >? *:2<8 when K,''K ?N y >? *:3<8 when K',,K ?N y >? *: <8 when K','K ?N y >? *:!<8 when K'',K ?N y >? *:"<8 when K'''K ?N y >? *:&<8 when others?Nnull8 end case8 else y >? @,@8 --#$% when en_l$1 end if8 end 0rocess8 end 3u$'!'8 -----------Data&low 'odel li1rary *###8 use *###.std9logic9''" .all8 entity 3u$-$' is 0ort : ;: in ;TD9LOG*+9B#+TOR :2 downto ,<8 A: in ;TD9LOG*+9B#+TOR :& downto ,<8 H: out ;TD9LOG*+ <8 end 3u$-$'8 architecture 3u$-$'d of 3u$-$' is 1egin with ; select H >? A:,< when K,,,K. A:'< when K,,'K. A:2< when K,',K. A:3< when K,''K. A: < when K',,K. A:!< when K','K. A:"< when K'',K. A:&< when K'''K. :others ?N @F@< when others8 %% -%1it vector of @F@ end 3u$-('d8
PROCEDURE:

'. O0en (ilin$ /roAect Navigator 2. O0en New /roAect -3)

E-CAD LAB 3. ;elect Target Device details . #nter BCDL /rogra3 !. +o30ile for ;ynta$ errors ". ;i3ulate design using Dodel ;i3 &. Berify the functionality of design with e$0ected results -. ;ynthesi6e design using (;T :(ilin$ ;ynthesis Tool< ). Erite Fser +onstrain Gile to fi$ in5out 0orts on Target device ',. Generate 0rogra33ing file ''. Down load design to the target device on G/GA5+/LD de3o 1oard '2. Berify the functionality of design with e$0ected results

WAVEFORMS:

-,

E-CAD LAB

. #x/ D!MULTIPLE"ER *+& '!! AIM: To Design the 2$ DeDulti0le$er and verify the functionality using software and hardware. -'

E-CAD LAB APPARATUS: '. (ilin$ ise ).2i 2. Digital *+%& '33. /ower cards. interfacing cards DESIGN PROCEDURE: '.Def: The de3ulti0le$er is the inverse of the 3ulti0le$er. in that it taIes a single data in0ut and n address in0uts. *t has 2n out0uts. The address in0ut

deter3ine which data out0ut is going to have the sa3e value as the data in0ut. The other data out0uts will have the value 0
2.Deter3ine the re4uired nu31er of in0ut and out0ut fro3 s0ecification Data *n0ut:'8 #na1le *n0uts:'.;election lines:2 Nu31er of out0uts: 3. Assign a sy31ol to each in0ut5out0ut ;election *n0uts : A.7 8 Data *n0uts : '+ 8 #na1le *n0ut:'G Out0uts : 'H,.'H'.'H2.'H3 . Derive the truth ta1le fro3 the re4uired relationshi0

!. O1tain the si30lified 7oolean functions

-2

E-CAD LAB

". Draw the logic diagra3 and verify design correctness

II PIN DIAGRAM OF IC74()): The a1ove logic diagra3 can 1e re0resented using co33ercially availa1le *+ & $'!! as shown: -3

E-CAD LAB

III VERIFICATION USING SOFTWARE: VHDL CODE:

--

E-CAD LAB

PROCEDURE:

'. O0en (ilin$ /roAect Navigator 2. O0en New /roAect -!

E-CAD LAB 3. ;elect Target Device details . #nter BCDL /rogra3 !. +o30ile for ;ynta$ errors ". ;i3ulate design using Dodel ;i3 &. Berify the functionality of design with e$0ected results -. ;ynthesi6e design using (;T :(ilin$ ;ynthesis Tool< ). Erite Fser +onstrain Gile to fi$ in5out 0orts on Target device ',. Generate 0rogra33ing file ''. Down load design to the target device on G/GA5+/LD de3o 1oard '2. Berify the functionality of design with e$0ected results

/.IC '/x%. 1 /-BIT COMPARATOR AIM: To Design the %1it co30arator and verify the functionality using software and hardware. -"

E-CAD LAB APPARATUS: '. (ilin$ ise ).2i 2. Digital *+%& '33. /ower cards. interfacing cards DESIGN PROCEDURE: '.Def: A comparator is a device that compares two values and switches its output to
indicate which is larger.

2.Deter3ine the re4uired nu31er of in0ut and out0ut fro3 s0ecification +ascading in0uts: 38Nu31er of in0uts:2 +ascading out0uts: 3 3. Assign a sy31ol to each in0ut5out0ut +ascading in0uts:AGT7*N.A#O7*N.ALT7*N 8 /ri3ary *n0uts:A.7 +ascading out0uts: AGT7OFT.A#O7OFT.ALT7OFT . Derive the truth ta1le fro3 the re4uired relationshi0 /resent in0ut condition AN7 A?7 A>7 " " " 1 0 0 0 1 0 0 0 1 " " "

;.No. 1 # $

+ascade in0uts AGTBIN(1 AE2BIN(1 ALTBIN(1

AGT7OFT 1 1 0 0 0

A#O7OFT 0 0 1 0 0

ALT7OFT 0 0 0 1 1

!. O1tain the si30lified 7oolean functions

". Draw the logic diagra3 and verify design correctness

-&

E-CAD LAB

II PIN DIAGRAM OF IC748): The a1ove logic diagra3 can 1e re0resented using co33ercially availa1le *+ & $-! as shown:

III VERIFICATION USING SOFTWARE: VHDL CODE: li1rary *###8 --

E-CAD LAB use *###.std9logic9''" .all8 entity co30 is 0ort : alt1in: in ;TD9LOG*+8 ae41in: in ;TD9LOG*+8 agt1in: in ;TD9LOG*+8 a: in ;TD9LOG*+9B#+TOR :3 downto ,<8 1: in ;TD9LOG*+9B#+TOR :3 downto ,<8 agt1out: out ;TD9LOG*+8 ae41out: out ;TD9LOG*+8 alt1out: out ;TD9LOG*+ <8 end co308 architecture co30 of co30 is 1egin 0rocess:a.1.agt1in.ae41in.alt1in< 1egin agt1out>?@,@8 --initiali(es the outputs to )%* ae41out>?@,@8 alt1out>?@,@8 if ae41in?@'@ then if a?1 then ae41out>?@'@8 elsif aN1 then agt1out>?@'@8 elsif :a>1< then alt1out>?@'@8 end if8 elsif :alt1in5?agt1in<then agt1out>?agt1in8 alt1out>?alt1in8 end if8 end 0rocess 8 end +o308

PROCEDURE:

'. O0en (ilin$ /roAect Navigator 2. O0en New /roAect 3. ;elect Target Device details -)

E-CAD LAB . #nter BCDL /rogra3 !. +o30ile for ;ynta$ errors ". ;i3ulate design using Dodel ;i3 &. Berify the functionality of design with e$0ected results -. ;ynthesi6e design using (;T :(ilin$ ;ynthesis Tool< ). Erite Fser +onstrain Gile to fi$ in5out 0orts on Target device ',. Generate 0rogra33ing file ''. Down load design to the target device on G/GA5+/LD de3o 1oard '2. Berify the functionality of design with e$0ected results WAVEFORMS:

',.'"(' MULTIPLE"ER

-!,

E-CAD LAB A*D: W34 ! a VHDL 567! 863 IC'/1.0

IC'/'/9A POSITIVE EDGE TRIGGERING D FLIP FLOP AIM: Erite a BCDL code for *+& & Ja 0ositive edge triggering D fli0 flo0. TITLE: *+& & Ja 0ositive edge triggering D fli0 flo0. LOGIC GATE S&MBOL:

-!'

E-CAD LAB

1. State the problem clearly 2. Determine inputs/outputs and assign letters to inputs/outputs Determine state bits and assign letters to the state bits 3. Draw a present state-next state diagram 4. !. using #. orm the state table or each input/output draw the "arnaugh maps ind the simpli$ied expressions $or the inputs/outputs %arnaugh maps &. Draw the logic diagram and implement the circuit 'a connection diagram will be needed i$ the circuit is to be hardwired(

CIRCUIT DIAGRAM:

-!2

E-CAD LAB

TRUTH TABLE: clr9l , , ' ' ' 0r9l , ' , ' ' +lI ( ( ( d ( ( ( , ' 4 ' , ' , ' 4n ' ' , ' ,

VHDL CODE: -!3

E-CAD LAB %%+,D- code for the circuit li1rary *###8 use ieee.std9logic9''" .all8 entity dff is 0ort : 0r9l: in ;TD9LOG*+8 clr9l:in ;TD9LOG*+8 clI :in ;TD9LOG*+8 d :in ;TD9LOG*+8 4 :inout ;TD9LOG*+8 4n :inout ;TD9LOG*+ <8 end dff8 architecture dff of dff is signal e.f.g.h:std9logic8 co30onent nand3 0ort : a.1.c: in ;TD9LOG*+8 d : out ;TD9LOG*+ <8 end co30onent8 1egin g':nand3 0ort 3a0:0r9l.h.f.e<8 g2:nand3 0ort 3a0:clr9l.e.clI.f<8 g3:nand3 0ort 3a0:f.clI.h.g<8 g :nand3 0ort 3a0:g.clr9l.d.h<8 g!:nand3 0ort 3a0:0r9l.f.4n.4<8 g":nand3 0ort 3a0:4.g.clr9l.4n<8 end dff8

-- active low preset input -- active low clear input -- cloc. input -- D input -- output of D flip flop -- inverted output

-- creates g1 gate -- creates g2 gate -- creates g" gate -- creates g/ gate -- creates g0 gate -- creates g1 gate

--+,D- code for " i p nand gate li1rary *###8 use *###.std9logic9''" .all8 entity nand3 is 0ort : a.1.c: in ;TD9LOG*+8 d : out ;TD9LOG*+ <8 end nand38 architecture PnandP of nand3 is 1egin d>? not :a and 1 and c<8 -- creates a " i p nand gate end PnandP8 -!

E-CAD LAB -- Beh !"#$ % &#'e% li1rary *###8 use *###.std9logic9''" .all8 entity Bdff& is 0ort :D. +LQ. /R9L. +LR9L: in ;TD9LOG*+8 O. ON: out ;TD9LOG*+ <8 end Bdff& 8 architecture Bdff& 91 of Bdff& is signal /R. +LR: ;TD9LOG*+8 1egin 0rocess:+LR9L. +LR. /R9L. /R. +LQ< 1egin /R >? not /R9L8 +LR >? not +LR9L8 if :+LR and /R< ? @'@ then O >? @,@8 ON >? @,@8 elsif +LR ? @'@ then O >? @,@8 ON >? @'@8 elsif /R ? @'@ then O >? @'@8 ON >? @,@8 elsif :+LQ@event and +LQ?@'@< then O >? D8 ON >? not D8 end if8 end 0rocess8 end Bdff& 918 WAVEFORMS: D FLIPFLOP

NAND GATE -!!

E-CAD LAB

B*BA OF#;T*ON;: '. Erite the 1ehavioral code for the *+ & $& . 2. Erite the dataflow code for the *+ & $& . 3. Ehat is the difference 1etween se4uential and co31inational circuitR . Ehat is a fli0%flo0R !. #$0lain the functions of 0reset and clear in0uts in fli0%flo0R ". Ehat is 3eant 1y a clocIed fli0%flo0R &. Ehat is 3eant 1y e$citation ta1leR -. Ehat is the difference 1etween fli0%flo0 and latchR ). Ehat are the various 3ethods used for triggering fli0%flo0sR ',. #$0lain level triggered fli0%flo0R ''. Erite the 1ehavioral code for *+ & (& . '2. Erite the synta$ of *G state3entR

$.IC '/x:0 1 DECADE COUNTER -!"

E-CAD LAB

A*D:To write the BCDL code for *+ & $), S decade counter. LOG*+ ;HD7OL:

+*R+F*T D*AGRAD OG *+ & $),:

TRFTC TA7L#:

-!&

E-CAD LAB

BCDL +OD#: --2o wor. as a decade counter li1rary *###8 Fse *###.std9logic9''" .all8 entity count is 0ort : ;,. s'. r,. r': in ;TD9LOG*+8 +lI,: in ;TD9LOG*+8 +lI': inout ;TD9LOG*+8 --set and reset i ps for mod2 and -- 'od0 counters --Cloc. signal for mod2 counter --Cloc. signal for mod0 counter

4 : inout ;TD9LOG*+9B#+TOR:3 downto ,< --o p of -- mod2 3 mod0$ mod1% <8 end count8

architecture count of count is co30onent AI9ff -- 4. flip flop instantiation -!-

E-CAD LAB

0ort : AI : in ;TD9LOG*+9B#+TOR:' downto ,<8 clI.0r9l.clr9l : in ;TD9LOG*+8 4.n4 : inout ;TD9LOG*+ <8 end co30onent8 signal 0reset.clear.;. 431ar:;TD9LOG*+8 1egin 0reset >? s, nand s'8 clear >?r, nand r'8 ;>?4:2< and 4:'<8 431ar >? not 4:3<8 clI'>?4:,<8 -- common preset inputs for mod2 and mod0 counters -- common reset inputs for mod2 and mod0 counters -- to set the last flip flop -- complemented output of 56"7 --to wor. as as#nchronous mod1% counter

AI':AI9ff 0ort 3a0:K''K.clI,.0reset.clear.4:,<.o0en<8 AI2:AI9ff 0ort 3a0:AI:'<?N 431ar. AI:,<?N@'@. clI?NclI'. 0r9l?N0reset. clr9l?Nclear. 4?N4:'<. n4?No0en<8 -- 4.184.2,4.",4./ create four 9: flip flops AI3:AI9ff 0ort 3a0:K''K.4:'<.0reset.clear.4:2<.o0en<8 AI :AI9ff 0ort 3a0:AI:,<?N4:3<. AI:'<?Ns. clI?NclI'. 0r9l?N0reset. clr9l?Nclear. 4?N4:3<. n4?N 431ar<8 end count8

EAB#GORD;: -!)

E-CAD LAB

--;rogram for 9: flip-flop li1rary *###8 use *###.std9logic9''" .all8 entity AI9ff is 0ort : AI

: in ;TD9LOG*+9B#+TOR:' downto ,<8 --4.617$9<4.6%7$:< clI.0r9l.clr9l : in ;TD9LOG*+8 4.n4 : inout ;TD9LOG*+ <8 end AI9ff8

architecture AI of AI9ff is -",

E-CAD LAB 1egin 0rocess:clI.0r9l.clr9l.AI< varia1le te30:std9logic:?@,@8 1egin 4>?@,@8n4>?@'@8 if :0r9l?@'@ and clr9l?@,@< then 4>?@,@8n4>?@'@8 elsif :0r9l?@,@ and clr9l ?@'@< then 4>?@'@8n4>?@,@8 elsif :0r9l?@'@ and clr9l?@'@< then if :clI @event and clI?@,@< then --performs during the falling edge of cloc. case AI is when K,,K?Nte30:?te308 when K,'K?Nte30:?@,@8 when K',K?Nte30:?@'@8 when K''K?Nte30:?not te308 when others?Nnull8 end case8 end if8 4>?te308 n4>? not te308 end if8 end 0rocess8 end AI8

-"'

E-CAD LAB WAVEFORMS:

VIVA 2UESTIONS: '.Erite the 1ehavioral code for *+ & $),. '.Ehat is a se4uential circuitR 2.Differentiate 1etween synchronous and asynchronous counterR 3.Cow 3any no.of fli0%flo0s are re4uired for decade counterR .Ehat is 3eant 1y e$citation ta1leR !.Ehat are the 3eanings of different ty0es of values in std9ulogicR ".Ehat are the o1Aects in BCDLR &.Erite the synta$ for a signalR -.Erite the difference 1etween signal and varia1leR ).#$0lain a1out enu3eration ty0esR ',.*f the 3odulus of a counter is '2 how 3any fli0%flo0s are re4uiredR

-"2

E-CAD LAB /.IC '/x:$ 1 / -BIT BINAR& COUNTER AIM:To write the BCDL code for *+ & $)3 S LOGIC S&MOL: %1it 1inary counter.

TRUTH TABLE: -"3

E-CAD LAB

O:3< , , , , , , , , ' ' ' ' ' ' ' '

OUTPUT O:2< O:'< , , , , , ' , ' ' , ' , ' ' ' ' , , , , , ' , ' ' , ' , ' ' ' '

O:,< , ' , ' , ' , ' , ' , ' , ' , '

CIRCUIT DIAGRAM OF IC'/":$:

VHDL CODE: -"

E-CAD LAB

--;rogram for /-bit counter li1rary *###8 use *###.std9logic9''" .all8 entity cnt is 0ort : clI,: in ;TD9LOG*+8 3r,: in ;TD9LOG*+8 3r': in ;TD9LOG*+8 clI': inout ;TD9LOG*+8 O:inout ;TD9LOG*+9B#+TOR:3 downto ,< <8 end cnt8 architecture cnt of cnt is +o30onent tff -- 2- flip flop instantiation 0ort : t : in ;TD9LOG*+8 clI : in ;TD9LOG*+8 clr9l : in ;TD9LOG*+8 4.n4 : out ;TD9LOG*+ <8 end co30onent8 signal clear : std9logic8 1egin clear>? 3r, nand 3r'8 -- common reset inputs for mod2 and mod! --counters +LQ'>?4:,<8 --to wor. as as#nchronous mod11 counter t':tff 0ort 3a0:@'@.clI,.clear.O:,<.o0en<8--t1,t2,t",t/ create four 2-flip flops t2:tff 0ort 3a0:@'@.clI'.clear.O:'<. o0en<8 t3:tff 0ort 3a0:@'@.O:'<.clear.O:2<. o0en<8 t :tff 0ort 3a0:@'@.O:2<.clear.O:3<. o0en<8 end cnt8

WAVEFORMS: -"!

E-CAD LAB

--;rogram for 2 flip-flop li1rary *###8 use *###.std9logic9''" .all8 entity tff is 0ort : t : in ;TD9LOG*+8--input to the 2-flip flop clI : in ;TD9LOG*+8--Cloc. signal for 2-flip flop clr9l : in ;TD9LOG*+8--active low clear input 4.n4 : out ;TD9LOG*+--actual and complemented outputs of 2-flip flop <8 end tff8 architecture tff of tff is 1egin 0rocess:t.clI.clr9l< varia1le te30:;TD9LOG*+:?@,@8 1egin if :clr9l?@,@< then te30:?@,@8 elsif ::clr9l?@'@< and :clI@event and clI?@,@<< then--perfoms during falling edge if : t?@,@< then te30:?te308 else te30:? not te308 end if8 end if8 4>? te308 -""

E-CAD LAB n4>? not te308 end 0rocess8 end tff8 WAVEFORMS:

VIVA 2UESTIONS: '. Erite the 1ehavioral code for *+ & $)3. 2. Ehat is the difference 1etween decade counter and 1it counterR 3. Ehat is 3eant 1y a 3odulus of a counterR . Erite the 1ehavioral code for *+& ()3R !. #$0lain the o0eration of *+& ()3R ". Erite the synta$ for co30onent instantiationR &. Ehat is netlistR -. 7riefly e$0lain a1out genericsR ). Erite the difference 1etween se4uential state3ent and concurrent state3entR ',. Erite the synta$ for loo0 state3entsR ''. Erite the synta$ for generate state3entsR '2. Erite the differences 1etween loo0 and generateR

..IC '/x:. 1 SHIFT REGISTER AIM:To write the structural 0rogra3 for *+ & $)! S ;C*GT R#G*;T#R. -"&

E-CAD LAB

TRUTH TABLE: 3ode control , clocI clI, function S!34a; 6<!3a 46= 4:2< to 4:3<. 4:'< to 4:2<. 4:,< to 4:'<. si to 4:,< /arallel o0eration A to 4:,< 7 to 4:'< + to 4:2< D to 4:3<

'

clI'

CIRCUIT DIAGRAM OF IC '/":.:

VHDL CODE: --Structural model --;rogram for shift register li1rary *###8 -"-

E-CAD LAB use *###.std9logic9''" .all8 entity shift9reg is 0ort : a.1.c.d: in ;TD9LOG*+8 --four parallel inputs si : in ;TD9LOG*+8 --one serial input 3 : in ;TD9LOG*+8 --mode control clI, :in ;TD9LOG*+8 --cloc. for serial input clI' :in ;TD9LOG*+8 --cloc. for parallel input 4 :inout ;TD9LOG*+9B#+TOR :3 downto ,<--/-bit output <8 end shift9reg8 architecture shift9reg of shift9reg is co30onent 3u$ -- multiple=er instantiation 0ort : a.1.c.d: in ;TD9LOG*+8 6 : out ;TD9LOG*+ <8 end co30onent 8 co30onent dff -- D- flip flop instantiation 0ort : d.clI: in ;TD9LOG*+8 4 : out ;TD9LOG*+ <8 end co30onent8 signal n3.c,.do.d'.d2.d3:;TD9LOG*+8 1egin n3>? not 38 g':3u$ 0ort 3a0:clI,.n3.clI'.3.c,<8 --to select the cloc. based on mode -- control g2:3u$ 0ort 3a0:si.n3.a.3.do,> --g2,g",g/,g0 are used to select g3:3u$ 0ort 3a0:4:,<.n3.1.3.d'<8 --either serial input or parallel input g :3u$ 0ort 3a0:4:'<.n3.c.3.d2<8 --based on mode control g!:3u$ 0ort 3a0:4:2<.n3.d.3.d3<8 d'':dff 0ort 3a0:do.c,.4:,<<8 --d11,d12,d1",d1/ creates four D flip flops d'2:dff 0ort 3a0:d'.c,.4:'<<8 --to perform either serial or parallel shift d'3:dff 0ort 3a0:d2.c,.4:2<<8 -- operations d' :dff 0ort 3a0:d3.c,.4:3<<8 end shift9reg8 WAVEFORMS:

-")

E-CAD LAB

IC '/x1:/ 1UNIVERSAL SHIFT REGISTER --program for D-flip-flop li1rary *###8 use *###.std9logic9''" .all8 entity dff is 0ort : d.clI: in ;TD9LOG*+8 4 : out ;TD9LOG*+ <8 end dff8 architecture dff of dff is 1egin 0rocess:clI< 1egin if: clI@event and clI?@,@< then 4>?d8 else null8 end if8 end 0rocess8 end dff8

--performs during falling edge

WAVEFORMS:

-&,

E-CAD LAB

--;rogram for multiple=er li1rary ieee8 use ieee.std9logic9''" .all8 entity 3u$ is 0ort : a.1.c.d: in ;TD9LOG*+8 6 : out ;TD9LOG*+ <8 end 3u$8 architecture 3u$ of 3u$ is 1egin 6>?::a and 1< or :c and d<<8 end 3u$8

WAVEFORMS:

B*BA OF#;T*ON;: '. Erite the 1ehavioral code for *+ & $)!. 2. Ehat is a shift registerR -&'

E-CAD LAB 3. Erite so3e a00lications of shift registerR . #$0lain 1riefly a1out 7LO+QR !. Erite the synta$ for functionR ". Erite the synta$ for 0rocedureR &. Cow to define varia1le in BCDLR -. Erite the synta$ for +A;# state3entR ). Ehat is the advantage of case state3ent over if%else state3entR ',. Erite the difference 1etween with%select and when%else state3entR

-.IC '/x1:/ 1UNIVERSAL SHIFT REGISTER AIM: To write the BCDL code for *+ & $') Suniversal shift register. -&2

E-CAD LAB

BLOC? DIAGRAM:

TRUTH TABLE: C;3); , ' ' ' ' ;:'< ( , , ' ' ;:,< ( , ' , ' C;@ ( OA <A 8A=5 46= ' no change shift right : dsr to 4:,<< shift left : dsl to 4:3<< load data :0arallel shifting<

VHDL 567!: li1rary *###8 use *###.std9logic9''" .all8 -&3

E-CAD LAB entity shift') is 0ort : clI : in ;TD9LOG*+8--Cloc. signal dsr.dsl : in ;TD9LOG*+8--serial input for right shift and left shift --operation clr9l : in ;TD9LOG*+8--active low clear input ;:in ;TD9LOG*+9B#+TOR:' downto ,<8--mode control bits d: in ;TD9LOG*+9B#+TOR :3 downto ,<8--four parallel input bits 4: inout ;TD9LOG*+9B#+TOR :3 downto ,< --/-bit output <8 end shift') 8 architecture shift') of shift') is 1egin 0rocess:clI.s.clr9l< 1egin if clr9l?@,@ then 4>?:others?N@,@<8 elsif clr9l?@'@ then if:clI@event and clI?@'@< then case s is whenK,,K ?N4>?48--*# +h *,e whenK,'K?N4>?4:2 downto ,< T dsr8--shift right6dsr to 56%77 whenK',K ?N4>?dsl T 4:3 downto '<8--shift left6dsl to 56"77 whenK''K ?N4>?d:3< T d:2< T d:'< T d:,<8--parallel operation --d6"7 to 56"7,d627 to 5627,d617 to 5617,d6%7 to 56%7 when others?Nnull8 end case8 end if8 end if8 end 0rocess8 end shift') 8

WAVEFORMS:

-&

E-CAD LAB

-&!

E-CAD LAB '.

%.

B*BA OF#;T*ON;: '. Erite the dataflow 3odel for the *+ & $-!. 2. Erite the BCDL code for the *+ & $-! using +A;# state3ent. 3. Erite the BCDL code for the *+ & $-! using E*TC state3ent. . Erite the BCDL code for the *+ & $-! using EC#N%%#L;# state3ent. !. Erite the structural 0rogra3 for *+ & $-!. ". Cow 3any %1it co30arators are needed to construct '2%1it co30aratorR &. Ehat does a digital co30arator 3eanR -. Design a 2%1it co30arator using gatesR ). #$0lain the 0hases of a si3ulationR ',. #$0lain 1riefly a1out wait state3entR :.%x1 MULTIPLE"ER AIM: Erite a BCDL code for *+& '!'J-$' 3ulti0le$er. TITLE: *+& '!'J-$' 3ulti0le$er. BLOC? DIAGRAM:

-&"

E-CAD LAB

TRUTH TABLE:

LOGIC DIGRAM:

-&&

E-CAD LAB

VHDL CODE: li1rary *###8 use *###.std9logic9''" .all8 -&-

E-CAD LAB

entity 3u$'!' is 0ort : * :in ;TD9LOG*+9B#+TOR :& downto ,<8 --! i p lines ; :in ;TD9LOG*+9B#+TOR :2 downto ,<8 --" data select lines en9l:in ;TD9LOG*+8 --active low enable i p y :out ;TD9LOG*+ --output line <8 end 3u$'!'8 architecture 3u$'!' of 3u$'!' is 1egin 0rocess :*.s.en9l< 1egin if en9l?@,@ then case s is when K,,,K ?N y >? *:,<8 when K,,'K ?N y >? *:'<8 when K,',K ?N y >? *:2<8 when K,''K ?N y >? *:3<8 when K',,K ?N y >? *: <8 when K','K ?N y >? *:!<8 when K'',K ?N y >? *:"<8 when K'''K ?N y >? *:&<8 when others?Nnull8 end case8 else y >? @,@8 --#$% when en_l$1 end if8 end 0rocess8 end 3u$'!'8

WAVEFORMS:

-&)

E-CAD LAB

B*BA OF#;T*ON; : '. Erite the 1ehavioral code for the *+ & $'!'. 2. Erite the BCDL code for the *+ & $'!' using *G state3ent. 3. Erite the BCDL code for the *+ & $'!' using E*TC state3ent. . Erite the BCDL code for the *+ & $'!' using EC#N%%#L;# state3ent. !. Erite the structural 0rogra3 for *+ & $'!'. ". Ehat is 3eant 1y 3ulti0le$erR &. Ehat does de3ulti0le$er 3eanR -. Cow 3any -(' 3ulti0le$ers are needed to construct '"(' 3ulti0le$erR ). +o30are decoder with de3ulti0le$erR ',. Design a full adder using -(' 3ulti0le$erR ''. Ehat are the two Iinds of su10rogra3sR '2. Ehat are the difference 1etween function and 0rocedureR '3. #$0lain 1riefly a1out su10rogra3 overloadingR 10.1-"1 MULTIPLE"ER AIM: Erite a BCDL code for *+& '!,J'"$' 3ulti0le$er. --,

E-CAD LAB

TITLE: *+& '!,J'"$' 3ulti0le$er. BLOC? DIAGRAM:

TRUTH TABLE:

--'

E-CAD LAB ;.No. ' 2 3 ! " & ) ', '' '2 '3 ' '! '" '& stro1e , , , , , , , , , , , , , , , , ' A , , , , , , , , ' ' ' ' ' ' ' ' ( Data select lines B C , , , , , ' , ' ' , ' , ' ' ' ' , , , , , ' , ' ' , ' , ' ' ' ' ( ( out0ut & d2:,< d2:'< d2:2< d2:3< d2: < d2:!< d2:"< d2:&< d2:-< d2:)< d2:',< d2:''< d2:'2< d2:'3< d2:' < d2:'!< '

D , ' , ' , ' , ' , ' , ' , ' , ' (

VHDL CODE: li1rary *###8 use *###.std9logic9''" .all8 entity 3u$'" is 0ort: stro1e : in ;TD9LOG*+8 --active low enable i p D : in ;TD9LOG*+9B#+TOR:'! downto ,<8 --11 i p lines ;el : in ;TD9LOG*+9B#+TOR:3 downto ,<8 --/ data select lines H : out ;TD9LOG*+ --output line <8 end 3u$'"8

architecture 3u$'" of 3u$'" is signal H9L:std9logic8 1egin --2

E-CAD LAB with ;el select H9L >? D:,< when K,,,,K. D:'< when K,,,'K. D:2< when K,,',K. D:3< when K,,''K. D: < when K,',,K. D:!< when K,','K. D:"< when K,'',K. D:&< when K,'''K. D:-< when K',,,K. D:)< when K',,'K. D:',< when K',',K. D:''< when K',''K. D:'2< when K'',,K. D:'3< when K'','K. D:' < when K''',K. D:'!< when K''''K. unaffected when others8 H>? not H9L when :stro1e?@,@< else @'@8 end 3u$'"8

WAVEFORMS:

--3

E-CAD LAB

B*BA OF#;T*ON;: '. Erite the 1ehavioral code for the *+ & $'!,. 2. Erite the BCDL code for the *+ & $'!, using *G state3ent. 3. Erite the BCDL code for the *+ & $'!, using +A;# state3ent. . Erite the BCDL code for the *+ & $'!, using EC#N%%#L;# state3ent. !. Erite the structural 0rogra3 for *+ & $'!,. ". *30le3ent '"(' 3ulti0le$er using structural 3odelR &. Erite the a00lications of 3ulti0le$er and de3ulti0le$erR -. Design 32(' 3ulti0le$er using '"(' 3ulti0le$erR ). #$0lain 1riefly a1out o0erator overloadingR ',. #$0lain the e$ecution ste0s of su10rogra3R ''. Erite the synta$ of 0acIage declarationR '2. Erite the synta$ of 0acIage 1odyR 11.IC '/"1%:9READ AND WRITE OPERATIONS OF RAM

--

E-CAD LAB AIM: T6 B34 ! C! VHDL 567! 863 IC '/"1%:93!a7 a=7 B34 ! 6<!3a 46=D 68 RAM. 7LO+Q D*AGRAD:

TRUTH TABLE:

en9l rw , , , ' ' (

o0eration Erite Read the co30le3ented data *nhi1it

VHDL 567!: --!

E-CAD LAB li1rary *###8 use *###.std9logic9''" .all8 entity ra3 is 0ort : rw : in ;TD9LOG*+8--read or write enable pin en9l: in ;TD9LOG*+8 --active low enable pin datain: in ;TD9LOG*+9B#+TOR :3 downto ,<8--/-bit input data line addr: in ;TD9LOG*+9B#+TOR :3 downto ,<8 --/-bit address line dataout: out ;TD9LOG*+9B#+TOR :3 downto ,< --/-bit input data line <8 end ra38

architecture ra3 of ra3 is su1ty0e wty0e is ;TD9LOG*+9B#+TOR :3 downto ,<8 ty0e 3e39ty0e is array :'! downto ,< of wty0e8 signal 3e3ory:3e39ty0e8 8--creates 11 memor# locations8>ach location can store --/-bits function conv9integer:$:std9logic9vector< return integer is %%function to convert varia1le result:integer8 --binar# to integer 1egin result:?,8 for i in $@range loo0 if $:i<?2'2 then result:? resultU2VVi8 else null8 end if8 end loo08 return result8 end conv9integer8 1egin 0rocess:en9l.rw.addr< 1egin if:en9l?@,@< then if :rw ?@,@< then ---e$.#$&/ 0$"1e #-e$ 1"#* 3e3ory:conv9integer:addr<<>? datain8--stores the data in the dataout>?K====K8 -- corresponding memor# elsif :rw ?@'@< then %% the output performs read operation dataout>?not 3e3ory:conv9integer:addr<<8--places the data on end if8 -- the given address line else dataout>?:others?N@=@<8 %%output is in inhibit state when en_l$*1*6i8e8,i-- impedence7 end if8 --"

E-CAD LAB end 0rocess8 end ra38 EAB#GORD;:

B*BA OF#;T*ON;: --&

E-CAD LAB '. Erite the 1ehavioral code for *+ & $'-) without declaring the function. 2. #$0lain a1out different ty0es of RADsR 3. Cow to s0ecify the 3e3ory si6eR . #$0lain read and write o0erationsR !. Ehat are the differences 1etween RAD and RADR ". #$0lain the ste0s of a co30ilation 0rocess of a BCDL 0rogra3R &. #$0lain the ty0es of design unitsR -. Ehy configurations are neededR ). Ehat is 1indingR ',. Ehat is su10rogra3 in vhdl

---