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INA

121

INA121

INA

121

FET-Input, Low Power INSTRUMENTATION AMPLIFIER


FEATURES
G LOW BIAS CURRENT: 4pA G LOW QUIESCENT CURRENT: 450A G LOW INPUT OFFSET VOLTAGE: 200V G LOW INPUT OFFSET DRIFT: 2V/C G LOW INPUT NOISE: 20nV/Hz at f = 1kHz (G =100) G HIGH CMR: 106dB G WIDE SUPPLY RANGE: 2.25V to 18V G LOW NONLINEARITY ERROR: 0.001% max G INPUT PROTECTION TO 40V G 8-PIN DIP AND SO-8 SURFACE MOUNT

DESCRIPTION
The INA121 is a FET-input, low power instrumentation amplifier offering excellent accuracy. Its versatile three-op amp design and very small size make it ideal for a variety of general purpose applications. Low bias current (4pA) allows use with high impedance sources. Gain can be set from 1V to 10,000V/V with a single external resistor. Internal input protection can withstand up to 40V without damage. The INA121 is laser-trimmed for very low offset voltage (200V), low offset drift (2V/C), and high common-mode rejection (106dB at G = 100). It operates on power supplies as low as 2.25V (+4.5V), allowing use in battery operated and single 5V systems. Quiescent current is only 450A. Package options include 8-pin plastic DIP and SO-8 surface mount. All are specified for the 40C to +85C industrial temperature range.

APPLICATIONS
G LOW-LEVEL TRANSDUCER AMPLIFIERS Bridge, RTD, Thermocouple G PHYSIOLOGICAL AMPLIFIERS ECG, EEG, EMG, Respiratory G HIGH IMPEDANCE TRANSDUCERS G CAPACITIVE SENSORS G MULTI-CHANNEL DATA ACQUISITION G PORTABLE, BATTERY OPERATED SYSTEMS G GENERAL PURPOSE INSTRUMENTATION

V+ 7 INA121

VIN

Over-Voltage Protection

A1 40k 25k A3 6 40k

G=1+

50k RG

RG 8 25k A2 40k

VO

5 40k

+ VIN

Over-Voltage Protection

Ref

4 V
International Airport Industrial Park Mailing Address: PO Box 11400, Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111 Twx: 910-952-1111 Internet: http://www.burr-brown.com/ FAXLine: (800) 548-6133 (US/Canada Only) Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132

1997 Burr-Brown Corporation

PDS-1412A 1

INA121

Printed in U.S.A. May, 1998

SBOS078

SPECIFICATIONS: VS = 15V
At TA = +25C, VS = 15V, RL = 10k, and IA reference = 0V, unless otherwise noted. INA121P, U PARAMETER INPUT Offset Voltage, RTI vs Temperature vs Power Supply Long-Term Stability Impedance, Differential Common-Mode Input Voltage Range Safe Input Voltage Common-Mode Rejection CONDITIONS MIN TYP MAX MIN INA121PA, UA TYP MAX UNITS V V/C V/V V/mo || pF || pF V dB dB dB dB 6 pA pA

VS = 2.25V to 18V

VO = 0V

200200/G 500500/G 22/G 520/G 520/G 50150/G 0.5 1012 || 1 1012 || 12 See Text and Typical Curves 40 78 91 96 86 100 106 106 4 See Typical Curve 0.5 See Typical Curve 30 21 20 1 1 1 + (50k/RG) 1 10,000 0.01 0.03 0.05 0.5 1 25 0.0002 0.0015 0.0015 0.002 (V+)0.9 (V)+0.15 (V+)0.9 (V)+0.25 1000 14 600 300 50 5 0.7 20 35 260 5 2.25 15 450 18 525 85 125 125 100 150 6 0.05 0.4 0.5 10 100 0.001 0.005 0.005 6 50 72 85 90

300200/G 10001000/G 6 1520/G 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 0.1 0.5 0.7 6 6 0.002 0.008 0.008

VCM = 12.5V to 13.5V G=1 G = 10 G = 100 G = 1000 VCM = 0V

BIAS CURRENT vs Temperature Offset Current vs Temperature NOISE, RTI Voltage Noise: f = 10Hz f = 100Hz f = 1kHz f = 0.1Hz to 10Hz Current Noise: f = 1kHz GAIN Gain Equation Range of Gain Gain Error

RS = 0 G = 100 G = 100 G = 100 G = 100

nV/Hz nV/Hz nV/Hz Vp-p fA/Hz V/V V/V % % % % ppm/C ppm/C % % % % of of of of FSR FSR FSR FSR

Gain vs Temperature(1) Nonlinearity

VO = 14V to 13.5V G=1 G = 10 G = 100 G = 1000 G=1 G>1 VO = 14V to 13.5V G=1 G = 10 G = 100 G = 1000 RL = 100k RL = 100k RL = 10k RL = 10k

OUTPUT Voltage: Positive Negative Positive Negative Capacitance Load Drive Short-Circuit Current FREQUENCY RESPONSE Bandwidth, 3dB

(V+)1.5 (V)+1

6 6

V V V V pF mA kHz kHz kHz kHz V/s s s s s V A C C C C/W C/W

Slew Rate Settling Time, 0.01%

Overload Recovery POWER SUPPLY Voltage Range Quiescent Current TEMPERATURE RANGE Specification Operating Storage Thermal Resistance, JA 8-Lead DIP SO-8 Surface Mount 6 Specification same as INA121P, U.

G=1 G = 10 G = 100 G = 1000 VO = 10V, G 10 G = 1 to 10 G = 100 G = 1000 50% Input Overload

IO = 0V 40 55 55

6 6 6

NOTE: (1) Temperature coefficient of the Internal Resistor in the gain equation. Does not include TCR of gain-setting resistor, RG.

INA121

PIN CONFIGURATION
Top View 8-Pin DIP and SO-8

ELECTROSTATIC DISCHARGE SENSITIVITY


This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

Top View RG VIN V


+ IN

1 2 3 4

8 7 6 5

RG V+ VO Ref

ABSOLUTE MAXIMUM RATINGS(1)


Supply Voltage .................................................................................. 18V Analog Input Voltage Range ............................................................. 40V Output Short-Circuit (to ground) .............................................. Continuous Operating Temperature ................................................. 55C to +125C Storage Temperature ..................................................... 55C to +125C Junction Temperature .................................................................... +150C Lead Temperature (soldering, 10s) ............................................... +300C NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability.

PACKAGE/ORDERING INFORMATION
PACKAGE DRAWING NUMBER(1) 006 006 182 " 182 " SPECIFIED TEMPERATURE RANGE 40C to +85C 40C to +85C 40C to +85C " 40C to +85C " PACKAGE MARKING INA121P INA121PA INA121U " INA121UA " ORDERING NUMBER(2) INA121P INA121PA INA121U INA121U/2K5 INA121UA INA121UA/2K5 TRANSPORT MEDIA Rails Rails Rails Tape and Reel Rails Tape and Reel

PRODUCT Single INA121P INA121PA INA121U " INA121UA "

PACKAGE 8-Pin DIP 8-Pin DIP SO-8 Surface-Mount " SO-8 Surface-Mount "

NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of INA121U/2K5 will get a single 2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

INA121

TYPICAL PERFORMANCE CURVES


At TA = +25C, VS = 15V, unless otherwise noted.

GAIN vs FREQUENCY 60

COMMON-MODE REJECTION vs FREQUENCY 120

Common-Mode Rejection (dB)

50 40

G = 1000V/V

100 G = 1000V/V 80 G = 100V/V 60 40 20 0

G = 100V/V

Gain (dB)

30 20 10 0 10 20 1k 10k 100k Frequency (Hz) 1M 10M G = 1V/V G = 10V/V

G = 10V/V G = 1V/V 10 100 1k 10k 100k 1M

Frequency (Hz)

POSITIVE POWER SUPPLY REJECTION vs FREQUENCY 120 120

NEGATIVE POWER SUPPLY REJECTION vs FREQUENCY G = 1000V/V G = 100V/V

Power Supply Rejection (dB)

100 80 60 40 20 0 10 100 1k 10k 100k 1M Frequency (Hz) G = 1000V/V G = 100V/V G = 10V/V

Power Supply Rejection (dB)

100 G = 10V/V 80 60 40 20 0 10 100 1k 10k 100k 1M Frequency (Hz) G = 1V/V

G = 1V/V

INPUT COMMON-MODE RANGE vs OUTPUT VOLTAGE, VS = 15V 15


5 4

INPUT COMMON-MODE RANGE vs OUTPUT VOLTAGE, VS = 5V, 2.5V G 10 G=1 G 10


G=1

Common-Mode Voltage (V)

Common-Mode Voltage (V)

10 5 0 5 10 15 15
+ +

3 2 1 0 1 2 3 4 5 VS = 5V VS = 2.5V 5 4 3 2 1 0 1 2 3 4 5

+15V
VO

VD/2 VD/2
+ VCM

Ref 15V

G=1 G 10 10 5 0 5 10 15

Output Voltage (V)

Output Voltage (V)

INA121

TYPICAL PERFORMANCE CURVES


At TA = +25C, VS = 15V, unless otherwise noted.

(CONT)

INPUT BIAS CURRENT vs TEMPERATURE 10k 1k


Bias Current (pA)
Input Bias Current (A)
1m 100 10 10p 1p 10 100

INPUT BIAS CURRENT vs COMMON-MODE INPUT VOLTAGE

100 10 1 0.1 0.01 75 IB IOS

50

25

25

50

75

100

125
1m 20 15 10 5 0 5 10 15 20 Common-Mode Voltage (V)

Temperature (C)

INPUT OVER-VOLTAGE V/I CHARACTERISTICS 1 0.8 0.6


Input Current (mA)

SETTLING TIME vs GAIN 1000

G = 1V/V
Settling Time (s)

0.4 0.2 0 0.2 0.4 0.6 0.8 1

Flat region represents normal linear operation.

G = 1000V/V

0.01% 100 0.1%

+15V G = 1V/V G = 1000V/V VIN IIN 10 15V

10

50 40 30

20 10

20

30

40

50

10 Gain (V/V)

100

1000

Input Voltage (V)

QUIESCENT CURRENT AND SLEW RATE vs TEMPERATURE 500 1.4 15

SHORT-CIRCUIT CURRENT vs TEMPERATURE

Quiescent Current (A)

475 IQ 450

Short-Circuit Current (A)

1.2

14

+ISC

Slew Rate (V/s)

13 ISC 12

425 SR 400

0.8

0.6

11

375 75 50 25 0 25 50 75 100 Temperature (C)

0.4 125

10 75

50

25

25

50

75

100

125

Temperature (C)

INA121

TYPICAL PERFORMANCE CURVES


At TA = +25C, VS = 15V, unless otherwise noted.

(CONT)

OUTPUT VOLTAGE SWING vs OUTPUT CURRENT V+ (V+) 0.3 +85C +25C 40C, 55C +125C

MAXIMUM OUTPUT VOLTAGE vs FREQUENCY 30


Peak-to-Peak Output Voltage (Vp-p)

G = 10 to 100

Output Voltage Swing (V)

(V+) 0.6 (V+) 0.9 (V+) 1.2 (V+) 1.5 (V) +1.5 (V) +1.2 (V) +0.9 (V) +0.6 (V) +0.3 (V) 0 2 4 6 +125C +85C

25 G=1 20 G = 1000 15 10 5 0

+25C 40C, 55C

10

100

1k

10k Frequency (Hz)

100k

1M

Output Current (mA)

INPUT OFFSET VOLTAGE WARM-UP 10 8


Offset Voltage Change (V)
18 16 14 Percent of Units (%) 12 10 8 6 4 2

INPUT OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION Typical production distribution of packaged units.

6 4 2 0 2 4 6 8 10 0 100 200 300 400 Time (s) 500

0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 Offset Voltage Drift (V/C)

INPUT-REFERRED NOISE VOLTAGE vs FREQUENCY 1000

VOLTAGE NOISE 0.1 TO 10Hz INPUT-REFERRED, G 100

Voltage Noise (nV/Hz)

100

G=1

G = 100

10

G = 1000 (BW Limit)

1 1 10 100 Frequency (Hz) 1k 10k

0.5V

G = 10

1s /div

INA121

TYPICAL PERFORMANCE CURVES


At TA = +25C, VS = 15V, unless otherwise noted.

(CONT)

SMALL-SIGNAL STEP RESPONSE (G = 1, 10)

SMALL-SIGNAL STEP RESPONSE (G = 100, 1000)

G=1

G = 100

50mV/div

50mV/div

G = 10

G = 1000

10s/div

100s/div

LARGE-SIGNAL STEP RESPONSE (G = 1, 10)

LARGE-SIGNAL STEP RESPONSE (G = 100, 1000)

G=1

G = 100

5V/div

5V/div

G = 10

G = 1000

100s/div

100s/div

INA121

APPLICATION INFORMATION
Figure 1 shows the basic connections required for operation of the INA121. Applications with noisy or high impedance power supplies may require decoupling capacitors close to the device pins as shown. The output is referred to the output reference (Ref) terminal which is normally grounded. This must be a low-impedance connection to assure good common-mode rejection. A resistance of 8 in series with the Ref pin will cause a typical device to degrade to approximately 80dB CMR (G = 1). SETTING THE GAIN Gain of the INA121 is set by connecting a single external resistor, RG, connected between pins 1 and 8:

The 50k term in Equation 1 comes from the sum of the two internal feedback resistors of A1 and A2. These on-chip metal film resistors are laser trimmed to accurate absolute values. The accuracy and temperature coefficient of these resistors are included in the gain accuracy and drift specifications of the INA121. The stability and temperature drift of the external gain setting resistor, RG, also affects gain. RGs contribution to gain accuracy and drift can be directly inferred from the gain equation (1). Low resistor values required for high gain can make wiring resistance important. Sockets add to the wiring resistance which will contribute additional gain error (possibly an unstable gain error) in gains of approximately 100 or greater. DYNAMIC PERFORMANCE The typical performance curve Gain vs Frequency shows that, despite its low quiescent current, the INA121 achieves wide bandwidth, even at high gain. This is due to the current-feedback topology of the INA121. Settling time also remains excellent at high gain.

50k G = 1+ RG

(1)

Commonly used gains and resistor values are shown in Figure 1.

V+ 0.1F

7 VIN 2 Over-Voltage Protection INA121 A1 40k 25k A3 25k A2 40k 40k 5 Ref 6
+ ) VO = G (VIN VIN +

DESIRED GAIN 1 2 5 10 20 50 100 200 500 1000 2000 5000 10000

RG ( ) NC 50.00k 12.50k 5.556k 2.632k 1.02k 505.1 251.3 100.2 50.05 25.01 10.00 5.001

NEAREST 1% RG ( ) NC 49.9k 12.4k 5.62k 2.61k 1.02k 511 249 100 49.9 24.9 10 4.99

40k

G=1+

50k RG

RG 8

Load VO

+ VIN

Over-Voltage Protection

0.1F

NC: No Connection.
Also drawn in simplified form: VIN RG + VIN INA121 Ref VO

FIGURE 1. Basic Connections.

INA121

The INA121 provides excellent rejection of high frequency common-mode signals. The typical performance curve, Common-Mode Rejection vs Frequency shows this behavior. If the inputs are not properly balanced, however, common-mode signals can be converted to differential sig + nals. Run the VIN and VIN connections directly adjacent each other, from the source signal all the way to the input pins. If possible use a ground plane under both input traces. Avoid running other potentially noisy lines near the inputs. NOISE AND ACCURACY PERFORMANCE The INA121s FET input circuitry provides low input bias current and high speed. It achieves lower noise and higher accuracy with high impedance sources. With source impedances of 2k to 50k the INA114, INA128, or INA129 may provide lower offset voltage and drift. For very low source impedance (1k), the INA103 may provide improved accuracy and lower noise. At very high source impedances (> 1M) the INA116 is recommended. OFFSET TRIMMING The INA121 is laser trimmed for low offset voltage and drift. Most applications require no external offset adjustment. Figure 2 shows an optional circuit for trimming the output offset voltage. The voltage applied to Ref terminal is summed at the output. The op amp buffer provides low impedance at the Ref terminal to preserve good commonmode rejection. Trim circuits with higher source impedance should be buffered with an op amp follower circuit to assure low impedance on the Ref pin.

Input circuitry must provide a path for this input bias current if the INA121 is to operate properly. Figure 3 shows various provisions for an input bias current path. Without a bias current return path, the inputs will float to a potential which exceeds the common-mode range of the INA121 and the input amplifiers will saturate. If the differential source resistance is low, the bias current return path can be connected to one input (see the thermocouple example in Figure 3). With higher source impedance, using two resistors provides a balanced input with possible advantages of lower input offset voltage due to bias current and better high-frequency common-mode rejection.

Crystal or Ceramic Transducer 1M 1M

INA121

Thermocouple

INA121

10k

INA121

VIN RG + VIN INA121 Ref

VO

V+ 100A 1/2 REF200

Center-tap provides bias current return.

INA121

OPA277 10mV Adjustment Range 10k(1)

100(1)

VREF

Bridge

100(1)

Bridge resistance provides bias current return.

NOTE: (1) For wider trim range required in high gains, scale resistor values larger V

100A 1/2 REF200

FIGURE 3. Providing an Input Common-Mode Current Path. INPUT COMMON-MODE RANGE The linear input voltage range of the input circuitry of the INA121 is from approximately 1.2V below the positive supply voltage to 2.1V above the negative supply. A differential input voltage causes the output voltage to increase. The linear input range, however, will be limited by the output voltage swing of amplifiers A1 and A2. So the linear common-mode input range is related to the output voltage of the complete amplifier. This behavior also depends on supply voltagesee typical performance curve Input Common-Mode Range vs Output Voltage.

FIGURE 2. Optional Trimming of Output Offset Voltage. INPUT BIAS CURRENT RETURN PATH The input impedance of the INA121 is extremely high approximately 1012. However, a path must be provided for the input bias current of both inputs. This input bias current is typically 4pA. High input impedance means that this input bias current changes very little with varying input voltage.

INA121

A combination of common-mode and differential input voltage can cause the output of A1 or A2 to saturate. Figure 4 shows the output voltage swing of A1 and A2 expressed in terms of a common-mode and differential input voltages. For applications where input common-mode range must be maximized, limit the output voltage swing by connecting the INA121 in a lower gain (see performance curve Input Common-Mode Voltage Range vs Output Voltage). If necessary, add gain after the INA121 to increase the voltage swing. Input-overload can produce an output voltage that appears normal. For example, if an input overload condition drives both input amplifiers to their positive output swing limit, the difference voltage measured by the output amplifier will be near zero. The output of A3 will be near 0V even though both inputs are overloaded. LOW VOLTAGE OPERATION The INA121 can be operated on power supplies as low as 2.25V. Performance remains excellent with power supplies ranging from 2.25V to 18V. Most parameters vary only slightly throughout this supply voltage rangesee typical

performance curves. Operation at very low supply voltage requires careful attention to assure that the input voltages remain within their linear range. Voltage swing requirements of internal nodes limit the input common-mode range with low power supply voltage. Typical performance curves, Input Common-Mode Range vs Output Voltage show the range of linear operation for 15V, 5V, and 2.5V supplies. INPUT FILTERING The INA121s FET input allows use of an R/C input filter without creating large offsets due to input bias current. Figure 5 shows proper implementation of this input filter to preserve the INA121s excellent high frequency commonmode rejection. Mismatch of the common-mode input time constant (R1C1 and R2C 2), either from stray capacitance or mismatched values, causes a high frequency common-mode signal to be converted to a differential signal. This degrades common-mode rejection. The differential input capacitor, C 3, reduces the bandwidth and mitigates the effects of mismatch in C1 and C 2. Make C 3 much larger than C1 and C 2. If properly matched, C1 and C2 also improve ac CMR.

VCM

G VD 2

V+

INA121 A1 VD 2 40k 25k RG 25k A2 VCM G VD 2 40k 40k A3 40k G=1+ 50k RG

VO = G V D

VD 2

VCM +

FIGURE 4. Voltage Swing of A1 and A2.

f3 d B =
C1 VIN C3 INA121 Ref

1 C1 4 R1 C 3 + 2
+10V

R1

G = 500 Bridge VO RG 100 VO

R2 VIN
+

INA121 Ref

C2

R1 = R2 C1 = C2 C3 10C1

FET input allows use of large resistors and small capacitors.

FIGURE 5. Input Low-Pass Filter.

FIGURE 6. Bridge Transducer Amplifier. 10

INA121

6V to 18V Isolated Power

C1

V+

V 15V

C2

RG

INA121 Ref

VO
VIN

R1

R2

fc =

1 2R1C1

INA121 VIN
+

ISO124

VO

Ref

NOTE: To preserve good low frequency CMR, make R1 = R2 and C1 = C2.

Isolated Common

FIGURE 7. High-Pass Input Filter.

FIGURE 8. Galvanically Isolated Instrumentation Amplifier.

VIN OPA277
VIN + RG INA121 Ref C1 0.1F

VO

C1 50nF

R1 1M

R1 10k INA121 RG R2 VIN G R2

OPA277

1 f3dB = 2R1C1 = 1.59Hz

Ref IL = Make G 10 where G = 1 + 50k RG Load

FIGURE 9. AC-Coupled Instrumentation Amplifier.

FIGURE 10. Voltage Controlled Current Source.

VAC R1 R2

C1 Transducer

C2 Null

RG

INA121 Ref

VO

FIGURE 11. Capacitive Bridge Transducer Circuit.

11

INA121

+5V VREF Channel 1 VIN + MPC800 MUX Channel 8 VIN + +In RG INA121 In Ref ADS7816 12 Bits Out Serial

FIGURE 12. Multiplexed-Input Data Acquisition System.

VIN
+ VIN

22.1k 22.1k

511

INA121 Ref

VO

100 NOTE: Driving the shield minimizes CMR degradation due to unequally distributed capacitance on the input line. The shield is driven at approximately 1V below the common-mode input voltage. OPA130

For G = 100 RG = 511 // 2(22.1k) effective RG = 505

FIGURE 13. Shield Driver Circuit.

RG = 5.6k 2.8k LA RG/2 2.8k 390k Low bias current allows use with high electrode impedances. RL 390k 1/2 OPA2131 10k VG 1/2 OPA2131 VG NOTE: Due to the INA121s current-feedback topology, VG is approximately 0.7V less than the common-mode input voltage. This DC offset in this guard potential is satisfactory for many guarding applications. INA121 Ref VO G = 10

RA

FIGURE 14. ECG Amplifier With Right-Leg Drive.

INA121

12

IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TIs standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customers applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TIs publication of information regarding any third partys products or services does not constitute TIs approval, warranty or endorsement thereof.

Copyright 2000, Texas Instruments Incorporated

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