ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R)

DECODER VHDL CODE USING BEHAVIOURAL MODELING

library IEEE; use IEEE.STD_LOGIC_1164.ALL; --------------------------------------------------------entity dec_1 is Port ( a: in std_logic_vector (1 downto 0 ); e: in std_logic; y: out std_logic_vector (3 downto 0); end dec_1; ---------------------------------------------------------architecture Behavioral_dec of dec_1 is begin ---------------------------------------------process(e,a) begin if (e='1') then case a is when "00"=> y<= "0001"; when "01"=> y<= "0010"; when "10"=> y<= "0100"; when others=> y<= "1000"; end case; else y<= "0000"; end if; end process; ---------------------------------------------end Behavioral_dec;

Library declaration

Std_logic_1164. package for std_logic (predefined data type).

Entity declaration. a :- input port bits.(code that is being to convert by decoder) e: enable pin of decoder. e=1 decoder will perform operation, if e=0 output will be zero. y: - output port bits. (Converted code)

This is the process statement. In process statement all the statements are executed in sequence. Here we are using case statements. According to the input line status, case statement assigns desire code to output. (i.e. the function of decoder- decoder converts the binary to other code representation.)

RTL VIEW:-

OUT PUT WAVEFORMS

INFOOP2R.WIX.COM/OP2R