SN74LVC2G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

www.ti.com
SCES203M APRIL 1999 REVISED FEBRUARY 2007

FEATURES
Available in the Texas Instruments NanoFree Package Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 5.9 ns at 3.3 V Low Power Consumption, 10-A Max ICC 24-mA Output Drive at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C
DCT PACKAGE (TOP VIEW)

Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25C Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
YZP PACKAGE (BOTTOM VIEW)

DCU PACKAGE (TOP VIEW)

CLK D Q GND

1 2 3 4

8 7 6 5

VCC PRE CLR Q

CLK D Q GND

1 2 3 4

8 7 6 5

VCC PRE CLR Q

GND Q D CLK

4 5 3 6 2 7 1 8

Q CLR PRE VCC

See mechanical drawings for dimensions.

DESCRIPTION/ORDERING INFORMATION
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation. NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION
TA PACKAGE (1) NanoFree WCSP (DSBGA) 0.23-mm Large Bump YZP (Pb-free) 40C to 85C SSOP DCT VSSOP DCU (1) (2) Reel of 3000 Reel of 3000 Reel of 3000 Reel of 250 ORDERABLE PART NUMBER SN74LVC2G74YZPR SN74LVC2G74DCTR SN74LVC2G74DCUR SN74LVC2G74DCUT TOP-SIDE MARKING (2) _ _ _CP_ C74_ _ _ C74_

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site. DCU: The actual top-side marking has one additional character that designates the assembly/test site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 19992007, Texas Instruments Incorporated

SN74LVC2G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

SCES203M APRIL 1999 REVISED FEBRUARY 2007

www.ti.com

FUNCTION TABLE
INPUTS PRE L H L H H H (1) CLR H L L H H H CLK X X X L D X X X H L X Q H L H (1) H L Q0 OUTPUTS Q L H H (1) L H Q0

This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level.

LOGIC DIAGRAM (POSITIVE LOGIC)

PRE CLK 7 1 C

C C

5 TG

C C

TG

TG

TG

3 C CLR 6 C C

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SN74LVC2G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

SCES203M APRIL 1999 REVISED FEBRUARY 2007 (1)

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

MIN VCC VI VO VO IIK IOK IO Supply voltage range Input voltage range (2) Voltage range applied to any output in the high-impedance or power-off Voltage range applied to any output in the high or low state (2) (3) Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND DCT package JA Tstg (1) (2) (3) (4) Package thermal impedance (4) Storage temperature range DCU package YZP package 65 VI < 0 VO < 0 state (2) 0.5 0.5 0.5 0.5 MAX 6.5 6.5 6.5 VCC + 0.5 50 50 50 100 220 227 102 150 C C/W UNIT V V V V mA mA mA mA

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7.

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SN74LVC2G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

SCES203M APRIL 1999 REVISED FEBRUARY 2007

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Recommended Operating Conditions (1)

MIN VCC Supply voltage Operating Data retention only VCC = 1.65 V to 1.95 V VIH High-level input voltage VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VI VO Input voltage Output voltage VCC = 1.65 V VCC = 2.3 V IOH High-level output current VCC = 3 V VCC = 4.5 V VCC = 1.65 V VCC = 2.3 V IOL Low-level output current VCC = 3 V VCC = 4.5 V VCC = 1.8 V 0.15 V, 2.5 V 0.2 V t/v TA (1) Input transition rise or fall rate Operating free-air temperature VCC = 3.3 V 0.3 V VCC = 5 V 0.5 V 40 0 0 1.65 1.5 0.65 VCC 1.7 2 0.7 VCC 0.35 VCC 0.7 0.8 0.3 VCC 5.5 VCC 4 8 16 24 32 4 8 16 24 32 20 10 5 85 C ns/V mA mA V V V V MAX 5.5 UNIT V

All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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SN74LVC2G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

SCES203M APRIL 1999 REVISED FEBRUARY 2007

Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = 100 A IOH = 4 mA VOH IOH = 8 mA IOH = 16 mA IOH = 24 mA IOH = 32 mA IOL = 100 A IOL = 4 mA VOL IOL = 8 mA IOL = 16 mA IOL = 24 mA IOL = 32 mA II Ioff ICC ICC Ci (1) Data or control inputs VI = 5.5 V or GND VI or VO = 5.5 V VI = 5.5 V or GND, One input at VCC 0.6 V, VI = VCC or GND All typical values are at VCC = 3.3 V, TA = 25C. IO = 0 Other inputs at VCC or GND TEST CONDITIONS VCC 1.65 V to 5.5 V 1.65 V 2.3 V 3V 4.5 V 1.65 V to 5.5 V 1.65 V 2.3 V 3V 4.5 V 0 to 5.5 V 0 1.65 V to 5.5 V 3 V to 5.5 V 3.3 V 5 MIN TYP (1) VCC 0.1 1.2 1.9 2.4 2.3 3.8 0.1 0.45 0.3 0.4 0.55 0.55 5 10 10 500 A A A A pF V V MAX UNIT

Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V 0.15 V MIN fclock tw tsu th Pulse duration Setup time, before CLK Hold time, data after CLK CLK PRE or CLR low Data PRE or CLR inactive 6.2 6.2 2.9 1.9 0 MAX 80 2.7 2.7 1.7 1.4 0.3 VCC = 2.5 V 0.2 V MIN MAX 175 2.7 2.7 1.3 1.2 1.2 VCC = 3.3 V 0.3 V MIN MAX 175 2 2 1.1 1 0.5 VCC = 5 V 0.5 V MIN MAX 200 MHz ns ns ns UNIT

Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMETER fmax tpd CLK PRE or CLR Q Q Q or Q FROM (INPUT) TO (OUTPUT) VCC = 1.8 V 0.15 V MIN 80 4.8 6 4.4 13.4 14.4 12.9 MAX VCC = 2.5 V 0.2 V MIN 175 2.2 3 2.3 7.1 7.7 7 MAX VCC = 3.3 V 0.3 V MIN 175 2.2 2.6 1.7 5.9 6.2 5.9 MAX VCC = 5 V 0.5 V MIN 200 1.4 1.6 1.6 4.1 4.4 4.1 ns MAX MHz UNIT

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SN74LVC2G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

SCES203M APRIL 1999 REVISED FEBRUARY 2007

www.ti.com

Operating Characteristics
TA = 25C
PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS f = 10 MHz VCC = 1.8 V TYP 35 VCC = 2.5 V TYP 35 VCC = 3.3 V TYP 37 VCC = 5 V TYP 40 UNIT pF

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SN74LVC2G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

SCES203M APRIL 1999 REVISED FEBRUARY 2007

PARAMETER MEASUREMENT INFORMATION

VLOAD From Output Under Test CL (see Note A) RL RL S1 Open GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open VLOAD GND

LOAD CIRCUIT INPUTS VCC 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5 V 0.5 V VI VCC VCC 3V VCC tr/tf 2 ns 2 ns 2.5 ns 2.5 ns VM VCC/2 VCC/2 1.5 V VCC/2 VLOAD 2 VCC 2 VCC 6V 2 VCC CL 30 pF 30 pF 50 pF 50 pF RL 1 kW 500 W 500 W 500 W VD 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input tW VI Input VM VOLTAGE WAVEFORMS PULSE DURATION VI Input tPLH Output tPHL VM VM VM VM 0V tPHL VOH VM VOL tPLH VOH Output VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at VLOAD (see Note B) tPZH VM VM 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM tPZL VM VM 0V tPLZ VLOAD/2 VOL + VD tPHZ VOH VD VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING VOL Data Input tsu VM th VI VM 0V VM 0V

Output Control

NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

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PACKAGE OPTION ADDENDUM

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8-Dec-2008

PACKAGING INFORMATION
Orderable Device SN74LVC2G74DCTR SN74LVC2G74DCTRE4 SN74LVC2G74DCTRG4 SN74LVC2G74DCUR SN74LVC2G74DCURE4 SN74LVC2G74DCURG4 SN74LVC2G74DCUT SN74LVC2G74DCUTE4 SN74LVC2G74DCUTG4 SN74LVC2G74YZPR
(1)

Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE

Package Type SM8 SM8 SM8 US8 US8 US8 US8 US8 US8 DSBGA

Package Drawing DCT DCT DCT DCU DCU DCU DCU DCU DCU YZP

Pins Package Eco Plan (2) Qty 8 8 8 8 8 8 8 8 8 8 3000 Green (RoHS & no Sb/Br) 3000 Green (RoHS & no Sb/Br) 3000 Green (RoHS & no Sb/Br) 3000 Green (RoHS & no Sb/Br) 3000 Green (RoHS & no Sb/Br) 3000 Green (RoHS & no Sb/Br) 250 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU SNAGCU

MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM

3000 Green (RoHS & no Sb/Br)

The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

8-Dec-2008

OTHER QUALIFIED VERSIONS OF SN74LVC2G74 : SN74LVC2G74-Q1 Automotive: Enhanced Product: SN74LVC2G74-EP NOTE: Qualified Version Definitions: - Q100 devices qualified for high-reliability automotive applications targeting zero defects Automotive Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Dec-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins Type Drawing US8 DSBGA DCU YZP 8 8

SPQ

Reel Reel Diameter Width (mm) W1 (mm) 180.0 180.0 9.2 8.4

A0 (mm)

B0 (mm)

K0 (mm)

P1 (mm) 4.0 4.0

W Pin1 (mm) Quadrant 8.0 8.0 Q3 Q1

SN74LVC2G74DCUR SN74LVC2G74YZPR

3000 3000

2.25 1.1

3.35 2.1

1.05 0.56

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Dec-2008

*All dimensions are nominal

Device SN74LVC2G74DCUR SN74LVC2G74YZPR

Package Type US8 DSBGA

Package Drawing DCU YZP

Pins 8 8

SPQ 3000 3000

Length (mm) 202.0 220.0

Width (mm) 201.0 220.0

Height (mm) 28.0 34.0

Pack Materials-Page 2

MECHANICAL DATA
MPDS049B MAY 1999 REVISED OCTOBER 2002

DCT (R-PDSO-G8)
0,30 0,15 8 5

PLASTIC SMALL-OUTLINE PACKAGE

0,65

0,13 M

PIN 1 INDEX AREA

1 3,15 2,75 4

0,15 NOM 2,90 2,70 4,25 3,75

Gage Plane 0,25 0 8 0,60 0,20

1,30 MAX

Seating Plane 0,10 0,10 0,00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion Falls within JEDEC MO-187 variation DA. 4188781/C 09/02

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