Beruflich Dokumente
Kultur Dokumente
PIC12F629/675
Data Sheet
8-Pin FLASH-Based 8-Bit
CMOS Microcontrollers
Preliminary
DS41190A
Note the following details of the code protection feature on PICmicro MCUs.
The PICmicro family meets the specifications contained in the Microchip Data Sheet.
Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
DS41190A - page ii
Preliminary
PIC12F629/675
Pin Diagram
8-Pin PDIP, SOIC
PIC12F675
VDD
GP3/MCLR/VPP
1
2
3
4
PIC12F629
GP5/T1CKI/
OSC1/CLKIN
GP4/T1G/
OSC2/CLKOUT
VSS
GP0/CIN+/ICSPDAT
GP1/CIN-/ICSPCLK
GP2/T0CKI/
INT/COUT
Peripheral Features:
6 I/O pins with individual direction control
High current sink/source for direct LED drive
Analog comparator module with:
- One analog comparator
- Programmable on-chip comparator voltage
reference (CVREF) module
- Programmable input multiplexing from device
inputs
- Comparator output is externally accessible
Analog-to-Digital Converter module (PIC12F675):
- 10-bit resolution
- Programmable 4-channel input
- Voltage reference input
Timer0: 8-bit timer/counter with 8-bit
programmable prescaler
Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Gate Input mode
- Option to use OSC1 and OSC2 in LP mode
as Timer1 oscillator, if INTRC Oscillator mode
selected
64 bytes of general purpose RAM
CMOS Technology:
Low power, high speed CMOS FLASH technology
Fully static design
Wide operating voltage range
- PIC12F629/675 - 2.0V to 5.5V
Industrial and Extended temperature range
Low power consumption
- < 1.0 mA @ 5.5V, 4.0 MHz
- 20 A typical @ 2.0V, 32 kHz
- < 1.0 A typical standby current @ 2.0V
* 8-bit, 8-pin devices protected by Microchips Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and
foreign patents and applications may be issued or pending.
Preliminary
DS41190A-page 1
PIC12F629/675
Pin Diagrams
8-pin PDIP, SOIC
1
GP5/T1CKI/OSC1/CLKIN
GP4/AN3/T1G/OSC2/CLKOUT
GP3/MCLR/VPP
PIC12F675
VDD
VSS
GP0/AN0/CIN+/ICSPDAT
GP1/AN1/CIN-/VREF/ICSPCLK
GP2/AN2/T0CKI/INT/COUT
VSS
GP0/CIN+/ICSPDAT
GP1/CIN-/ICSPCLK
GP2/T0CKI/INT/COUT
VSS
GP0/AN0/CIN+/ICSPDAT
GP1/AN1/CIN-/VREF/ICSPCLK
GP2/AN2/T0CKI/INT/COUT
8-pin MLF-S
8 7 6 5
PIC12F675
1 2 3 4
1 2 3 4
VDD
GP5/T1CKI/OSC1/CLKIN
GP4/T1G/OSC2/CLKOUT
GP3/MCLR/VPP
VDD
GP5/T1CKI/OSC1/CLKIN
GP4/AN3/T1G/OSC2/CLKOUT
GP3/MCLR/VPP
8 7 6 5
PIC12F629
DS41190A-page 2
Preliminary
PIC12F629/675
Table of Contents
1.0 Device Overview. ......................................................................................................................................................................... 5
2.0 Memory Organization ....................... ............................................................................................................................................7
3.0 GPIO Port............................ .......................................................................................................................................................19
4.0 Timer0 Module ........................................................................................................................................................................... 25
5.0 Timer1 Module with Gate Control............................................................................................................................................... 28
6.0 Comparator Module.................................................................................................................................................................... 33
7.0 Analog-to-Digital Converter (A/D) Module (PIC12F675 only)..................................................................................................... 39
8.0 Data EEPROM Memory. ............................................................................................................................................................ 47
9.0 Special Features of the CPU...................................................................................................................................................... 51
10.0 Instruction Set Summary ............................................................................................................................................................ 69
11.0 Development Support................................................................................................................................................................. 77
12.0 Electrical Specifications.............................................................................................................................................................. 83
13.0 Packaging Information.............................................................................................................................................................. 101
Appendix A: Data Sheet Revision History ....................................................................................................................................... 107
Appendix B: Device Differences...................................................................................................................................................... 107
Appendix C: Device Migrations ....................................................................................................................................................... 108
Appendix D: Migrating from other PICmicro Devices ...................................................................................................................... 108
Appendix E: Development Tool Version Requirements .................................................................................................................. 109
Index .................................................................................................................................................................................................. 111
On-Line Support ................................................................................................................................................................................ 115
Reader Response ............................................................................................................................................................................. 116
Product Identification System ........................................................................................................................................................... 117
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
Microchips Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
Preliminary
DS41190A-page 3
PIC12F629/675
NOTES:
DS41190A-page 4
Preliminary
PIC12F629/675
1.0
DEVICE OVERVIEW
FIGURE 1-1:
Data Bus
Program Counter
FLASH
Program
Memory
Program
Bus
GP0/AN0/CIN+
GP1/AN1/CIN-/VREF
GP2/AN2/T0CKI/INT/COUT
GP3/MCLR/VPP
GP4/AN3/T1G/OSC2/CLKOUT
GP5/T1CKI/OSC1/CLKIN
RAM
File
Registers
64 x 8
8 Level Stack
(13-bit)
1K x 14
14
RAM
Addr(1)
Addr MUX
Instruction Reg
Direct Addr
7
8
Indirect
Addr
FSR Reg
Internal
4 MHz
Oscillator
STATUS Reg
8
3
Instruction
Decode &
Control
Power-up
Timer
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MUX
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
VDD, VSS
ALU
8
W Reg
10-bit A/D
(PIC12F675 only)
Timer0
Timer1
CVREF
Comparator
EE Data
Memory
Preliminary
DS41190A-page 5
PIC12F629/675
TABLE 1-1:
GP3/MCLR/VPP
GP4/AN3/T1G/OSC2/
CLKOUT
GP5/T1CKI/OSC1/CLKIN
VSS
VDD
DS41190A-page 6
GP0
TTL
CMOS
AN0
CIN+
ICSPDAT
GP1
AN
AN
TTL
TTL
CMOS
CMOS
AN1
CINVREF
ICSPCLK
GP2
AN
AN
AN
ST
ST
CMOS
AN
ST
ST
GP3
TTL
ST
HV
Master Clear
Programming voltage
GP4
TTL
AN
T1G
OSC2
CLKOUT
GP2/AN2/T0CKI/INT/COUT
Output
Type
AN3
GP1/AN1/CIN-/VREF/
ICSPCLK
Input
Type
MCLR
VPP
GP0/AN0/CIN+/ICSPDAT
Function
AN2
T0CKI
INT
COUT
Name
ST
GP5
TTL
T1CKI
OSC1
CLKIN
VSS
VDD
ST
XTAL
ST
Power
Power
CMOS
CMOS
XTAL
CMOS
CMOS
Description
Bi-directional I/O w/ programmable pull-up and
interrupt-on-change
A/D Channel 0 input (PIC12F675 only)
Comparator input
Serial programming I/O
Bi-directional I/O w/ programmable pull-up and
interrupt-on-change
A/D Channel 1 input (PIC12F675 only)
Comparator input
External voltage reference (PIC12F675 only)
Serial programming clock
Bi-directional I/O w/ programmable pull-up and
interrupt-on-change
A/D Channel 2 input (PIC12F675 only)
TMR0 clock input
External interrupt
Comparator output
Preliminary
PIC12F629/675
2.0
MEMORY ORGANIZATION
2.2
2.1
FIGURE 2-1:
CALL, RETURN
RETFIE, RETLW
2.2.1
13
Stack Level 1
Stack Level 2
Stack Level 8
RESET Vector
000h
Interrupt Vector
0004
0005
On-chip Program
Memory
03FFh
0400h
1FFFh
Preliminary
DS41190A-page 7
PIC12F629/675
2.2.2
FIGURE 2-2:
Indirect addr.(1)
TMR0
PCL
STATUS
FSR
GPIO
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
CMCON
ADRESH(2)
ADCON0(2)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
General
Purpose
Registers
File
Address
Indirect addr.(1)
OPTION_REG
PCL
STATUS
FSR
TRISIO
PCLATH
INTCON
PIE1
PCON
OSCCAL
WPU
IOCB
VRCON
EEDATA
EEADR
EECON1
EECON2(1)
ADRESL(2)
ANSEL(2)
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
accesses
20h-5Fh
64 Bytes
5Fh
60h
DFh
E0h
7Fh
Bank 0
1:
2:
DS41190A-page 8
Preliminary
FFh
Bank 1
PIC12F629/675
TABLE 2-1:
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR Reset
Page
Bank 0
00h
INDF(1)
0000 0000
18,59
01h
TMR0
xxxx xxxx
25
02h
PCL
0000 0000
17
03h
STATUS
04h
FSR
05h
GPIO
IRP(2)
RP1(2)
RP0
PD
DC
--xx xxxx
19
Unimplemented
07h
Unimplemented
08h
Unimplemented
09h
Unimplemented
---0 0000
17
PCLATH
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
11
18
06h
0Ah
0001 1xxx
xxxx xxxx
TO
0Bh
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000
13
0Ch
PIR1
EEIF
ADIF
CMIF
TMR1IF
00-- 0--0
15
0Dh
Unimplemented
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit Timer1
xxxx xxxx
28
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit Timer1
xxxx xxxx
28
10h
T1CON
-000 0000
30
11h
Unimplemented
12h
Unimplemented
13h
Unimplemented
14h
Unimplemented
15h
Unimplemented
16h
Unimplemented
17h
Unimplemented
18h
Unimplemented
-0-0 0000
33
19h
CMCON
TMR1GE
COUT
T1CKPS1
T1CKPS0
CINV
T1OSCEN
CIS
T1SYNC
CM2
TMR1CS
CM1
TMR1ON
CM0
1Ah
Unimplemented
1Bh
Unimplemented
1Ch
Unimplemented
1Dh
Unimplemented
xxxx xxxx
40
00-- 0000
41,59
1Eh
ADRESH(3)
1Fh
ADCON0(3)
Most Significant 8 bits of the Left Shifted A/D Result or 2 bits of the Right Shifted Result
ADFM
VCFG
CHS1
CHS0
GO/DONE
ADON
Legend:
Preliminary
DS41190A-page 9
PIC12F629/675
TABLE 2-1:
Address
Bit 7
Bit 6
Bit 5
Bit 2
0000 0000
Bit 1
Bit 0
PS1
PS0
Page
18,59
1111 1111
12,26
0000 0000
Bit 3
Value on
POR Reset
17
0001 1xxx
11
xxxx xxxx
Bit 4
18
--11 1111
19
Bank 1
80h
INDF(1)
81h
OPTION_REG
82h
PCL
83h
STATUS
84h
FSR
85h
TRISIO
INTEDG
T0CS
T0SE
PSA
PS2
RP0
RP1(2)
TO
PD
DC
TRIS4
TRIS3
TRIS2
TRIS1
TRIS0
TRIS5
86h
Unimplemented
87h
Unimplemented
88h
Unimplemented
89h
Unimplemented
---0 0000
17
8Ah
PCLATH
8Bh
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000
13
8Ch
PIE1
EEIE
ADIE
CMIE
TMR1IE
00-- 0--0
14
8Dh
8Eh
PCON
Unimplemented
16
POR
BOD
---- --0x
CAL4
CAL3
CAL2
CAL1
CAL0
1000 00--
16
8Fh
90h
OSCCAL
91h
Unimplemented
92h
Unimplemented
93h
Unimplemented
94h
Unimplemented
95h
WPU
96h
IOCB
Unimplemented
CAL5
WPU5
WPU4
WPU2
WPU1
WPU0
--11 1111
19
IOCB5
IOCB4
IOCB3
IOCB2
IOCB1
IOCB0
--00 0000
20
97h
Unimplemented
98h
Unimplemented
0-0- 0000
38
0000 0000
47
-000 0000
47
---- x000
48
48
99h
VRCON
VREN
VRR
VR3
VR2
VR1
VR0
9Ah
EEDATA
9Bh
EEADR
9Ch
EECON1
9Dh
EECON2(1)
---- ----
9Eh
ADRESL(3)
Least Significant 2 bits of the Left Shifted A/D Result of 8 bits or the Right Shifted Result
xxxx xxxx
40
9Fh
ANSEL(3)
-000 1111
42,59
ADCS2
ADCS1
ADCS0
WRERR
ANS3
WREN
ANS2
WR
ANS1
RD
ANS0
Legend:
DS41190A-page 10
Preliminary
PIC12F629/675
2.2.2.1
STATUS Register
REGISTER 2-1:
RP1
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
RP0
TO
PD
DC
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
bit 0
For borrow the polarity is reversed. A subtraction is executed by adding the twos
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register
Legend:
R = Readable bit
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS41190A-page 11
PIC12F629/675
2.2.2.2
OPTION Register
Note:
TMR0/WDT prescaler
External GP2/INT interrupt
TMR0
Weak pull-ups on GPIO
REGISTER 2-2:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit
DS41190A-page 12
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
PIC12F629/675
2.2.2.3
INTCON Register
Note:
REGISTER 2-3:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS41190A-page 13
PIC12F629/675
2.2.2.4
PIE1 Register
REGISTER 2-4:
Note:
R/W-0
U-0
U-0
R/W-0
U-0
U-0
R/W-0
EEIE
ADIE
CMIE
TMR1IE
bit 7
bit 0
bit 7
bit 6
bit 5-4
Unimplemented: Read as 0
bit 3
bit 2-1
Unimplemented: Read as 0
bit 0
DS41190A-page 14
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
PIC12F629/675
2.2.2.5
PIR1 Register
REGISTER 2-5:
Note:
R/W-0
U-0
U-0
R/W-0
U-0
U-0
R/W-0
EEIF
ADIF
CMIF
TMR1IF
bit 7
bit 0
bit 7
bit 6
bit 5-4
Unimplemented: Read as 0
bit 3
bit 2-1
Unimplemented: Read as 0
bit 0
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS41190A-page 15
PIC12F629/675
2.2.2.6
PCON Register
REGISTER 2-6:
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-x
POR
BOD
bit 7
bit 0
bit 7-2
bit 1
bit 0
2.2.2.7
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
OSCCAL Register
REGISTER 2-7:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
bit 7
bit 0
bit 7-2
bit 1-0
- n = Value at POR
DS41190A-page 16
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
PIC12F629/675
2.3
2.3.2
FIGURE 2-3:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
PC
8
PCLATH<4:0>
Instruction with
PCL as
Destination
ALU result
PCLATH
PCH
12
11 10
PCL
8
PC
STACK
GOTO, CALL
PCLATH<4:3>
11
Opcode <10:0>
PCLATH
2.3.1
COMPUTED GOTO
Preliminary
DS41190A-page 17
PIC12F629/675
2.4
EXAMPLE 2-1:
Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually
accesses data pointed to by the File Select register
(FSR). Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a no
operation (although STATUS bits may be affected). An
effective 9-bit address is obtained by concatenating the
8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 2-4.
FIGURE 2-4:
movlw
movwf
clrf
incf
btfss
goto
NEXT
0x20
FSR
INDF
FSR
FSR,4
NEXT
CONTINUE
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
;yes continue
Direct Addressing
RP1(1) RP0
INDIRECT ADDRESSING
From Opcode
Indirect Addressing
IRP(1)
Bank Select
01
10
FSR Register
Location Select
11
00h
180h
Data
Memory
Not Used
7Fh
1FFh
Bank 0
Bank 1
Bank 2
Bank 3
DS41190A-page 18
Preliminary
PIC12F629/675
3.0
GPIO PORT
3.1
EXAMPLE 3-1:
GPIO is an 6-bit wide, bi-directional port. The corresponding data direction register is TRISIO. Setting a
TRISIO bit (= 1) will make the corresponding GPIO pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISIO bit (= 0) will
make the corresponding GPIO pin an output (i.e., put
the contents of the output latch on the selected pin).
The exception is GP3, which is input only and its TRIS
bit will always read as 1. Example 3-1 shows how to
initialize GPIO.
STATUS,RP0
GPIO
07h
CMCON
STATUS,RP0
0Ch
TRISIO
bcf
STATUS,RP0
3.2
;Bank 0
;Init GPIO
;Set GP<2:0> to
;digital IO
;Bank 1
;Set GP<3:2> as inputs
;and set GP<5:4,1:0>
;as outputs
;Bank 0
Every GPIO pin on the PIC12F629/675 has an interrupt-on-change option and every GPIO pin, except
GP3, has a weak pull-up option. The next two sections
describe these functions.
3.2.1
REGISTER 3-1:
INITIALIZING GPIO
bcf
clrf
movlw
movwf
bsf
movlw
movwf
WEAK PULL-UP
U-0
R/W-1
R/W-1
U-0
R/W-1
R/W-1
R/W-1
WPU5
WPU4
WPU2
WPU1
WPU0
bit 7
bit 0
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3
Unimplemented: Read as 0
bit 2-0
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS41190A-page 19
PIC12F629/675
3.2.2
INTERRUPT-ON-CHANGE
REGISTER 3-2:
Any read or write of GPIO. This will end the mismatch condition.
Clear the flag bit GPIF.
b)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IOCB5
IOCB4
IOCB3
IOCB2
IOCB1
IOCB0
bit 7
bit 0
bit 7-6
Unimplemented: Read as 0
bit 5-0
- n = Value at POR
DS41190A-page 20
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
PIC12F629/675
3.3
FIGURE 3-1:
3.3.1
GP0/AN0/CIN+
Data Bus
WR
WPU
D
CK
VDD
Weak
GPPU
RD
WPU
Figure 3-1 shows the diagram for this pin. The GP0 pin
is configurable to function as one of the following:
a general purpose I/O
an analog input for the A/D (PIC12F675 only)
an analog input to the comparator
3.3.2
D
WR
PORT
Q
I/O pin
GP1/AN1/CIN-/VREF
Figure 3-1 shows the diagram for this pin. The GP1 pin
is configurable to function as one of the following:
CK
VDD
WR
TRIS
CK
Q
Q
VSS
Analog
Input Mode
RD
TRIS
RD
PORT
D
WR
IOCB
CK
Q
Q
Q
EN
RD
IOCB
D
EN
Interrupt-on-Change
RD PORT
To Comparator
To A/D Converter
Preliminary
DS41190A-page 21
PIC12F629/675
3.3.3
GP2/AN2/T0CKI/INT/COUT
3.3.4
GP3/MCLR/VPP
Figure 3-2 shows the diagram for this pin. The GP2 pin
is configurable to function as one of the following:
Figure 3-3 shows the diagram for this pin. The GP3 pin
is configurable to function as one of the following:
FIGURE 3-3:
Data Bus
FIGURE 3-2:
Data Bus
WR
WPU
RD
TRIS
CK
VDD
D
WR
PORT
WR
IOCB
Q
Q
RD
IOCB
VDD
D
EN
CK
COUT
Interrupt-on-Change
1
0
D
WR
TRIS
CK
VSS
EN
Analog
Input
Mode
COUT
Enable
MCLRE
GPPU
RD
WPU
I/O pin
VSS
RD
PORT
Weak
MCLRE
RESET
CK
I/O pin
RD PORT
Q
Q
VSS
Analog
Input Mode
RD
TRIS
RD
PORT
D
WR
IOCB
CK
Q
Q
Q
EN
RD
IOCB
Interrupt-on-Change
D
EN
RD PORT
To TMR0
To INT
To A/D Converter
DS41190A-page 22
Preliminary
PIC12F629/675
3.3.5
GP4/AN3/T1G/OSC2/CLKOUT
3.3.6
GP5/T1CKI/OSC1/CLKIN
Figure 3-4 shows the diagram for this pin. The GP4 pin
is configurable to function as one of the following:
Figure 3-5 shows the diagram for this pin. The GP5 pin
is configurable to function as one of the following:
FIGURE 3-5:
FIGURE 3-4:
Analog
Input Mode
Data Bus
WR
WPU
D
CK
Data Bus
TMR1LPEN
D
VDD
WR
WPU
Weak
CK
GPPU
Oscillator
Circuit
Oscillator
Circuit
OSC1
FOSC/4
D
CK
OSC2
VDD
CLKOUT
Enable
D
WR
PORT
1
0
CK
WR
TRIS
INTOSC/
EXTRC/EC1(2)
CLKOUT
Enable
INTOSC
Mode
(1)
D
WR
IOCB
CK
Q
Q
RD
IOCB
Q
EN
Q
Interrupt-on-Change
Q
EN
RD
IOCB
VSS
RD
PORT
Analog
Input Mode
CK
RD
TRIS
RD
PORT
WR
IOCB
CK
RD
TRIS
Q
I/O pin
D
CLKOUT
Enable
CK
VDD
I/O pin
VSS
WR
TRIS
Weak
RD
WPU
GPPU
RD
WPU
WR
PORT
VDD
Interrupt-on-Change
D
EN
EN
RD PORT
RD PORT
To TMR1 or CLKGEN
To TMR1 T1G
To A/D Converter
Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT
Enable.
Preliminary
DS41190A-page 23
PIC12F629/675
TABLE 3-1:
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other
RESETS
--uu uuuu
05h
GPIO
GP5
GP4
GP3
GP2
GP1
GP0
--xx xxxx
0Bh/8Bh
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000
0000 000u
19h
CMCON
COUT
CINV
CIS
CM2
CM1
CM0
-0-0 0000
-0-0 0000
1111 1111
81h
OPTION_REG
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
85h
TRISIO
TRIS5
TRIS4
TRIS3
TRIS2
TRIS1
TRIS0
--11 1111
--11 1111
95h
WPU
WPU5
WPU4
WPU2
WPU1
WPU0
--11 -111
--11 -111
96h
IOCB
IOCB5
IOCB4
IOCB3
IOCB2
IOCB1
IOCB0
--00 0000
--00 0000
9Fh
ANSEL
ADCS2
ADCS1
ADCS0
ANS3
ANS2
ANS1
ANS0
-000 1111
-000 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as 0. Shaded cells are not used by GPIO.
DS41190A-page 24
Preliminary
PIC12F629/675
4.0
TIMER0 MODULE
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
Note:
4.1
4.2
Timer0 Interrupt
A Timer0 interrupt is generated when the TMR0 register timer/counter overflows from FFh to 00h. This overflow sets the T0IF bit. The interrupt can be masked by
clearing the T0IE bit (INTCON<5>). The T0IF bit
(INTCON<2>) must be cleared in software by the
Timer0 module Interrupt Service Routine before reenabling this interrupt. The Timer0 interrupt cannot
wake the processor from SLEEP since the timer is
shut-off during SLEEP.
Timer0 Operation
FIGURE 4-1:
CLKOUT
(= FOSC/4)
Data Bus
0
8
1
SYNC 2
Cycles
1
T0CKI
pin
0
T0SE
T0CS
8-bit
Prescaler
PSA
PSA
TMR0
PS0 - PS2
1
WDT
Time-out
Watchdog
Timer
PSA
WDTE
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the Option register.
Preliminary
DS41190A-page 25
PIC12F629/675
4.3
REGISTER 4-1:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit
- n = Value at POR
DS41190A-page 26
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
PIC12F629/675
4.4
EXAMPLE 4-1:
Prescaler
bcf
STATUS,RP0
clrwdt
clrf
TMR0
bsf
SWITCHING PRESCALER
ASSIGNMENT
STATUS,RP0
;Bank 0
;Clear WDT
;Clear TMR0 and
; prescaler
;Bank 1
movlw
b00101111 ;Required if desired
movwf
OPTION_REG ; PS2:PS0 is
clrwdt
; 000 or 001
;
movlw
b00101xxx ;Set postscaler to
movwf
OPTION_REG ; desired WDT rate
bcf
STATUS,RP0 ;Bank 0
4.4.1
CHANGING PRESCALER
(TIMER0WDT)
EXAMPLE 4-2:
CHANGING PRESCALER
(WDTTIMER0)
clrwdt
bsf
STATUS,RP0
movlw
movwf
bcf
TABLE 4-1:
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h
TMR0
0Bh/8Bh
INTCON
81h
OPTION_REG
85h
TRISIO
Legend:
Value on
POR
Value on
all other
RESETS
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
TRIS5
TRIS4
TRIS3
TRIS2
TRIS1
TRIS0
Preliminary
DS41190A-page 27
PIC12F629/675
5.0
Note:
FIGURE 5-1:
TMR1ON
TMR1GE
Synchronized
Clock Input
0
TMR1H
TMR1L
1
LP Oscillator
T1SYNC
OSC1
OSC2
INTOSC
w/o CLKOUT
T1OSCEN
1
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
Detect
0
2
T1CKPS<1:0>
SLEEP Input
TMR1CS
LPEN
DS41190A-page 28
Preliminary
PIC12F629/675
5.1
5.2
FIGURE 5-2:
Timer1 Interrupt
5.3
Timer1 Prescaler
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the
clock.
Preliminary
DS41190A-page 29
PIC12F629/675
REGISTER 5-1:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1SYNC
TMR1CS
TMR1ON
bit 7
bit 0
bit 7
Unimplemented: Read as 0
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
- n = Value at POR
DS41190A-page 30
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
PIC12F629/675
5.4
Timer1 Operation in
Asynchronous Counter Mode
TABLE 5-1:
Osc Type
Reading the 16-bit value requires some care. Examples 12-2 and 12-3 in the PICmicro Mid-Range MCU
Family Reference Manual (DS33023) show how to
read and write Timer1 when it is running in Asynchronous mode.
Timer1 Oscillator
TABLE 5-2:
Address
Name
C1
C2
LP
32 kHz
33 pF
33 pF
100 kHz
15 pF
15 pF
200 kHz
15 pF
15 pF
These values are for design guidance only.
Note 1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropriate values of external components.
5.5
The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN
should be set and a suitable delay
observed prior to enabling Timer1.
5.6
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
all other
RESETS
0Bh/8Bh
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
0Ch
PIR1
EEIF
ADIF
CMIF
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
10h
T1CON
8Ch
PIE1
Legend:
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
EEIE
GPIF
Value on
POR
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu
ADIE
CMIE
Preliminary
DS41190A-page 31
PIC12F629/675
NOTES:
DS41190A-page 32
Preliminary
PIC12F629/675
6.0
COMPARATOR MODULE
The PIC12F629/675 devices have one analog comparator. The inputs to the comparator are multiplexed with
the GP0 and GP1 pins. There is an on-chip Compara-
REGISTER 6-1:
R-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
COUT
CINV
CIS
CM2
CM1
CM0
bit 7
bit 0
bit 7
Unimplemented: Read as 0
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2-0
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS41190A-page 33
PIC12F629/675
6.1
TABLE 6-1:
Comparator Operation
Input Conditions
CINV
COUT
FIGURE 6-1:
SINGLE COMPARATOR
VIN+
VIN
Output
VINVIN+
Output
Note:
DS41190A-page 34
Preliminary
PIC12F629/675
6.2
Comparator Configuration
FIGURE 6-2:
CM2:CM0 = 000
CM2:CM0 = 111
GP1/CIN-
GP0/CIN+
GP0/CIN+
GP2/COUT
GP2/COUT
GP1/CINOff (Read as 0)
Off (Read as 0)
CM2:CM0 = 010
CM2:CM0 = 100
GP1/CIN-
GP1/CIN-
GP0/CIN+
GP2/COUT
COUT
GP0/CIN+
GP2/COUT
COUT
CM2:CM0 = 011
CM2:CM0 = 101
GP1/CIN-
GP1/CIN-
GP0/CIN+
GP2/COUT
COUT
GP0/CIN+
GP2/COUT
CIS = 0
CIS = 1
COUT
CM2:CM0 = 001
CM2:CM0 = 110
GP1/CIN-
GP1/CIN-
GP0/CIN+
GP2/COUT
COUT
GP0/CIN+
GP2/COUT
CIS = 0
CIS = 1
COUT
Preliminary
DS41190A-page 35
PIC12F629/675
6.3
FIGURE 6-3:
Rs < 10K
RIC
AIN
CPIN
5 pF
VA
Leakage
500 nA
VT = 0.6V
Vss
Legend:
6.4
CPIN
VT
ILEAKAGE
RIC
RS
VA
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to Various Junctions
= Interconnect Resistance
= Source Impedance
= Analog Voltage
Comparator Output
FIGURE 6-4:
To GP2/T0CKI pin
To Data Bus
RD CMCON
CVREF
D
EN
CINV
CM2:CM0
D
EN
RD CMCON
RESET
DS41190A-page 36
Preliminary
PIC12F629/675
6.5
Comparator Reference
6.5.1
FIGURE 6-5:
6.5.2
VOLTAGE REFERENCE
ACCURACY/ERROR
VDD
8R
VRR
16-1 Analog
MUX
VREN
CVREF to
Comparator
Input
VR3:VR0
6.6
6.7
6.8
Effects of a RESET
A device RESET forces the CMCON and VRCON registers to their RESET states. This forces the comparator module to be in the Comparator Reset mode,
CM2:CM0 = 000 and the voltage reference to its off
state. Thus, all potential inputs are analog inputs with
the comparator and voltage reference disabled to consume the smallest current possible.
Preliminary
DS41190A-page 37
PIC12F629/675
REGISTER 6-2:
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VREN
VRR
VR3
VR2
VR1
VR0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3-0
- n = Value at POR
6.9
W = Writable bit
1 = Bit is set
0 = Bit is cleared
Comparator Interrupts
a)
b)
TABLE 6-2:
Address
x = Bit is unknown
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0Bh/8Bh
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
0Ch
PIR1
EEIF
ADIF
CMIF
19h
CMCON
COUT
CINV
CIS
CM2
CM1
Bit 0
GPIF
Value on
POR
Value on
all other
RESETS
8Ch
PIE1
EEIE
ADIE
CMIE
85h
TRISIO
TRIS5
TRIS4
TRIS3
TRIS2
TRIS1
TRIS0
99h
VRCON
VREN
VRR
VR3
VR2
VR1
VR0
Legend:
x = unknown, u = unchanged, - = unimplemented, read as 0. Shaded cells are not used by the comparator module.
DS41190A-page 38
Preliminary
PIC12F629/675
7.0
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
(PIC12F675 ONLY)
FIGURE 7-1:
VREF
VCFG = 1
GP0/AN0
GP1/AN1/VREF
ADC
GP2/AN2
10
GO/DONE
GP4/AN3
ADFM
CHS1:CHS0
10
ADON
ADRESH
ADRESL
VSS
7.1
There are two registers available to control the functionality of the A/D module:
1.
2.
7.1.1
7.1.2
CHANNEL SELECTION
7.1.3
VOLTAGE REFERENCE
7.1.4
CONVERSION CLOCK
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (dedicated internal RC oscillator)
Preliminary
DS41190A-page 39
PIC12F629/675
TABLE 7-1:
Device Frequency
Operation
ADCS2:ADCS0
20 MHz
5 MHz
4 MHz
1.25 MHz
000
100 ns(2)
400 ns(2)
500 ns(2)
1.6 s
2 TOSC
4 TOSC
100
200 ns(2)
800 ns(2)
1.0 s(2)
3.2 s
(2)
8 TOSC
001
400 ns
1.6 s
2.0 s
6.4 s
16 TOSC
101
800 ns(2)
3.2 s
4.0 s
12.8 s(3)
32 TOSC
010
1.6 s
6.4 s
8.0 s(3)
25.6 s(3)
(3)
(3)
64 TOSC
110
3.2 s
12.8 s
16.0 s
51.2 s(3)
A/D RC
x11
2 - 6 s(1,4)
2 - 6 s(1,4)
2 - 6 s(1,4)
2 - 6 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The A/D RC source has a typical TAD time of 4 s for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the
conversion will be performed during SLEEP.
7.1.5
STARTING A CONVERSION
Note:
7.1.6
FIGURE 7-2:
CONVERSION OUTPUT
(ADFM = 0)
ADRESL
MSB
LSB
bit 7
bit 0
bit 7
Unimplemented: Read as 0
MSB
(ADFM = 1)
bit 7
LSB
bit 0
Unimplemented: Read as 0
DS41190A-page 40
bit 0
Preliminary
bit 7
bit 0
PIC12F629/675
REGISTER 7-1:
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
VCFG
CHS1
CHS0
GO/DONE
ADON
bit 7
bit 0
bit 7
bit 6
bit 5-4
bit 3-2
bit 1
bit 0
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS41190A-page 41
PIC12F629/675
REGISTER 7-2:
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
ADCS2
ADCS1
ADCS0
ANS3
ANS2
ANS1
ANS0
bit 7
bit 0
bit 7
Unimplemented: Read as 0.
bit 6-4
bit 3-0
DS41190A-page 42
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
PIC12F629/675
7.2
7.2.1
7.2.2
The maximum recommended impedance for analog sources is 2.5 k. This value is calculated based
on the maximum leakage current of the input pin. The
leakage current is 100 nA max., and the analog input
voltage cannot be varied by more than 1/4 LSb or
250 V due to leakage. This places a requirement on
the input impedance of 250 V/100 nA = 2.5 k.
FIGURE 7-3:
Rs
Port Pin
CPIN
5 pF
VA
Sampling
Switch
VT = 0.6 V
RIC @ 1k
VT = 0.6 V
SS
RSS
ILEAKAGE
100 nA
CHOLD = 25 pF
VSS
Legend CPIN
= input capacitance
= threshold voltage
VT
ILEAKAGE = leakage current at the pin due to
various junctions
RIC
SS
CHOLD
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
Preliminary
VDD
6V
5V
4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch (RSS)
(kW)
DS41190A-page 43
PIC12F629/675
EQUATION 7-1:
T C
TC
------------------ ( R I C + R SS + R S )
------------------ ( R I C + R S S + R S )
1
1 ----------- = V REF 1 e C H O LD
V R EF V RE F = ( V R E F ) 1 e C HO L D
------------V H OL D =
V REF
4096
4096
1
T C = C HOLD ( 1k + R SS + R S )In -----------
4096
CHOLD = 25 pF
RS = 2.5 kW
EXAMPLE 7-1:
CALCULATING THE
MINIMUM REQUIRED
SAMPLE TIME
TACQ
TACQ
TC
TC
TC
TC
TC
TC
=
=
=
=
=
=
TACQ
5 s
+ 3.3 s
+ [(50C - 25C)(0.05 s / C)]
TACQ
TAC
=
=
8.3 s + 1.25 s
9.55 s
DS41190A-page 44
Preliminary
PIC12F629/675
7.3
TABLE 7-2:
Address
05h
7.4
Effects of RESET
Name
GPIO
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
GPIF
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
PIR1
EEIF
ADIF
CMIF
1Eh
ADRESH Most Significant 8 bits of the Left Shifted A/D result or 2 bits of the Right Shifted Result
1Fh
ADCON0
85h
TRISIO
PIE1
Value on
all other
RESETS
Bit 6
0Ch
8Ch
Value on:
POR,
BOR
Bit 7
VCFG
CHS1
CHS0
GO
TRIS5
TRIS4
TRIS3
TRIS2
TRIS1
EEIE
ADIE
CMIE
ADFM
ADON
TRIS0
9Eh
ADRESL Least Significant 2 bits of the Left Shifted A/D Result or 8 bits of the Right Shifted Result xxxx xxxx uuuu uuuu
9Fh
ANSEL
ADCS2
ADCS1
ADCS0
ANS3
ANS2
ANS1
ANS0
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D converter module.
Preliminary
DS41190A-page 45
PIC12F629/675
NOTES:
DS41190A-page 46
Preliminary
PIC12F629/675
8.0
EECON1
EECON2 (not a physically implemented register)
EEDATA
EEADR
Additional information on the Data EEPROM is available in the PICmicro Mid-Range Reference Manual,
(DS33023).
REGISTER 8-1:
R/W-0
R/W-0
R/W-0
R/W-0
EEDAT7
EEDAT6
EEDAT5
EEDAT4
EEDAT3
R/W-0
R/W-0
EEDAT2 EEDAT1
R/W-0
EEDAT0
bit 7
bit 7-0
bit 0
- n = Value at POR
REGISTER 8-2:
W = Writable bit
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EADR6
EADR5
EADR4
EADR3
EADR2
EADR1
EADR0
bit 7
bit 0
bit 7
bit 6-0
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS41190A-page 47
PIC12F629/675
8.1
EEADR
8.2
REGISTER 8-3:
U-0
U-0
U-0
R/W-x
R/W-0
R/S-0
R/S-0
WRERR
WREN
WR
RD
bit 7
bit 0
bit 7-4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
DS41190A-page 48
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
PIC12F629/675
8.3
EXAMPLE 8-1:
bsf
movlw
movwf
bsf
movf
8.4
8.5
;Bank 1
;
;Address to read
;EE Read
;Move data to W
EXAMPLE 8-3:
Required
Sequence
STATUS,RP0
bsf
bsf
bsf
bcf
movlw
movwf
movlw
movwf
bsf
bsf
WRITE VERIFY
bcf
:
bsf
movf
EXAMPLE 8-2:
WRITE VERIFY
STATUS,RP0
CONFIG_ADDR
EEADR
EECON1,RD
EEDATA,W
EECON1,RD
STATUS,RP0
EEDATA,W
xorwf EEDATA,W
btfss STATUS,Z
goto
WRITE_ERR
:
;Bank 0
;Any code
;Bank 1 READ
;EEDATA not changed
;from previous write
;YES, Read the
;value written
;Is data the same
;No, handle error
;Yes, continue
STATUS,RP0
EECON1,WREN
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
INTCON,GIE
8.5.1
;Bank 1
;Enable write
;Disable INTs
;Unlock write
;
;
;
;Start the write
;Enable INTS
MAXIMIZING ENDURANCE
8.6
PROTECTION AGAINST
SPURIOUS WRITE
brown-out
power glitch
software malfunction
Preliminary
DS41190A-page 49
PIC12F629/675
8.7
TABLE 8-1:
Address
0Ch
PIR1
9Ah
EEDATA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
EEIF
ADIF
CMIF
Bit 0
9Bh
EEADR
9Ch
EECON1
9Dh
WR
RD
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition.
Shaded cells are not used by Data EEPROM module.
Note 1: EECON2 is not a physical register.
DS41190A-page 50
Preliminary
PIC12F629/675
9.0
Preliminary
DS41190A-page 51
PIC12F629/675
9.1
Configuration Bits
Note:
REGISTER 9-1:
R/P-1 R/P-1
BG1
bit 13
bit 13-12
bit 11-9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
U-0
U-0
U-0
R/P-1
R/P-1
CPD
CP
BG0
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
DS41190A-page 52
W = Writable bit
1 = bit is set
Preliminary
PIC12F629/675
9.2
FIGURE 9-2:
Oscillator Configurations
9.2.1
OSCILLATOR TYPES
Note:
TABLE 9-1:
Mode
Freq
OSC1(C1)
OSC2(C2)
XT
455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
HS
8.0 MHz
16.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
TABLE 9-2:
XTAL
RF(3)
1:
2:
3:
RS(2)
Freq
OSC1(C1)
OSC2(C2)
LP
32 kHz
200 kHz
68 - 100 pF
15 - 30 pF
68 - 100 pF
15 - 30 pF
100 kHz
2 MHz
4 MHz
68 - 150 pF
15 - 30 pF
15 - 30 pF
150 - 200 pF
15 - 30 pF
15 - 30 pF
HS
8 MHz
10 MHz
20 MHz
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
PIC12F629/675
Mode
SLEEP
OSC2
C2(1)
XT
To Internal
Logic
C1
OSC1
(1)
OSC2(1)
FIGURE 9-1:
OSC1
Open
Additional information on oscillator configurations is available in the PICmicroTM MidRange Reference Manual, (DS33023).
9.2.2
Clock from
External System
PIC12F629/675
LP
Low Power Crystal
XT
Crystal/Resonator
HS
High Speed Crystal/Resonator
RC
External Resistor/Capacitor (2 modes)
INTOSC Internal Oscillator (2 modes)
EC
External Clock In
Note
Preliminary
DS41190A-page 53
PIC12F629/675
9.2.3
EXTERNAL CLOCK IN
9.2.5
For applications where a clock is already available elsewhere, users may directly drive the PIC12F629/675
provided that this external clock source meets the AC/
DC timing requirements listed in Section 12.0.
Figure 9-2 below shows how an external clock circuit
should be configured.
9.2.4
RC OSCILLATOR
For applications where precise timing is not a requirement, the RC oscillator option is available. The operation and functionality of the RC oscillator is dependent
upon a number of variables. The RC oscillator frequency is a function of:
9.2.5.1
FIGURE 9-3:
RC OSCILLATOR MODE
VDD
PIC12F629/675
REXT
GP5/OSC1/
CLKIN
Internal
Clock
Supply voltage
Resistor (REXT) and capacitor (CEXT) values
Operating temperature.
The oscillator frequency will vary from unit to unit due
to normal process parameter variation. The difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to account for the
tolerance of the external R and C components.
Figure 9-3 shows how the R/C combination is connected.
Erasing the device will also erase the preprogrammed internal calibration value for
the internal oscillator. The calibration value
must be saved prior to erasing part.
EXAMPLE 9-1:
bsf
call
movwf
bcf
9.2.6
CALIBRATING THE
INTERNAL OSCILLATOR
STATUS, RP0
3FFh
OSCCAL
STATUS, RP0
;Bank 1
;Get the cal value
;Calibrate
;Bank 0
CLKOUT
The PIC12F629/675 devices can be configured to provide a clock out signal in the INTOSC and RC oscillator
modes. When configured, the oscillator frequency
divided by four (FOSC/4) is output on the GP4/OSC2/
CLKOUT pin. FOSC/4 can be used for test purposes or
to synchronize other logic.
CEXT
VSS
FOSC/4
GP4/OSC2/CLKOUT
DS41190A-page 54
Preliminary
PIC12F629/675
9.3
RESET
Some registers are not affected in any RESET condition; their status is unknown on POR and unchanged in
any other RESET. Most other registers are reset to a
RESET state on:
Power-on Reset
MCLR Reset
WDT Reset
MCLR Reset during SLEEP
Brown-out Detect (BOD) Reset
FIGURE 9-4:
MCLR/
VPP pin
WDT
WDT
Module
SLEEP
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Detect
BODEN
OST/PWRT
OST
Chip_Reset
Enable PWRT
Enable OST
Note
1:
Preliminary
DS41190A-page 55
PIC12F629/675
9.3.1
9.3.3
MCLR
FIGURE 9-5:
RECOMMENDED MCLR
CIRCUIT
9.3.4
VDD
PIC12F629/675
R1
1 k (or greater)
C1
0.1 f
(optional, not critical)
9.3.5
POWER-ON RESET (POR)
The POR circuit does not produce an internal RESET when VDD declines.
DS41190A-page 56
MCLR
9.3.2
Preliminary
PIC12F629/675
FIGURE 9-6:
BROWN-OUT SITUATIONS
VDD
VBOR
Internal
RESET
72 ms(1)
VDD
VBOR
Internal
RESET
<72 ms
72 ms(1)
VDD
VBOR
Internal
RESET
72 ms(1)
9.3.6
TIME-OUT SEQUENCE
9.3.7
Preliminary
DS41190A-page 57
PIC12F629/675
TABLE 9-3:
Brown-out Reset
Oscillator Configuration
Wake-up
from SLEEP
PWRTE = 0
PWRTE = 1
PWRTE = 0
PWRTE = 1
XT, HS, LP
TPWRT +
1024TOSC
1024TOSC
TPWRT +
1024TOSC
1024TOSC
1024TOSC
TPWRT
TPWRT
TABLE 9-4:
POR
BOD
TO
PD
Power-on Reset
Brown-out Detect
WDT Reset
WDT Wake-up
TABLE 9-5:
Address
Value on all
other
RESETS(1)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
03h
STATUS
IRP
RP1
RPO
TO
PD
DC
8Eh
PCON
POR
BOD
Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during
normal operation.
TABLE 9-6:
STATUS
Register
PCON
Register
Power-on Reset
000h
0001 1xxx
---- --0x
000h
000u uuuu
---- --uu
000h
0001 0uuu
---- --uu
Condition
WDT Reset
WDT Wake-up
Brown-out Detect
Interrupt Wake-up from SLEEP
000h
0000 uuuu
---- --uu
PC + 1
uuu0 0uuu
---- --uu
000h
0001 1uuu
---- --10
uuu1 0uuu
---- --uu
PC + 1
(1)
DS41190A-page 58
Preliminary
PIC12F629/675
TABLE 9-7:
Register
Address
Power-on
Reset
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF
00h/80h
TMR0
01h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
02h/82h
0000 0000
0000 0000
PC + 1(3)
STATUS
03h/83h
0001 1xxx
000q quuu(4)
uuuq quuu(4)
FSR
04h/84h
xxxx xxxx
uuuu uuuu
uuuu uuuu
GPIO
05h
--xx xxxx
--uu uuuu
--uu uuuu
PCLATH
0Ah/8Ah
---0 0000
---0 0000
---u uuuu
INTCON
0Bh/8Bh
0000 0000
0000 000u
uuuu uuqq(2)
PIR1
0Ch
00-- 0--0
00-- 0--0
qq-- q--q(2,5)
T1CON
10h
-000 0000
-uuu uuuu
-uuu uuuu
CMCON
19h
-0-0 0000
-0-0 0000
-u-u uuuu
ADRESH
1Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
1Fh
00-- 0000
00-- 0000
uu-- uuuu
OPTION_REG
81h
1111 1111
1111 1111
uuuu uuuu
TRISIO
85h
--11 1111
--11 1111
--uu uuuu
PIE1
8Ch
00-- 0--0
00-- 0--0
uu-- u--u
PCON
8Eh
---- --0x
---- --uu(1,6)
---- --uu
OSCCAL
90h
1000 00--
1000 00--
uuuu uu--
WPU
95h
--11 -111
--11 -111
uuuu uuuu
IOCB
96h
--00 0000
--00 0000
--uu uuuu
VRCON
99h
0-0- 0000
0-0- 0000
u-u- uuuu
EEDATA
9Ah
0000 0000
0000 0000
uuuu uuuu
EEADR
9Bh
-000 0000
-000 0000
-uuu uuuu
EECON1
9Ch
---- x000
---- q000
---- uuuu
EECON2
9Dh
---- ----
---- ----
---- ----
ADRESL
9Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
ANSEL
9Fh
-000 1111
-000 1111
-uuu uuuu
Legend:
Note 1:
2:
3:
Preliminary
DS41190A-page 59
PIC12F629/675
FIGURE 9-7:
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal RESET
FIGURE 9-8:
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal RESET
FIGURE 9-9:
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal RESET
DS41190A-page 60
Preliminary
PIC12F629/675
FIGURE 9-10:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
FIGURE 9-12:
VDD
VDD
VDD
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
VDD
R1
Q1
MCLR
R
R2
R1
40k
PIC12F629/675
MCLR
PIC12F629/675
VDD x
R1
R1 + R2
= 0.7V
FIGURE 9-13:
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 3
VDD
FIGURE 9-11:
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
VDD
VDD
RST
33k
Vss
PIC12F629/675
MCLR
PIC12F629/675
MCLR
40k
VDD
MCP809
VDD
10k
Bypass
Capacitor
Preliminary
DS41190A-page 61
PIC12F629/675
9.4
Interrupts
DS41190A-page 62
Preliminary
PIC12F629/675
FIGURE 9-14:
INTERRUPT LOGIC
IOC-GP0
IOCB0
IOC-GP1
IOCB1
IOC-GP2
IOCB2
IOC-GP3
IOCB3
IOC-GP4
IOCB4
IOC-GP5
IOCB5
T0IF
T0IE
INTF
INTE
GPIF
GPIE
PEIF
PEIE
TMR1IF
TMR1IE
CMIF
CMIE
ADIF
ADIE
(1)
Interrupt to CPU
GIE
EEIF
EEIE
Note 1: PIC12F675 only.
Preliminary
DS41190A-page 63
PIC12F629/675
9.4.1
GP2/INT INTERRUPT
9.4.3
GPIO INTERRUPT
9.4.4
COMPARATOR INTERRUPT
9.4.5
9.4.2
TMR0 INTERRUPT
FIGURE 9-15:
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT 3
4
INT pin
INTF Flag
(INTCON<1>)
Interrupt Latency 2
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
Instruction
Fetched
Inst (PC)
Instruction
Executed
Inst (PC-1)
PC+1
PC+1
Inst (PC+1)
Inst (PC)
Dummy Cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
DS41190A-page 64
Preliminary
PIC12F629/675
TABLE 9-8:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Value on all
other
RESETS
Bit 0
Value on
POR Reset
GPIF
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
0Ch
PIR1
EEIF
ADIF
CMIF
8Ch
PIE1
EEIE
ADIE
CMIE
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition.
Shaded cells are not used by the Interrupt module.
9.5
EXAMPLE 9-2:
MOVWF
W_TEMP
SWAPF
BCF
STATUS,W
STATUS,RP0
MOVWF STATUS_TEMP
:
:(ISR)
:
SWAPF STATUS_TEMP,W;swap STATUS_TEMP register into
W, sets bank to original state
MOVWF STATUS
;move W into STATUS register
SWAPF W_TEMP,F
;swap W_TEMP
SWAPF W_TEMP,W
;swap W_TEMP into W
9.6.1
9.6
WDT PERIOD
9.6.2
WDT PROGRAMMING
CONSIDERATIONS
Preliminary
DS41190A-page 65
PIC12F629/675
FIGURE 9-16:
CLKOUT
(= FOSC/4)
Data Bus
0
8
1
SYNC 2
Cycles
1
T0CKI
pin
0
T0CS
T0SE
TMR0
0
Set Flag bit T0IF
on Overflow
8-bit
Prescaler
PSA
1
8
PSA
PS0 - PS2
WDT
Time-Out
Watchdog
Timer
PSA
WDTE
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the Option register.
TABLE 9-9:
Address
Bit 7
Bit 6
81h
2007h
Config. bits
CP
Value on all
other
RESETS
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR Reset
T0CS
T0SE
PSA
PS2
PS1
PS0
F0SC2
F0SC1
F0SC0
Legend: u = Unchanged, shaded cells are not used by the Watchdog Timer.
DS41190A-page 66
Preliminary
PIC12F629/675
9.7
The first event will cause a device RESET. The two latter events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be used to determine the cause of device RESET.
The PD bit, which is set on power-up, is cleared when
SLEEP is invoked. TO bit is cleared if WDT Wake-up
occurred.
When the SLEEP instruction is being executed, the
next instruction (PC + 1) is pre-fetched. For the device
to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up
is regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction, then branches to the interrupt
address (0004h). In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have an NOP after the SLEEP instruction.
Note:
9.7.1
FIGURE 9-17:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
Instruction
Fetched
Instruction
Executed
Note
1:
2:
3:
4:
Inst(PC) = SLEEP
Inst(PC - 1)
PC+1
PC+2
PC+2
Inst(PC + 1)
Inst(PC + 1)
Dummy cycle
0004h
0005h
Inst(0004h)
Inst(PC + 2)
SLEEP
PC + 2
Inst(0005h)
Dummy cycle
Inst(0004h)
Preliminary
DS41190A-page 67
PIC12F629/675
9.8
Code Protection
9.9
The entire data EEPROM and FLASH program memory will be erased when the
code protection is turned off. The INTRC
calibration data is also erased. See
PIC12F629/675 Programming Specification for more information.
FIGURE 9-18:
ID Locations
9.10
External
Connector
Signals
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
To Normal
Connections
PIC12F629/675
+5V
VDD
0V
VSS
VPP
GP3/MCLR/VPP
CLK
GP0
Data I/O
GP1
power
ground
programming voltage
VDD
To Normal
Connections
DS41190A-page 68
Preliminary
PIC12F629/675
10.0
TABLE 10-1:
Field
PC
Program Counter
TO
Time-out bit
PD
Power-down bit
FIGURE 10-1:
All instruction examples use the format 0xhh to represent a hexadecimal number, where h signifies a
hexadecimal digit.
10.1
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
OPCODE
0
k (literal)
READ-MODIFY-WRITE
OPERATIONS
Description
Note:
OPCODE FIELD
DESCRIPTIONS
Preliminary
13
11
OPCODE
10
0
k (literal)
DS41190A-page 69
PIC12F629/675
TABLE 10-2:
Mnemonic,
Operands
14-Bit Opcode
Description
Cycles
MSb
LSb
Status
Affected
Notes
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
1,2
1,2
3
3
k
k
k
k
k
k
k
k
k
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven low by an external
device, the data will be written back with a 0.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note:
Additional information on the mid-range instruction set is available in the PICmicro Mid-Range MCU
Family Reference Manual (DS33023).
DS41190A-page 70
Preliminary
PIC12F629/675
10.2
Instruction Descriptions
ADDLW
BCF
Bit Clear f
Syntax:
[label] ADDLW
Syntax:
[label] BCF
Operands:
0 k 255
Operands:
Operation:
(W) + k (W)
0 f 127
0b7
Status Affected:
C, DC, Z
Operation:
0 (f<b>)
Description:
Status Affected:
None
Description:
ADDWF
Add W and f
BSF
Bit Set f
Syntax:
[label] ADDWF
Syntax:
[label] BSF
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
0b7
Operation:
Operation:
1 (f<b>)
Status Affected:
C, DC, Z
Status Affected:
None
Description:
Description:
ANDLW
BTFSS
Syntax:
[label] ANDLW
Syntax:
Operands:
0 k 255
Operands:
Operation:
0 f 127
0b<7
Status Affected:
Operation:
skip if (f<b>) = 1
Description:
Status Affected:
None
Description:
BTFSC
Syntax:
f,d
f,b
f,b
ANDWF
AND W with f
Syntax:
[label] ANDWF
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
0b7
Operation:
Operation:
skip if (f<b>) = 0
Status Affected:
Status Affected:
None
Description:
Description:
f,d
Preliminary
DS41190A-page 71
PIC12F629/675
CALL
Call Subroutine
CLRWDT
Syntax:
[ label ] CALL k
Syntax:
[ label ] CLRWDT
Operands:
0 k 2047
Operands:
None
Operation:
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
Operation:
Status Affected:
None
00h WDT
0 WDT prescaler,
1 TO
1 PD
Description:
Status Affected:
TO, PD
Description:
Clear f
COMF
Complement f
CLRF
Syntax:
[label] CLRF
Syntax:
[ label ] COMF
Operands:
0 f 127
Operands:
Operation:
00h (f)
1Z
0 f 127
d [0,1]
Operation:
(f) (destination)
Status Affected:
Status Affected:
Description:
Description:
CLRW
Clear W
DECF
Decrement f
Syntax:
[ label ] CLRW
Syntax:
Operands:
None
Operands:
Operation:
00h (W)
1Z
0 f 127
d [0,1]
Operation:
(f) - 1 (destination)
Status Affected:
Status Affected:
Description:
Description:
Decrement register f. If d is 0,
the result is stored in the W
register. If d is 1, the result is
stored back in register f.
DS41190A-page 72
Preliminary
f,d
PIC12F629/675
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (destination);
skip if result = 0
Operation:
(f) + 1 (destination),
skip if result = 0
Status Affected:
None
Status Affected:
None
Description:
Description:
GOTO
Unconditional Branch
IORLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 2047
Operands:
0 k 255
Operation:
k PC<10:0>
PCLATH<4:3> PC<12:11>
Operation:
Status Affected:
Status Affected:
None
Description:
Description:
INCF
Increment f
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) + 1 (destination)
Operation:
Status Affected:
Status Affected:
Description:
Description:
GOTO k
INCF f,d
Preliminary
INCFSZ f,d
IORLW k
IORWF
f,d
DS41190A-page 73
PIC12F629/675
MOVF
Move f
NOP
Syntax:
[ label ]
Syntax:
Operands:
0 f 127
d [0,1]
Operation:
No operation
Operation:
(f) (destination)
Status Affected:
None
Status Affected:
Description:
No operation.
Description:
MOVLW
Move Literal to W
RETFIE
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 255
Operands:
None
Operation:
k (W)
Operation:
TOS PC,
1 GIE
MOVLW k
[ label ]
Operands:
MOVF f,d
No Operation
None
NOP
RETFIE
Status Affected:
None
Description:
Status Affected:
None
MOVWF
Move W to f
RETLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
Operands:
0 k 255
Operation:
(W) (f)
Operation:
Status Affected:
None
k (W);
TOS PC
Description:
Status Affected:
None
Description:
DS41190A-page 74
MOVWF
Preliminary
RETLW k
PIC12F629/675
RLF
SLEEP
Syntax:
[ label ] RLF
Syntax:
[ label ] SLEEP
Operands:
0 f 127
d [0,1]
Operands:
None
Operation:
Operation:
Status Affected:
Description:
00h WDT,
0 WDT prescaler,
1 TO,
0 PD
Status Affected:
TO, PD
Description:
f,d
Register f
RETURN
SUBLW
Syntax:
[ label ]
Syntax:
[ label ] SUBLW k
Operands:
None
Operands:
0 k 255
Operation:
TOS PC
Operation:
k - (W) (W)
Status Affected:
None
Description:
Description:
RRF
SUBWF
Subtract W from f
Syntax:
[ label ]
Syntax:
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
Operation:
Status Affected:
C
The contents of register f are
rotated one bit to the right through
the Carry Flag. If d is 0, the result
is placed in the W register. If d is
1, the result is placed back in
register f.
Status
Affected:
C, DC, Z
Description:
Description:
RETURN
RRF f,d
Register f
Preliminary
DS41190A-page 75
PIC12F629/675
SWAPF
Swap Nibbles in f
XORWF
Exclusive OR W with f
Syntax:
Syntax:
[label]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Operation:
Status Affected:
Status Affected:
None
Description:
Description:
XORLW
[label]
f,d
Syntax:
XORWF
XORLW k
Operands:
0 k 255
Operation:
Status Affected:
Description:
DS41190A-page 76
Preliminary
PIC12F629/675
11.0
DEVELOPMENT SUPPORT
11.1
11.2
MPASM Assembler
11.3
Preliminary
DS41190A-page 77
PIC12F629/675
11.4
11.6
11.5
11.7
The MPLAB SIM software simulator allows code development in a PC-hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user-defined key press, to any of the pins. The
execution can be performed in single step, execute
until break, or trace mode.
The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and the MPLAB C18 C compilers and the MPASM assembler. The software simulator
offers the flexibility to develop and debug code outside of
the laboratory environment, making it an excellent multiproject software development tool.
DS41190A-page 78
Preliminary
PIC12F629/675
11.8
Microchips In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is
based on the FLASH PICmicro MCUs and can be used
to develop for this and other PICmicro microcontrollers.
The MPLAB ICD utilizes the in-circuit debugging capability built into the FLASH devices. This feature, along
with Microchips In-Circuit Serial ProgrammingTM protocol, offers cost-effective in-circuit FLASH debugging
from the graphical user interface of the MPLAB
Integrated Development Environment. This enables a
designer to develop and debug source code by watching variables, single-stepping and setting break points.
Running at full speed enables testing hardware in realtime.
11.9
Preliminary
DS41190A-page 79
PIC12F629/675
11.13 PICDEM 3 Low Cost PIC16CXXX
Demonstration Board
The PICDEM 3 demonstration board is a simple demonstration board that supports the PIC16C923 and
PIC16C924 in the PLCC package. It will also support
future 44-pin PLCC microcontrollers with an LCD Module. All the necessary hardware and software is
included to run the basic demonstration programs. The
user can program the sample microcontrollers provided with the PICDEM 3 demonstration board on a
PRO MATE II device programmer, or a PICSTART Plus
development programmer with an adapter socket, and
easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 3 demonstration
board to test firmware. A prototype area has been provided to the user for adding hardware and connecting it
to the microcontroller socket(s). Some of the features
include a RS-232 interface, push button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM 3 demonstration board is a LCD panel, with 4
commons and 12 segments, that is capable of displaying time, temperature and day of the week. The
PICDEM 3 demonstration board provides an additional
RS-232 interface and Windows software for showing
the demultiplexor LCD signals on a PC. A simple serial
interface allows the user to construct a hardware
demultiplexer for the LCD signals.
DS41190A-page 80
Preliminary
Software Tools
PIC18CXX2
9
9 9 9
9
9
9
PIC17C7XX
9 9
9 9
9
9
PIC17C4X
9 9
9 9
9
9
PIC16C9XX
9
9 9
9
9
PIC16F8XX
9
9 9
9
9
PIC16C8X
9
9 9
9
9
9
PIC16C7XX
9
9 9
9
9
9
PIC16C7X
9
9 9
9
9
9
PIC16F62X
9
9 9
PIC16CXXX
9
9 9
9
PIC16C6X
9
9 9
9
PIC16C5X
9
9 9
9
PIC14000
9
9 9
PIC12CXXX
9
9 9
9
9
9
9
9
9
9
9
Preliminary
9
MCRFXXX
9 9
24CXX/
25CXX/
93CXX
9 9
9
9
9
9
MCP2510
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77.
** Contact Microchip Technology Inc. for availability date.
Development tool is available on select devices.
PICDEMTM 17 Demonstration
Board
9
9
PICDEMTM 3 Demonstration
Board
9
9
PICDEMTM 2 Demonstration
Board
HCSXXX
PICDEMTM 1 Demonstration
Board
9
**
PRO MATE II
Universal Device Programmer
**
**
9 9 9
PIC18FXXX
MPASMTM Assembler/
MPLINKTM Object Linker
TABLE 11-1:
MPLAB Integrated
Development Environment
PIC12F629/675
DS41190A-page 81
PIC12F629/675
NOTES:
DS41190A-page 82
Preliminary
PIC12F629/675
12.0
ELECTRICAL SPECIFICATIONS
Note:
Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latchup.
Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR pin, rather than
pulling this pin directly to VSS
Preliminary
DS41190A-page 83
PIC12F629/675
FIGURE 12-1:
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.0
0
10
12
16
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 12-2:
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.0
0
10
12
16
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
DS41190A-page 84
Preliminary
PIC12F629/675
FIGURE 12-3:
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.2
2.0
0
10
12
16
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 12-4:
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.0
0
12
16
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
Preliminary
DS41190A-page 85
PIC12F629/675
12.1
DC CHARACTERISTICS
Param
No.
Sym
VDD
Characteristic
Min
Supply Voltage
Conditions
FOSC < = 4 MHz:
PIC12F629/675 with A/D off
PIC12F675 with A/D on, 0C to 85C
PIC12F675 with A/D on, -40C to 85C
4 MHZ < FOSC < = 10 MHz
2.0
2.2
2.5
3.0
4.5
D001
D001A
D001B
D001C
D001D
5.5
5.5
5.5
5.5
5.5
V
V
V
V
V
1.5*
D002
VDR
D003
VPOR
VSS
D004
SVDD
0.05*
D005
VBOR
2.0
0.4
2.0
mA
D011
20
48
D012
0.9
mA
D013
5.2
15
mA
D010
IDD
IPD
Supply
Current(2,3)
D020
0.9
TBD
D021
153
D022
TBD TBD
D023
D024
TBD TBD
D025
TBD TBD
D026
18
TBD
DS41190A-page 86
Preliminary
PIC12F629/675
12.2
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
Conditions
D001A VDD
Supply Voltage
4.5
5.5
-40C to +125C
D002
VDR
1.5*
D003
VPOR
VSS
D004
SVDD
0.05*
2.0
0.9
mA
5.2
15
mA
D005
VBOR
D012
IDD
Supply Current(2,3)
D013
IPD
D020
TBD TBD
D021
TBD TBD
D022
TBD TBD
D023
TBD TBD
D024
TBD TBD
D025
TBD TBD
D026
12
TBD
Preliminary
DS41190A-page 87
PIC12F629/675
12.3
DC CHARACTERISTICS
Param
Sym
No.
VIL
D030
D030A
D031
D032
D033
D033A
VIH
D040
D040A
D041
D042
D043
D043A
D043B
D070 IPUR
D060
IIL
D060A
D060B
D061
D063
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
with Schmitt Trigger buffer
MCLR, OSC1 (RC mode)
OSC1 (XT and LP modes)
OSC1 (HS mode)
Input High Voltage
I/O ports
with TTL buffer
VOL
D090
D092
VOH
Typ
Max
Units
VSS
VSS
VSS
VSS
VSS
VSS
0.8
0.15 VDD
0.2 VDD
0.2 VDD
0.3
0.3 VDD
V
V
V
V
V
V
VDD
VDD
VDD
VDD
V
V
V
V
V
A
(Note 1)
(Note 1)
250
VDD
VDD
VDD
400*
Input Leakage
I/O ports
TBD
TBD
5
5
A
A
A
A
0.6
0.6
V
V
VDD-0.7
VDD-0.7
V
V
Conditions
(Note 1)
(Note 1)
2.0
(0.25 VDD+0.8)
with Schmitt Trigger buffer
0.8VDD
MCLR, GP2/AN2/T0CKI/
0.8VDD
INT/COUT
OSC1 (XT and LP modes)
1.6
OSC1 (HS mode)
0.7VDD
OSC1 (RC mode)
0.9VDD
GPIO Weak Pull-up Current
50*
Current(3)
Analog inputs
VREF
MCLR(2)
OSC1
D080
D083
Min
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use
an external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
DS41190A-page 88
Preliminary
PIC12F629/675
12.3
DC CHARACTERISTICS
Param
No.
Sym
D100
COSC2
D101
D101A
D101B
CIO
CAN
CVR
D120
D120A
D121
ED
ED
VDRW
D122
TDEW
D130
D130A
D131
EP
EP
VPR
D132
D133
Characteristic
Capacitive Loading Specs
on Output Pins
OSC2 pin
Min
Typ
Max
Units
Conditions
15*
pF
50*
TBD
TBD
pF
pF
pF
100K
10K
VMIN
1M
100K
5.5
4.5
5.5
8
10K
1000
VMIN
100K
10K
5.5
4.5
5.5
VPEW VDD for Erase/Write
TPEW Erase/Write cycle time
2
4
* These parameters are characterized but not tested.
Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Preliminary
DS41190A-page 89
PIC12F629/675
12.4
FIGURE 12-5:
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
Hi-impedance
LOAD CONDITIONS
Load Condition 1
Load Condition 2
VDD/2
RL
CL
Pin
CL
Pin
VSS
VSS
RL = 464
CL = 50 pF
15 pF
DS41190A-page 90
Preliminary
PIC12F629/675
12.5
FIGURE 12-6:
Q1
Q2
Q3
Q4
Q1
OSC1
1
2
CLKOUT
TABLE 12-1:
Param
No.
Sym
FOSC
Min
Typ
Max
Units
DC
DC
DC
DC
5
200
4
20
20
200
kHz
MHz
MHz
MHz
kHz
MHz
MHz
MHz
MHz
LP osc mode
XT mode
HS mode
EC mode
LP osc mode
INTRC mode
RC osc mode
XT osc mode
HS osc mode
200
s
ns
ns
ns
s
ns
ns
ns
ns
LP osc mode
HS osc mode
EC osc mode
XT osc mode
LP osc mode
INTRC mode
RC osc mode
XT osc mode
HS osc mode
Oscillator Frequency(1)
TBD
0.1
1
1
TOSC
Oscillator Period(1)
5
50
50
250
5
250
250
50
TCY
250
4
4
20
TBD
10,000
1,000
Conditions
200
TCY
DC
ns TCY = 4/FOSC
3
TosL,
2*
50*
ns LP oscillator
TosF External CLKIN Fall
25*
ns XT oscillator
15*
ns HS oscillator
* These parameters are characterized but not tested.
Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at min values with an external
clock applied to OSC1 pin. When an external clock input is used, the max cycle time limit is DC (no clock)
for all devices.
Preliminary
DS41190A-page 91
PIC12F629/675
TABLE 12-2:
AC Characteristics
Param
No.
Min*
Typ(1)
Max*
Units
3.92
4.00
4.08
Sym
3.80
4.00
4.20
Conditions
DS41190A-page 92
Preliminary
PIC12F629/675
FIGURE 12-7:
Q4
Q2
Q3
OSC1
11
10
22
23
CLKOUT
13
12
19
14
18
16
I/O pin
(Input)
15
17
I/O pin
(Output)
New Value
Old Value
20, 21
TABLE 12-3:
Param
No.
Characteristic
10
TosH2ckL
Min
Max
Units
OSC1 to CLKOUT
Typ
75
200
ns
Conditions
(Note 1)
11
TosH2ckH
OSC1 to CLKOUT
75
200
ns
(Note 1)
12
TckR
35
100
ns
(Note 1)
13
TckF
35
100
ns
(Note 1)
14
TckL2ioV
20
ns
(Note 1)
15
TioV2ckH
TOSC + 200 ns
ns
(Note 1)
16
TckH2ioI
(Note 1)
ns
50
150 *
ns
300
ns
100
ns
17
TosH2ioV
18
TosH2ioI
19
TioV2osH
ns
20
TioR
10
40
ns
21
TioF
10
40
ns
22
Tinp
25
ns
23
Trbp
TCY
ns
Preliminary
DS41190A-page 93
PIC12F629/675
FIGURE 12-8:
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
Reset
34
31
34
I/O Pins
FIGURE 12-9:
VDD
BVDD
35
72 ms time out(1)
DS41190A-page 94
Preliminary
PIC12F629/675
TABLE 12-4:
Param
No.
Characteristic
Min
Typ
Max
Units
Conditions
30
TMCL
2
TBD
TBD
TBD
s
ms
31
TWDT
7*
TBD
18
TBD
33*
TBD
ms
ms
32
TOST
1024TOSC
33*
TPWRT
28*
TBD
72
TBD
132*
TBD
ms
ms
34
TIOZ
2.0
BVDD
2.0
2.1
Brown-out Hysteresis
TBD
100*
35
TBOR
Preliminary
DS41190A-page 95
PIC12F629/675
FIGURE 12-10:
T0CKI
40
41
42
T1CKI
45
46
48
47
TMR0 or
TMR1
TABLE 12-5:
Param
No.
Sym
40*
TT0H
Characteristic
With Prescaler
TT0L
41*
No Prescaler
With Prescaler
42*
TT0P
T0CKI Period
45*
TT1H
Max
0.5 TCY + 20
ns
10
ns
0.5 TCY + 20
ns
10
ns
ns
0.5 TCY + 20
ns
15
No Prescaler
Typ
Greater of:
20 or TCY + 40
N
Min
Units
ns
TT1L
30
ns
15
ns
30
ns
Synchronous
Greater of:
30 or TCY + 40
N
ns
Synchronous, No Prescaler
Synchronous,
with Prescaler
TT1P
47*
T1CKI Input
Period
Asynchronous
FT1
48
60
N = prescale value
(2, 4, ..., 256)
ns
0.5 TCY + 20
Asynchronous
46*
Conditions
ns
DC
200*
kHz
2 TOSC*
7 TOSC*
N = prescale value
(1, 2, 4, 8)
DS41190A-page 96
Preliminary
PIC12F629/675
TABLE 12-6:
COMPARATOR SPECIFICATIONS
Comparator Specifications
Sym
Characteristics
Typ
Max
Units
VOS
5.0
10
mV
VCM
VDD - 1.5
CMRR
+55*
db
150
400*
ns
10*
Comments
Response Time
TRT
(1)
TABLE 12-7:
Characteristics
Typ
Max
Units
Comments
Resolution
VDD/24*
VDD/32
LSb
LSb
Absolute Accuracy
1/4*
1/2*
LSb
LSb
2k*
Settling Time(1)
10*
Preliminary
DS41190A-page 97
PIC12F629/675
TABLE 12-8:
Param
No.
Sym
Min
Typ
Max
Units
Conditions
A01
NR
Resolution
10 bits
bit
A02
EABS
TBD
LSb
A03
EIL
Integral Error
TBD
LSb
VREF = 3.0V
A04
EDL
Differential Error
TBD
LSb
A05
EFS
2.2*
5.5*
A06
EOFF
Offset Error
TBD
LSb
VREF = 3.0V
A07
EGN
Gain Error
TBD
LSb
VREF = 3.0V
A10
Monotonicity
guaranteed(3)
A21
VREF
Reference V High
(VDD or VREF)
VSS
VDD
A25
VAIN
VSS
VREF
A30
ZAIN
Recommended
Impedance of Analog
Voltage Source
2.5
A50
IREF
10
1000
10
VREF = 3.0V
Note 1: When A/D is off, it will not consume any current other than leakage current. The power-down current spec includes any such
leakage from the A/D module.
2: VREF current is from External VREF or VDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
DS41190A-page 98
Preliminary
PIC12F629/675
FIGURE 12-11:
BSF ADCON0, GO
134
1 TCY
(TOSC/2)(1)
131
Q4
130
A/D CLK
9
A/D DATA
0
NEW_DATA
OLD_DATA
ADRES
1 TCY
ADIF
GO
SAMPLE
DONE
SAMPLING STOPPED
132
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
TABLE 12-9:
Param
No.
Sym
Min
Typ
Max
Units
Conditions
A/D Internal RC
Oscillator Period
131
TCNV
Conversion Time
(not including
Acquisition Time)(1)
132
TACQ
Acquisition Time
134
TGO
Q4 to A/D Clock
Start
3.0*
6.0
9.0*
4.0
6.0*
At VDD = 5.0V
11
TAD
(Note 2)
11.5
5*
TAD
2.0*
130
TAD
1.6
3.0*
130
TOSC/2
Preliminary
DS41190A-page 99
PIC12F629/675
FIGURE 12-12:
BSF ADCON0, GO
134
(TOSC/2 + TCY)(1)
1 TCY
131
Q4
130
A/D CLK
9
A/D DATA
NEW_DATA
OLD_DATA
ADRES
ADIF
1 TCY
GO
DONE
SAMPLE
SAMPLING STOPPED
132
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
Sym
Characteristic
Min
Typ
Max
Units
1.6
VREF 3.0V
3.0*
3.0*
6.0
9.0*
2.0*
4.0
6.0*
At VDD = 5.0V
11
TAD
(Note 2)
11.5
5*
TOSC/2 + TCY
130
TAD
130
TAD
A/D Internal RC
Oscillator Period
131
TCNV
Conversion Time
(not including
Acquisition Time)(1)
132
TACQ
Acquisition Time
134
TGO
Q4 to A/D Clock
Start
Conditions
DS41190A-page 100
Preliminary
PIC12F629/675
13.0
PACKAGING INFORMATION
13.1
12F629-I
/017
0215
8-Lead SOIC
Example
XXXXXXXX
XXXXYYWW
NNN
12F629-E
/0215
017
Example
8-Lead MLF-S
XXXXXXX
XXXXXXX
XXYYWW
NNN
12F629
-E/021
0215
017
Legend:
Note:
XX...X
Y
YY
WW
NNN
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
Preliminary
DS41190A-page 101
PIC12F629/675
13.2
Package Details
E1
D
2
n
A2
A1
B1
p
eB
Units
Dimension Limits
n
p
Number of Pins
Pitch
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
Significant Characteristic
A
A2
A1
E
E1
D
L
c
B1
B
eB
MIN
.140
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
5
INCHES*
NOM
MAX
8
.100
.155
.130
.170
.145
.313
.250
.373
.130
.012
.058
.018
.370
10
10
.325
.260
.385
.135
.015
.070
.022
.430
15
15
MILLIMETERS
NOM
8
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
9.14
9.46
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
MAX
4.32
3.68
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010 (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
DS41190A-page 102
Preliminary
PIC12F629/675
8-Lead Plastic Small Outline (SN) Narrow, 150 mil (SOIC)
E
E1
D
2
B
45
c
A2
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
Significant Characteristic
A
A2
A1
E
E1
D
h
L
c
B
MIN
.053
.052
.004
.228
.146
.189
.010
.019
0
.008
.013
0
0
A1
INCHES*
NOM
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
.009
.017
12
12
MAX
.069
.061
.010
.244
.157
.197
.020
.030
8
.010
.020
15
15
MILLIMETERS
NOM
8
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
6.02
3.71
3.91
4.80
4.90
0.25
0.38
0.48
0.62
0
4
0.20
0.23
0.33
0.42
0
12
0
12
MIN
MAX
1.75
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
0.25
0.51
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010 (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
Preliminary
DS41190A-page 103
PIC12F629/675
8-Lead Plastic Micro Leadframe Package (MF) 6x5 mm Body (MLF-S)
E
p
E1
n
R
D1
D2
PIN 1
ID
EXPOSED
METAL
PADS
E2
TOP VIEW
BOTTOM VIEW
A2
A3
A
A1
INCHES
Units
Dimension Limits
Number of Pins
MILLIMETERS*
NOM
MIN
MAX
NOM
MIN
MAX
8
Pitch
Overall Height
.033
.039
0.85
1.00
A2
.026
.031
0.65
0.80
Standoff
A1
.0004
.002
0.01
0.05
Base Thickness
A3
.008 REF.
0.20 REF.
4.92 BSC
.050 BSC
.000
E
E1
.184 BSC
E2
0.00
.194 BSC
1.27 BSC
Overall Length
Overall Width
.152
.158
4.67 BSC
.163
3.85
4.00
4.15
5.99 BSC
.236 BSC
D1
D2
.085
.091
.097
2.16
2.31
2.46
Lead Width
.014
.016
.019
0.35
0.40
0.47
Lead Length
.020
.024
.030
0.50
0.60
0.75
.226 BSC
5.74 BSC
.356
.014
12
12
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010 (0.254mm) per side.
JEDEC equivalent: pending
Drawing No. C04-113
DS41190A-page 104
Preliminary
PIC12F629/675
8-Lead Plastic Micro Leadframe Package (MF) 6x5 mm Body (MLF-S)
M
SOLDER
MASK
PACKAGE
EDGE
L
Units
Pitch
Dimension Limits
p
INCHES
MIN
NOM
MILLIMETERS*
MAX
MIN
.050 BSC
NOM
MAX
1.27 BSC
Pad Width
.014
.016
.019
0.35
0.40
Pad Length
.020
.024
.030
0.50
0.60
.005
.006
0.13
0.47
0.75
0.15
*Controlling Parameter
Drawing No. C04-2113
Preliminary
DS41190A-page 105
PIC12F629/675
NOTES:
DS41190A-page 106
Preliminary
PIC12F629/675
APPENDIX A:
DATA SHEET
REVISION HISTORY
Revision A
APPENDIX B:
DEVICE
DIFFERENCES
TABLE B-1:
DEVICE DIFFERENCES
Feature
Preliminary
PIC12F675
A/D
PIC12F629
No
Yes
DS41190A-page 107
PIC12F629/675
APPENDIX C:
DEVICE MIGRATIONS
APPENDIX D:
MIGRATING FROM
OTHER PICmicro
DEVICES
D.1
PIC12C67X to PIC12F6XX
See
Microchip
website
(www.microchip.com).
Note:
DS41190A-page 108
Preliminary
for
availability
PIC12F629/675
APPENDIX E:
DEVELOPMENT
TOOL VERSION
REQUIREMENTS
TBD
MPLAB
SIMULATOR:
TBD
MPLAB
ICE 3000:
TBD
TBD
PICSTART Plus:
TBD
TM
TBD
MPASM
Assembler:
Note:
Preliminary
DS41190A-page 109
PIC12F629/675
NOTES:
DS41190A-page 110
Preliminary
PIC12F629/675
INDEX
A
A/D ...................................................................................... 39
Acquisition Requirements ........................................... 43
Block Diagram............................................................. 39
Configuration and Operation....................................... 39
Effects of a RESET ..................................................... 45
Internal Sampling Switch (Rss) Impedence ................ 43
Operation During SLEEP ............................................ 45
PIC12F675 Converter Characteristics ........................ 98
Sampling Time ............................................................ 44
Source Impedance...................................................... 43
Summary of Registers ................................................ 45
Absolute Maximum Ratings ................................................ 83
AC Characteristics
Industrial and Extended .............................................. 91
Additional Pin Functions ..................................................... 19
Interrupt-on-Change.................................................... 20
Weak Pull-up............................................................... 19
Analog Input Connection Considerations............................ 36
Analog-to-Digital Converter. See A/D
Assembler
MPASM Assembler ..................................................... 77
B
Block Diagram
TMR0/WDT Prescaler................................................. 25
Block Diagrams
Analog Input Mode...................................................... 36
Comparator Output ..................................................... 36
Comparator Voltage Reference .................................. 37
GP0 and GP1 Pins...................................................... 21
GP2............................................................................. 22
GP3............................................................................. 22
GP4............................................................................. 23
GP5............................................................................. 23
On-Chip Reset Circuit ................................................. 55
RC Oscillator Mode..................................................... 54
Timer1 ......................................................................... 28
Watchdog Timer .......................................................... 66
Brown-out
Associated Registers .................................................. 58
Brown-out Detect (BOD) ..................................................... 56
Brown-out Reset Timing and Characteristics...................... 94
C
Calibrated Internal RC Frequencies.................................... 92
CLKOUT ............................................................................. 54
Code Examples
Changing Prescaler .................................................... 27
Data EEPROM Read .................................................. 49
Data EEPROM Write .................................................. 49
Initializing GPIO .......................................................... 19
Saving STATUS and W Registers in RAM .................. 65
Write Verify.................................................................. 49
Code Protection .................................................................. 68
Comparator......................................................................... 33
Associated Registers.................................................. 38
Configuration .............................................................. 35
Effects of a RESET..................................................... 37
I/O Operating Modes .................................................. 35
Interrupts .................................................................... 38
Operation.................................................................... 34
Operation During SLEEP............................................ 37
Output......................................................................... 36
Reference ................................................................... 37
Response Time........................................................... 37
Comparator Specifications.................................................. 97
Comparator Voltage Reference Specifications................... 97
Configuration Bits ............................................................... 52
Configuring the Voltage Reference..................................... 37
Crystal Operation................................................................ 53
D
Data EEPROM Memory
Associated Registers/Bits ........................................... 50
Code Protection.......................................................... 50
EEADR Register......................................................... 47
EECON1 Register ...................................................... 47
EECON2 Register ...................................................... 47
EEDATA Register ....................................................... 47
Data Memory Organization................................................... 7
DC Characteristics
Extended .................................................................... 87
Extended and Industrial.............................................. 88
Industrial ..................................................................... 86
Development Support ......................................................... 77
Development Tool Version Requirements ........................ 109
Device Differences............................................................ 107
Device Migrations ............................................................. 108
Device Overview................................................................... 5
E
EEPROM Data Memory
Reading ...................................................................... 49
Spurious Write ............................................................ 49
Write Verify ................................................................. 49
Writing ........................................................................ 49
Electrical Specifications ...................................................... 83
Errata .................................................................................... 3
F
Firmware Instructions ......................................................... 69
G
General Purpose Register File ............................................. 7
GPIO
Associated Registers.................................................. 24
GPIO Port ........................................................................... 19
GPIO, TRISIO Registers..................................................... 19
Preliminary
DS41190A-page 111
PIC12F629/675
I
MCLR.................................................................................. 56
Memory Organization
Data EEPROM Memory.............................................. 47
Migrating from other PICmicro Devices ............................ 108
MPLAB C17 and MPLAB C18 C Compilers ....................... 77
MPLAB ICD In-Circuit Debugger ........................................ 79
MPLAB ICE High Performance Universal In-Circuit
Emulator with MPLAB IDE............................................ 78
MPLAB Integrated Development
Environment Software .................................................. 77
MPLINK Object Linker/MPLIB Object Librarian .................. 78
O
OPCODE Field Descriptions............................................... 69
Oscillator Configurations..................................................... 53
Oscillator Start-up Timer (OST) .......................................... 56
P
Packaging ......................................................................... 101
Details....................................................................... 102
Marking ..................................................................... 101
PCL and PCLATH............................................................... 17
Computed GOTO........................................................ 17
Stack ........................................................................... 17
PICDEM 1 Low Cost PICmicro
Demonstration Board.................................................... 79
PICDEM 17 Demonstration Board...................................... 80
PICDEM 2 Low Cost PIC16CXX
Demonstration Board.................................................... 79
PICDEM 3 Low Cost PIC16CXXX
Demonstration Board.................................................... 80
PICSTART Plus Entry Level Development
Programmer.................................................................. 79
Pin Descriptions and Diagrams .......................................... 21
Pinout Descriptions
PIC12F629 ................................................................... 6
PIC12F675 ................................................................... 6
Power Control/Status Register (PCON).............................. 57
Power-Down Mode (SLEEP) .............................................. 67
Power-on Reset (POR)....................................................... 56
Power-up Timer (PWRT) .................................................... 56
Prescaler............................................................................. 27
Switching Prescaler Assignment ................................ 27
PRO MATE II Universal Device Programmer ..................... 79
Program Memory Organization............................................. 7
Programming, Device Instructions ...................................... 69
K
KEELOQ Evaluation and Programming Tools ...................... 80
DS41190A-page 112
Preliminary
PIC12F629/675
R
RC Oscillator ....................................................................... 54
Read-Modify-Write Operations ........................................... 69
Registers
ADCON0 (A/D Control) ............................................... 41
ANSEL (Analog Select)............................................... 42
CMCON (Comparator Control) ................................... 33
CONFIG (Configuration Word).................................... 52
EEADR (EEPROM Address) ...................................... 47
EECON1 (EEPROM Control)...................................... 48
EEDAT (EEPROM Data)............................................. 47
INTCON (Interrupt Control)......................................... 13
IOCB (Interrupt-on-Change GPIO) ............................. 20
Maps
PIC12F629............................................................ 8
PIC12F675............................................................ 8
OPTION_REG (Option) ........................................ 12, 26
OSCCAL (Oscillator Calibration)................................. 16
PCON (Power Control) ............................................... 16
PIE1 (Peripheral Interrupt Enable 1)........................... 14
PIR1 (Peripheral Interrupt 1)....................................... 15
STATUS ...................................................................... 11
T1CON (Timer1 Control)............................................. 30
VRCON (Voltage Reference Control) ......................... 38
WPU (Weak Pull-up) ................................................... 19
RESET ................................................................................ 55
Revision History ................................................................ 107
Timer1
Associated Registers.................................................. 31
Asynchronous Counter Mode ..................................... 31
Reading and Writing ........................................... 31
Capacitor Selection .................................................... 31
Interrupt ...................................................................... 29
Modes of Operations .................................................. 29
Operation During SLEEP............................................ 31
Oscillator..................................................................... 31
Prescaler .................................................................... 29
Timer1 Module with Gate Control ....................................... 28
Timing Diagrams
CLKOUT and I/O ........................................................ 93
External Clock ............................................................ 91
INT Pin Interrupt ......................................................... 64
PIC12F675 A/D Conversion (Normal Mode) .............. 99
PIC12F675 A/D Conversion Timing
(SLEEP Mode).................................................... 100
RESET, Watchdog Timer, Oscillator Start-up Timer
and Power-up Timer ............................................. 94
Time-out Sequence on Power-up
(MCLR not Tied to VDD)/
Case 1 ................................................................ 60
Case 2 ................................................................ 60
Time-out Sequence on Power-up
(MCLR Tied to VDD).............................................. 60
Timer0 and Timer1 External Clock ............................. 96
Timer1 Incrementing Edge ......................................... 29
Timing Parameter Symbology ............................................ 90
Watchdog Timer
Summary of Registers ................................................ 66
Watchdog Timer (WDT)...................................................... 65
WWW, On-Line Support ....................................................... 3
Time-out Sequence............................................................. 57
Timer0 ................................................................................. 25
Associated Registers .................................................. 27
External Clock............................................................. 26
Interrupt....................................................................... 25
Operation .................................................................... 25
T0CKI.......................................................................... 26
Preliminary
DS41190A-page 113
PIC12F629/675
NOTES:
DS41190A-page 114
Preliminary
PIC12F629/675
ON-LINE SUPPORT
013001
Preliminary
DS41190A-page 115
PIC12F629/675
READER RESPONSE
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Device: PIC12F629/675
N
Literature Number: DS41190A
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DS41190A-page 116
Preliminary
PIC12F629/675
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
/XX
XXX
Temperature
Range
Package
Pattern
Examples:
I
E
=
=
-40C to +85C
-40C to +125C
Package
P
SN
MF
=
=
=
PDIP
SOIC (Gull Wing, 150 mil body)
MLF-S
Pattern
Temperature Range
b)
Device
a)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
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Preliminary
DS41190A-page117
M
WORLDWIDE SALES AND SERVICE
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ASIA/PACIFIC
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Corporate Office
Australia
Rocky Mountain
China - Beijing
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2767 S. Albright Road
Kokomo, Indiana 46902
Tel: 765-864-8360 Fax: 765-864-8387
Los Angeles
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
China - Chengdu
Microchip Technology Consulting (Shanghai)
Co., Ltd., Chengdu Liaison Office
Rm. 2401, 24th Floor,
Ming Xing Financial Tower
No. 88 TIDU Street
Chengdu 610016, China
Tel: 86-28-6766200 Fax: 86-28-6766599
China - Fuzhou
Microchip Technology Consulting (Shanghai)
Co., Ltd., Fuzhou Liaison Office
Unit 28F, World Trade Plaza
No. 71 Wusi Road
Fuzhou 350001, China
Tel: 86-591-7503506 Fax: 86-591-7503521
China - Shanghai
Microchip Technology Consulting (Shanghai)
Co., Ltd.
Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
China - Shenzhen
San Jose
Hong Kong
New York
Toronto
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699 Fax: 905-673-6509
India
Microchip Technology Inc.
India Liaison Office
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, OShaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Singapore
Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-6334-8870 Fax: 65-6334-8850
Taiwan
Microchip Technology Taiwan
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Denmark
Microchip Technology Nordic ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
France
Microchip Technology SARL
Parc dActivite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Microchip Technology GmbH
Gustav-Heinemann Ring 125
D-81739 Munich, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Italy
Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
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