What is an FPGA?

Field Programmable Gate Arrays (FPGAs) are semiconductor devices that are based around a matrix of configurable logic blocks (CLBs) connected via programmable interconnects. PGAs can be reprogrammed to desired application or functionality requirements after manufacturing. This feature distinguishes FPGAs from Application Specific Integrated Circuits (ASICs), which are custom manufactured for specific design tasks. Although onetime programmable (OTP) FPGAs are available, the dominant types are SRAM based which can be reprogrammed as the design evolves. FPGAs allow designers to change their designs very late in the design cycle even after the end product has been manufactured and deployed in the field. In addition, Xilinx FPGAs allow for field upgrades to be completed remotely, eliminating the costs associated with redesigning or manually updating electronic systems.

Figure 1: FPGA Block Structure

Why do we need FPGAs? By the early 1980s large scale integrated circuits (LSI) formed the back bone of most of the logic circuits in major systems. Microprocessors, bus/IO controllers, system timers etc. were implemented using integrated circuit fabrication technology. Random glue logic or interconnects were still required to help connect the large integrated circuits in order to: Generate global control signals (for resets etc.) Data signals from one subsystem to another sub system.

Systems typically consisted of few large scale integrated components and large number of SSI (small scale integrated circuit) and MSI (medium scale integrated circuit) components. Initial attempt to solve this problem led to development of Custom ICs which were to replace the large amount of interconnect. This reduced system complexity and manufacturing cost, and improved performance. However, custom ICs have their own disadvantages. They are relatively very expensive to develop, and delay introduced for product to market (time to market) because of increased design time. There are two kinds of costs involved in development of custom ICs Cost of development and design Cost of manufacture

(A tradeoff usually exists between the two costs) Therefore the custom IC approach was only viable for products with very high volume, and which were not time to market sensitive. FPGAs were introduced as an alternative to custom ICs for implementing entire system on one chip and to provide flexibility of reporogramability to the user. Introduction of FPGAs resulted in improvement of density relative to discrete SSI/MSI components (within around 10x of custom ICs). Another advantage of FPGAs over Custom ICs is that with the help of computer aided design (CAD) tools circuits could be implemented in a short amount of time (no physical layout process, no mask making, no IC manufacturing)

FPGA Structural Classification Basic structure of an FPGA includes logic elements, programmable interconnects and memory. Arrangement of these blocks is specific to particular manufacturer. On the basis of internal arrangement of blocks FPGAs can be divided into three classes:

1- Symmetrical arrays This architecture consists of logic elements (called CLBs) arranged in rows and columns of a matrix and interconnect laid out between them shown in Fig 20.2. This symmetrical matrix is surrounded by I/O blocks which connect it to outside world. Each CLB consists of n-input Lookup table and a pair of programmable flip flops. I/O blocks also control functions such as tri-state control, output transition speed. Interconnects provide routing path. Direct interconnects between adjacent logic elements have smaller delay compared to general purpose interconnect

2- Row based architecture Row based architecture consists of alternating rows of logic modules and programmable interconnect tracks. Input output blocks is located in the periphery of the rows. One row may be connected to adjacent rows via vertical interconnect. Logic modules can be implemented in various combinations. Combinatorial modules contain only combinational elements which Sequential modules contain both combinational elements along with flip flops. This sequential module can implement complex combinatorial-sequential functions. Routing tracks are divided into smaller segments connected by anti-fuse elements between them.

Row based Architecture

3- Hierarchical PLDs This architecture is designed in hierarchical manner with top level containing only logic blocks and interconnects. Each logic block contains number of logic modules. And each logic module has combinatorial as well as sequential functional elements. Each of these functional elements is controlled by the programmed memory. Communication between logic blocks is achieved by programmable interconnect arrays. Input output blocks surround this scheme of logic blocks and interconnects.

Hierarchical PLD

FPGA Design Flow One of the most important advantages of FPGA based design is that users can design it using CAD tools provided by design automation companies. Generic design flow of an FPGA includes following steps: System Design : At this stage designer has to decide what portion of his functionality has to be implemented on FPGA and how to integrate that functionality with rest of the system. I/O integration with rest of the system : Input Output streams of the FPGA are integrated with rest of the Printed Circuit Board, which allows the design of the PCB early in design process. FPGA vendors provide extra automation software solutions for I/O design process. Design Description : Designer describes design functionality either by using schematic editors or by using one of the various Hardware Description Languages (HDLs) like Verilog or VHDL. Synthesis : Once design has been defined CAD tools are used to implement the design on a given FPGA. Synthesis includes generic optimization, slack optimizations, power optimizations followed by placement and routing. Implementation includes Partition, Place and route. The output of design implementation phase is bit-stream file. Design Verification : Bit stream file is fed to a simulator which simulates the design functionality and reports errors in desired behavior of the design. Timing tools are used to determine maximum clock frequency of the design. Now the design is loading onto the target FPGA device and testing is done in real environment.

FPGA Applications Due to their programmable nature, FPGAs are an ideal fit for many different markets. As the industry leader, Xilinx provides comprehensive solutions consisting of FPGA devices, advanced software, and configurable, ready-to-use IP cores for markets and applications such as:

Aerospace & Defense - Radiation-tolerant FPGAs along with intellectual property for image processing, waveform generation, and partial reconfiguration for SDRs.

ASIC Prototyping - ASIC prototyping with FPGAs enables fast and accurate SoC system modeling and verification of embedded software

Audio - Xilinx FPGAs and targeted design platforms enable higher degrees of flexibility, faster time-to-market, and lower overall non-recurring engineering costs (NRE) for a wide range of audio, communications, and multimedia applications.

Automotive - Automotive silicon and IP solutions for gateway and driver assistance systems, comfort, convenience, and in-vehicle infotainment. - Learn how Xilinx FPGA's enable Automotive Systems

Broadcast - Adapt to changing requirements faster and lengthen product life cycles with Broadcast Targeted Design Platforms and solutions for high-end professional broadcast systems.

Consumer Electronics - Cost-effective solutions enabling next generation, full-featured consumer applications, such as converged handsets, digital flat panel displays, information appliances, home networking, and residential set top boxes.

Data Center - Designed for high-bandwidth, low-latency servers, networking, and storage applications to bring higher value into cloud deployments.

High Performance Computing and Data Storage - Solutions for Network Attached Storage (NAS), Storage Area Network (SAN), servers, and storage appliances.

Industrial - Xilinx FPGAs and targeted design platforms for Industrial, Scientific and Medical (ISM) enable higher degrees of flexibility, faster time-to-market, and lower overall non-recurring engineering costs (NRE) for a wide range of applications such as industrial imaging and surveillance, industrial automation, and medical imaging equipment.

Medical - For diagnostic, monitoring, and therapy applications, the Virtex FPGA and Spartan FPGA families can be used to meet a range of processing, display, and I/O interface requirements.

Security - Xilinx offers solutions that meet the evolving needs of security applications, from access control to surveillance and safety systems.

Video & Image Processing - Xilinx FPGAs and targeted design platforms enable higher degrees of flexibility, faster time-to-market, and lower overall non-recurring engineering costs (NRE) for a wide range of video and imaging applications.

Wired Communications - End-to-end solutions for the Reprogrammable Networking Linecard Packet Processing, Framer/MAC, serial backplanes, and more

Wireless Communications - RF, base band, connectivity, transport and networking solutions for wireless equipment, addressing standards such as WCDMA, HSDPA, WiMAX and others.

FPGA Design Cycle The FPGA design cycle can be divided into 3 phases: the evaluation phase, the design and debugging phase, and the production phase. In the evaluation phase, the designer is typically evaluating the FPGA for possible implementation of their design. In this phase, the designers evaluate the estimated ASIC performance of their design and compare it with an estimated FPGA performance of their design. Additionally, users may also evaluate different FPGA architectures and vendors. In this phase, the FPGA physical design tools are required to be very fast and must provide a result that provides a reasonably close estimation of the final system performance. At the other end of the FPGA design cycle is the production phase, where a design is very close to being complete. Typically, late features or last minute bugs are fixed in this stage. In this phase, FPGA physical design software must focus on getting the best possible performance (or at least a result no worse than before) at the cost of some additional runtime. The majority of the time in the FPGA design cycle is spent in the debug phase. This is the phase where the designer implements their design, configures the FPGA, and debugs specific functional units of their design. This requires the FPGA software to produce a result with reasonably good performance in a very short time. In this phase, it is more important that the software run fast than it is to produce the highest possible circuit frequency. This is because the time to compile a design to an FPGA is considered dead time when the designer cannot look at the results on the bench and hence is not very productive. The turns-per-day metric is, therefore, of paramount importance. In other words, it is very important to allow the user to iterate several times a day during this phase. Furthermore, since 90% of the total number of design compilations are done in the debug phase, faster compile times are of paramount importance for FPGA physical design software in this phase. Depending on the design phase, the primary requirement for the FPGA physical design software changes from extremely fast compile times to extremely good circuit performance by trading off one for the other. In the evaluation and debug phase, runtime is of primary importance and circuit performance, while still being important, is of secondary importance. In the production phase, circuit performance is of primary importance, while runtime of the software is not as important. While we see that the primary requirements for the FPGA design software can change from very fast compile times to very high frequency implementations it is important to note that the underlying FPGA value proposition of faster time-to-market makes compile times that are greater than 10-12 hours unacceptable. This is a very important requirement for FPGA

software since this perceived upper limit on the amount of time a single compilation run can take has not scaled with the increase in the FPGA device and design sizes. For example, in the same time it took to completely place and route the largest FPGA device of 25000 gates five years ago, it is now not only possible but expected that a multi-million gate design be placed and routed.