Memory & Programmable Logic

04-Apr-14

Memory Unit
A device
to which binary information is transferred for storage and from which information is available when needed for processing

When data processing takes place

information from the memory is transferred to selected register in the processing unit Intermediate and final results obtained in the processing unit are transferred back to the memory for storage
04-Apr-14 2

Memory Unit
Used to communicate with an input/output device
binary information received from an input device is stored in memory

information transferred to an output device is taken from memory

A collection of cells capable of storing a large quantity of binary information Two types
RAM (random-access memory) ROM (read-only memory)
04-Apr-14 3

Classification
RAM
We can read stored information (read operation) Accepts new information for storage (write operation) Perform both read and write operation

ROM
only performs read operation existing information cannot be modified Programming the device specifying the binary information and storing it within the programmable device a.k.a. programmable logic device
04-Apr-14 4

Programmable Logic Devices

PLD
ROM is one example Programmable Logic Array (PLA) Programmable Array Logic (PAL) Field Programmable Gate Array (FPGA)

PLD is
an integrated circuit (IC) with internal logic gates Interconnection between the gates can be programmed through fuses At the beginning they are all intact By programming we remove some of them, while keeping the others
04-Apr-14 5

Random Access Memory (RAM)

RAM The reason for the name Word
The time it takes to transfer information to or from any desired random location is always the same. groups of bits in which a memory unit stores information At one time, memory move in and out of the storage a word of information 8 bit byte 16 bit 32 bit Capacity is usually given in number of bytes
04-Apr-14 6

Memory Unit
Block diagram
n data input lines

k address lines

Read Read/Write Write

Memory Unit 2k words n bit per word

n data output lines

04-Apr-14

Specification
A memory unit is specified by
1. the number of words it contains 2. number of bits in each word

Each word (or location for a word) in memory is assigned an identification number
address 0 to 2k-1 selection process to read and write a word is done by applying k-bit address to the address lines A decoder accepts the address and selects the specified word in the memory
8

Selection

04-Apr-14

Memory Map and Address Selection

1 K x 16 Memory
0xFC12 0x45AB 0xE24F 0x71C3
0000000000
0000000001 0000000010

address lines

10 x 1024 Decoder

0000000011

0x201D 0x092F

1111111110

1111111111

10 1 K = 2 04-Apr-14

1 M = 220

1 G = 230

1 T = 240
9

Write and Read Operations

Write
transfer in

Read
transfer out

Steps for write operation

1. Apply the binary address of the desired word to the address lines 2. Apply the data word that is be stored in memory to the (data) input lines

3. Activate the write input

04-Apr-14 10

Read Operation
Steps
1. Apply the binary address of the desired word to the address lines 2. Activate the read input The desired word will appear on the (data) output lines reading does no affect the content of the word

04-Apr-14

11

Control Inputs to Memory Chip

Commercial memory components usually provide a memory enable (or chip select) control input memory enable is used to activate a particular memory chip in a multi-chip implementation of a large memory
Memory Enable
0 1

Read/Write
X 0

Memory Operation
None write

1
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read
12

 Memory does not have to use an internal clock

It only reacts to the control inputs, e.g., read and write operation of a memory unit is controlled by an external device (e.g. CPU) that has its own clock

Timing

Access time
the time required to select a word and read it

Cycle time
the time required to complete a write operation
data address read/write enable
04-Apr-14 13

CPU

Memory

Write Cycle
CPU clock: 2 GHz Cycle time: 1.25 ns
0.5 ns clock Memory address Memory enable Read/ Write Data input T1

1.The address and input data are applied to the memory at the beginning of the T1

2.The memory enable and the Read/Write signals must be activated after the signals in the address lines are stable.
3.The memory enable and the Read/Write signals must stay active for at least 50 ns ( cycle time )

4. The address and data signals must remain stable for a short time after the control signals are deactivated.

T2 Address valid

T3

Data valid

CPU must devote three clock cycles for each 04-Apr-14 write operation

14

 CPU clock: 2 GHz Access time: 1.25 ns

clock Memory address Memory enable Read/ Write Data output
T1

Read Cycle

1.The memory enable and Read/Write signals must be high level for a read operation

1.25 ns T2 Address valid

T3

Data valid

The desired word appears at output, 1.25 ns after 04-Apr-14 enable is activated memory

15

Types of Memory
RAM ROM

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16

Types of Memory 1/2

RAM
access time is always the same no matter where the desired data is actually located

Sequential-access memory
Access time is variable e.g., magnetic disks, tapes

RAM
SRAM (static RAM) latches, stores information as long as power is on DRAM (dynamic RAM) information is stored as charge on a capacitor refreshing is necessary due to discharge 04-Apr-14 17

Types of Memory 2/2

Volatile memory (RAM)
When the power is turned off, the stored information is lost RAM (SRAM or DRAM)

Nonvolatile memory (ROM)

retains the stored information after removal of power magnetic disks data is represented as the direction of magnetization ROM programs needed to start a computer are kept in ROM
04-Apr-14 18

Memory Cell
Equivalent logic of a memory cell for storing one bit of information
select output

input

S R

read/write S R 0 0 0 1 1 0 1 1 Q(t+1) Q 0 1 X
04-Apr-14

select input

BC

output

read/write
19

Random Access Memory (RAM)

Conventional Symbol

Array Logic Symbol

20 / 18

4 x 4 RAM
word 0 Address inputs

1.The decoder is enabled with the memory enable input. 2. Once a word has been selected, the Read/Write determines the operation. input data

BC
word 1 2x4 decoder word 2

BC

BC

BC

BC

BC

BC

BC

BC
memory enable

BC

BC

BC

EN

word 3

BC

BC

BC

BC

read/write
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output data

21

4 x 4 RAM
word 0

Read Operation:1 it reads the content in word 1. Write Operation:0 it writes data from data input

input data

0 Address inputs 1

BC
word 1 2x4 decoder word 2

BC

BC

BC

BC

x3

BC

x2

BC

x1

BC

x0

BC
memory enable

BC

BC

BC

EN

word 3

BC

BC

BC

BC

read/write
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x3

output data x2 x1

22

x0

Read Operation:

0
1 1

Write Operation:
0 0
1 1

 Physical construction

Commercial RAMs

Capacity of thousands of words each word may range from 1 to 64 bits How to increase capacity of Memory? Ans. Combining Memories Example: We have memory chips of 10244
Logical construction: 1024 8 data input

address lines memory enable read/write

04-Apr-14

10244

10244

data output

25

Combining Memories
address lines
X X . X 1 0

. . .

0 1 9

10244

. . .

0 1 9

10244

ME
R/W

ME R/W

20484 RAM

Memory Enable

04-Apr-14

26

Coincident Decoding
A memory with 2k words requires a k 2k decoder k 2k decoder requires 2k AND gates with k inputs per gate There are ways to reduce the total number of gates and number of inputs per gate Two dimensional selection scheme
Arrange the memory words in an array that is as close as possible to square Use two k/2-input decoders instead of one k-input decoder. One decoder performs the row selection 04-Apr-14 27 The other does the column selection

Example:With out Coincident Decoding

Need 1024 AND gates

10 1024 decoder

1024

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28

Example: Coincident Decoding

1024 word memory
Binary address 01100 10100
Where X-MSB Y-LSB 532 decoder
0 1 2 20 31

Need 64 AND gates

Y

0 1
2

532 decoder 12

04-Apr-14

31

29

Classification of RAMs

Static RAM

Dynamic RAM

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30

Static RAM
SRAM consists essentially of internal latches that store the binary information. The stored information remains valid as long as power is applied to the unit.

SRAM is easier to use and has shorter read and write cycles.
Low density, low capacity, high cost, high speed, high power consumption.

31

Dynamic RAM
DRAM stores the binary information in the form of electric charges on capacitors. The capacitors are provided inside the chip by MOS transistors.

The capacitors tends to discharge with time and must be periodically recharged by refreshing the dynamic memory.

32

DRAMs
SRAM memory is expensive
One cell typically contains four to six transistors Usually used for on-chip cache memories and embedded systems (cameras, smart phones, etc.)

DRAM is much less expensive

One MOS transistor and a capacitor Four times the density of SRAM in a given chip area cost per bit storage is three to four times less than SRAM low power requirement Perfect technology for large memories such as main memory Most DRAMs have short word sizes 04-Apr-14 33

DRAMs and Address Multiplexing

In order to reduce number of pins on a memory chip, the same pins are used for both row and column addresses Example: 1 GB DRAM
15-bit column register

CAS

RAS

15 x 32768 decoder

15-bit address

15-bit row register

15 x 32768 decoder

32768 x 32768 memory array

read/ write

04-Apr-14

data in

data out

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DRAMs and Address Multiplexing

CAS RAS
clock

CAS (Column address Strobe) RAS (Row address Strobe)

CAS

15-bit column register

RAS

15 x 32768 decoder

15-bit address

15-bit row register

15 x 32768 decoder

32768 x 32768 memory array

read/ write

04-Apr-14

data in

data out

35

What is Register ?
Registers are clocked sequential circuits A register is a group of flip-flops
Each flip-flop capable of storing one bit of information An n-bit register consists of n flip-flops capable of storing n bits of information

36

DRAMs and Address Multiplexing

CAS (Column address Strobe) RAS (Row address Strobe)

Address Multiplexing
To reduce the number of the pins in the IC package. 8-bit row address

DRAMs and Address Multiplexing

CAS (Column address Strobe) RAS (Row address Strobe)

Address Multiplexing

8-bit column address

Read-Only Memory
ROM
memory device in which permanent binary information is stored Binary information must be specified by the designer It then is embedded in the unit to form the required interconnection pattern nonvolatile

Block diagram
k inputs

2k x n ROM

n outputs
Programming input
39

no data inputs 04-Apr-14 enable inputs three-state outputs

Read-Only Memory (ROM)

Conventional Symbol

Array Logic Symbol

40 / 18

Example: ROM
32 x 8 ROM
0
1

intersections

I0 I1 I2 I3 I4

2 3

5x32 decoder
28 29 30 31

each OR gates are considered as 04-Apr-14 having 32 inputs

A7

A6

A5

A4

A3

A2

A1

A0

41

Example: ROM
Number of connections

In general

32 8 ROM has 32 8 = 256 internal connections

These intersections are programmable

2k n ROM will have a k 2k decoder and n OR gates Each OR gate has 2k inputs inputs of every OR gate are initially connected to each output of the decoder
they are initially closed (connected to the input of OR gate) A fuse is used to connect two wires During programming, some of these fuses are blown by applying high voltage.
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 Internal storage specified by a table Example: 32 8 ROM

Inputs I4 0 0 0 0 I3 0 0 0 0 I2 0 0 0 0 I1 0 0 1 1 I0 0 1 0 1 A7 1 0 1 1 A6 0 0 1 0 A5 1 0 0 1 A4 1 1 0 1

Programming ROM
Outputs A3 0 1 0 0 A2 1 1 1 0 A1 1 0 0 1 A0 0 1 1 0

1
1 1 1

1
1 1 1
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1
1 1 1

0
0 1 1

0
1 0 1

0
1 0 0

0
1 1 0

0
1 0 1

0
0 0 1

1
0 1 0

0
0 0 0

0
1 1 1
43

1
0 0 1

Programming ROM
Inputs I4 0 I3 0 I2 0 I1 0
0

Outputs I0 0 A7 1 A6 0 A5 1 A4 1 A3 0 A2 1 A1 1 A0 0

I0 I1 I2 I3 I4

2 3

5x32 decoder
28 29

30 31

04-Apr-14

A7

A6

A5

A4

A3

A2

A1

A0

44

Consider a 32 8 ROM ROM Block Diagram There are 5 input lines that form the binary numbers from 0 to 31 for the address.

Consider a 32X8 ROM The 5-to32-line address decoder 32 8 storage array

Consider a 32X8 ROM

Data output lines

Programming the ROM

The hardware procedure that programs the ROM results in blowing fuse links according to a given truth table.

Programming the ROM

The 0 in the word are programmed by blowing the fuse links between output of decoder and the inputs of OR gates.

Programming the ROM

The 1 in the word are marked in the diagram with a X to denote a connection in place of a dot used for permanent connection in logic diagram.

 Combinational Circuit Implementation

The ROM may be onsidered as a combinational circuit with eight outputs, each being a function of the five input variables.

 Combinational Circuit Implementation

Output A7 can be expressed in sum of minterms as A7= ( 0,2,3,,29 )

Combinational Circuit Design with ROM

Formerly,
we have shown that a k 2k decoder generates 2k minterms of k input variables

Furthermore,
by inserting OR gates to sum these minterms, we were able to realize any desired combinational circuit.

A ROM is essentially a device that includes both the decoder and the OR gates within a single device.
first interpretation: a memory unit that stores words
04-Apr-14 53

Combinational Circuit Design with ROM

ROM (cont.)
Second interpretation: a programmable device that can realize any combinational circuit
0

I0 I1 I2 I3 I4

2 3

5x32 decoder
28 29

30 31

04-Apr-14

A7

A6

A5

A4

A3

A2

A1

A0

54

Combinational Circuit Design with ROM

Example: Truth table
Inputs A2 0 0 A1 0 0 A0 0 1 B5 0 0 B4 0 0 Outputs B3 0 0 B2 0 0 B1 0 1 B0 0 1

0
0 1 1

1
1 0 0

0
1 0 1

0
0 0 0

0
0 1 1

0
1 0 1

1
0 0 0

0
1 0 0

0
0 0 1

1
1
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1
1

0
1

1
1

0
1

0
0

1
0

1
0

1
1
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Example: Design with ROM

8 x 6 ROM would suffice
Inputs B0 A0 A1 A2 B1 86 ROM B2 B3 B4 B5 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 Outputs 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 A2 A1 A0 B5 B4 B3 B2 B1 B0

1
1 1

0
1 1

1
0 1

0
1 1

1
0 1

1
0 0

0
1 0

0
1 0
56

1
1 1

04-Apr-14

ROM Truth Table

Example: Design with ROM

0
1

I0 I1 I2

3x8 decoder 4

2 3

Inputs

Outputs

A2 0 0 0
0

A1 0 0 1
1

A0 0 1 0
1

B5 0 0 0
0

B4 0 0 0
0

B3 0 0 0
1

B2 0 0 1
0

B1 0 1 0
1

B0 0 1 0
0

5 6 7

1 1

0 0 1 1

0 1 0 1

0 0 1 1

1 1 0 1

0 1 0 0

0 0 1 0

0 0 1 0

0 1 1 1

B5 B4 B3 B2 B1 B0

1 1

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57

Types of ROMs
Mask Programmed ROM
Programmed during manufacturing

Field Programmable ROM Programmable Read-Only Memory (PROM)

Blow out fuses to produce 0

Erasable Programmable ROM (EPROM)

Erase all data by Ultra Violet exposure

Electrically Erasable PROM (EEPROM)

Erase the required data using an electrical signal

58 / 18

 Programming can be done in different ways

Mask programming: customer provides the truth table manufacturer generates the mask for the truth table can be costly, since generating a custom mask is charged to the customer. economical only if a large quantity of the same ROM configuration is to be ordered. Field Programmable Programmable ROM (PROM): Customer can program the ROM by blowing fuses by applying high voltage through a special pin Special instrument called PROM programmer is 04-Apr-14 59 needed.

Types of ROM 1/2

Types of ROM 2/2

Programming ROM and PROMs is irreversible.

Erasable PROM (EPROM)

can be programmed repeatedly. EPROM is placed under a special ultra-violet light for a given period of time At the end, the former program is erased

After erasure, EPROM becomes ready for another programming

Electronically erasable PROM (EEPROM or E2PROM)

04-Apr-14 60

Programmable Logic Devices

EPROM is an example of combinational programmable logic device (PLD)

Configuration of EPROM
Fixed AND array (decoder) programmable OR array

Inputs

Outputs

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61

Programmable Logic Device (PLD)

Boolean Functions:
Sums-of-Products AND-plane followed by OR-plane
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

I2 I1 I0

62 / 18

Other PLDs
Two other types
programmable AND array programmable OR array

Inputs

Outputs

Programmable Logic Array (PLA)

Inputs

programmable AND array

fixed OR array

Outputs

04-Apr-14

Programmable Array Logic (PAL)

63

Programmable Logic Array (PLA)

Inputs
programmable AND array programmable OR array

Outputs

Similar to PROM However, PLA does not generate all the minterms Decoder is replaced by an array of AND gates The product terms are then connected to OR gates
that provide the sum of products 04-Apr-14

can be programmed to generate any product term of input variables

64

 PLA: 3 inputs, 5 product terms and 4 outputs

A B C F1 = (A AB ++BC) AC F2 = AC + AB F3 = BC + AB F4 = BC + A
0 1

PLA: Example

C C B B A A

F1 F2 F3

04-Apr-14

F465

PLA Programming Table

F1 = (A + BC) F2 = AC + AB F3 = BC + AB F4 = BC + A Outputs

Inputs Product Term A

1 2 3 1 1

C F1
1 1 -

T F2 F3 F4

B
0 -

C
0 0

4 5
04-Apr-14 66

Size of PLA
Specified by
number of inputs, number of product terms, number of outputs

A typical IC PLA (F100)

16 inputs, 48 product terms, and 8 outputs

n input, k product terms, m output PLA has

k AND gates, m OR gates, m XOR gates

2n k connections between input and the AND array k m connections between the AND and OR arrays 2m connections associated with XOR gates (2n k + k m + 2m) connections to program
04-Apr-14 67

 PLA: 3 inputs, 5 product terms and 4 outputs

A B C F1 = (A + BC) F2 = AC + AB F3 = BC + AB F4 = BC + A
0 1

PLA: Example

C C B B A A

F1 F2 F3

04-Apr-14

F468

Programming PLA
Optimization
number of literals in a product term is not important
When implementing more than one function, functions must be optimized together in order to share more product terms multiple output optimization (espresso) both the true and complement of each function should be simplified to see which one requires fewer number of product terms
04-Apr-14 69

Example: Programming PLA

Two functions F1 (A, B, C) = (0, 1, 2, 4) F2 (A, B, C) = (0, 5, 6, 7)
BC A 0 1 00 01 11 10 BC

A 0
1

00

01

11

10

1 1

1 0

0 0

1 0

1 0

0 1

0 1

0 1

F1 = AB + AC + BC

F2 = AB + AC + ABC

F1 = (AB + AC + BC)
04-Apr-14

F2 = (AC + AB + ABC)
70

Example: Programming PLA

PLA programming table
F1 = (AB + AC + BC) F2 = AB + AC + ABC
Outputs Inputs Product Term AB AC BC ABC
04-Apr-14

A 1 1 0

B 1 1 0

C 1 1 0

F1

F2

1 2 3 4

71

Programmable Array Logic (PAL)

Inputs
programmable AND array fixed OR array

Outputs

Programmable Array Logic (PAL)

Easier to program than PLA But, not as flexible A typical PAL

8 inputs, 8 outputs, 8-wide AND-OR array
04-Apr-14 72

product term
1
2

Example: PAL
AND gates inputs
3 4
5 6

F1

I1

F2

I2

7 8 9
10 11

F3

I3

I4

12

F4

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73

Design with PAL

Each Boolean function must be simplified to fit into each section. Product terms cannot be shared among OR gates
Each function can be simplified by itself without regard to common product terms

The number of product terms in each section is fixed

If the number of product terms is too many, we may have to use two sections to implement the function.

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74

 Four functions

Example: Design with PAL

A(x, y, z, t) = (2, 12, 13)

B(x, y, z, t) = (7, 8, 9, 10, 11, 12, 13, 14, 15) C(x, y, z, t) = (0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15) D(x, y, z, t) = (1, 2, 8, 12, 13)

First step is to simplify four functions separately

A = xyz + xyzt B = x + yzt
C = xy + zt + yt D = xyz + xyzt + xyt + xyzt
04-Apr-14 75

Example: Design with PAL

1

A = xyz + xyzt B = x + yzt C = xy + zt + yt D = xyz + xyzt + xyt + xyzt = A + xyt + xyzt

3 4 5 6 7 8
9

F1

F2

F3

10 11 12
04-Apr-14 76

F4

 D = A + xyt + xyzt
Product Term 1 2
3

Example: Design with PAL

AND Inputs x 1 0
-

y 1 0
-

z 0 1
-

t 0
-

F1 -

Outputs A = F1 = xyz + xyzt

4 5 6 7 8 9 10 11 12 04-Apr-14

1 0 -

1 1 0

1 1 -

1 1 0

B = F2 = x + yzt

C = F3 = xy + zt + yt

D = F4 = F1 + xyt + xyzt

77

Example: Design with PAL

AND gates inputs
1 2
3

4 5 6 7 8 9 10 11 12

04-Apr-14x x y y z z t t A A

A = xyz + xyzt D = A + xyt + xyzt

78

PAL: BCD to 7-Segment P14H8: 14 inputs, 8 outputs (2 have four -Display Decoder product terms, 6 have
(ABCD)10 (a b c d e f g)
2 product terms)
a f g e d b c

a = A + BD + C + BD b = A + CD + CD + B c = A + B + C d = BD + CD + BCD + BC e = BD + CD f = A + CD + BD + BC g = A + CD + BC + BC we need 4 inputs, 7 outputs, 4 product terms per output P16H8: 10 inputs, 8 outputs, 7 product terms per output 04-Apr-14

a b c d e f g
BCD to 7-segment-display decoder

D
79

7-Segment-Display Decoder
Different way to optimize
multiple output optimization espresso supports this a = BCD + CD + BD + A + BCD b = BD + CD + CD + BD c = BD + BCD + CD + CD + BCD d = BC + BCD + BD + BCD e = BD + BCD f = BCD + CD + A + BCD g = BC + BC + A + BCD
a = A + BD + C + BD b = A + CD + CD + B c = A + B + C d = BD + CD + BCD + BC e = BD + CD f = A + CD + BD + BC g = A + CD + BC + BC

9 product terms in total (previous one has 14)

PLA can also be used

F100: 16 inputs, 48 product terms, and 8 outputs
04-Apr-14 80

Sequential PLDs
So far, we have seen PLD that can realize only combinational circuits However, digital systems are designed using both combinational circuits (gates) and flipflops.
With PLDs, we need to use external flip-flops to realize sequential circuit functions.

Different types
1. Sequential (or simple) programmable logic device (SPLD) 2. Complex programmable logic device (CPLD) 3. Field programmable gate array (FPGA)
04-Apr-14 81

SPLD
Inputs
programmable AND-OR array (PAL or PLA)

Outputs
flip-flops

Sequential Programmable Logic Device (SPLD)

Additional programmable connections are available to include flip-flop outputs in the product terms formed with AND array. Flip-flops may be of D or JK type Example: AMD 22V10
24 pin device, 10 output logic macrocells The number of product term allocated to an output varied from 8 to 16
04-Apr-14 82

AMD 22V10

04-Apr-14

83

 SPLD is usually PAL + D flip-flops Each section in SPLD is called macrocell. A macrocell

SPLD Macrocell

sum-of-products combinational logic + optional flip-flop 8-10 macrocells in one IC package

D
C

x y
04-Apr-14

x x y y

CLK OE

84

Additional SPLD Functionalities

Additional SPLD Functionalities
Bypass circuitry for the output (bypassing) flip-flop selection of clock edge polarity XOR gate for selection of true or complement of output bypass
0 D C Q 1

x y

OE CLK

04-Apr-14

x x y y Q Q CLK OE

85

Example: serial adder

Output equation:
S = x y Q = xyQ + xyQ + xyQ + xyQ

Flip-flop input equation:

D = Q(t+1) = xy + xQ + yQ
SI clock shift control serial input SI shift register B shift register A SO

serial output

a b
C_in

FA

S C

SO

04-Apr-14

reset

86

86

Example: Serial Adder with SPLD

Q(t+1) = xy + xQ + yQ
bypass

0 D C Q
1

OE CLK

x y
x x y y Q Q CLK OE

04-Apr-14

87

Example: Serial Adder with SPLD

S = xyQ + xyQ + xyQ + xyQ
bypass

0 D C Q 1

x y

OE CLK

x x y y Q Q CLK OE

04-Apr-14

88

Generic Array Logic (GAL)

Similar to SPLD with PAL
PAL uses fuses while GAL uses electrically erasable CMOS (E2CMOS) cell at each intersection

04-Apr-14

89

Complex Programmable Logic Device

PLD PLD PLD PLD

IO block

programmable switch matrix

IO block

PLD

PLD

PLD

PLD

Example: Altera MAX 7000-series CPLD with 2500 gates

04-Apr-14 90

FPGA
Field Programmable Gate Array
FPGA is a VLSI circuit

Field programmable means user can program it in his own location Gate array consists of a pattern of gates fabricated in an area of silicon
pattern of gates are repeated many (thousand) times one thousand to millions of gates are fabricated within a single IC chip
04-Apr-14 91

Basics of FPGA

04-Apr-14

92

Basics of FPGA
CLB CLB CLB

PSM CLB CLB PSM

PSM

CLB

CLB

PSM

CLB

CLB

CLB

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93

Basics of FPGA
A typical FPGA consists of an array of hundreds or thousands of configurable logic blocks (CLB)
CLBs are connected to each other via programmable interconnection structure CLBs are surrounded by I/O blocks for basic communication with outside world.

CLBs consist of look-up tables, multiplexers, gates, and flip flops look-up table
is a truth table stored in an SRAM provides the combinational circuit functions for the logic block. It is like a ROM implemented as SRAM 04-Apr-14 94