Reference:http://www.ht-lab.com/howto/vh2sc_tut/vh2sc_tut.

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System C vs VHDL

An SC_MODULE serves the same purpose as a VHDL Entity-Architecture pair or a Verilog mo ule! "t contains "#O $orts% &unctions% component instantiations processes etc! 'he mo ule name && is speci&ie (et)een the roun (rac*ets! SC_MODULE+s are normally )ritten to a so calle hea er &ile )ith an e,tension !h! 'he &unction p1 contains the process co e )hich in our case is a simple assignment! 'his assignment is e,ecute on the rising e ge o& the cl* signal! Similar to a VHDL process there is no return value hence the voi *ey)or ! "n the a(ove e,ample the &unction co e is inclu e in the hea er -SC_MODULE. &ile (ut as )e )ill see later on this is normally )ritten to a separate cpp &ile! 'he only (it in the a(ove e,ample )hich stan s out is the constructor part SC_C'O/- &&. &or )hich there is no VHDL e0uivalent! 1ithout going into C22 terminology% the constructor is calle &or each instance o& this && mo ule -component.! 'he tas* o& the constructor is to create an initialise the mo ule in memory an to pass on some in&o to the SystemC *ernel (e&ore the simulation starts!

/ecommen ation3 Use metho s3 .write() and .read()

Using sensitive << clk )ill result in &unction p4 (eing calle on (oth the rising an &alling e ge! "nsi e &unction p4 )e then &ilter out only the rising#positive e ge - cl*!pose ge-. .! O(viously &or a event (ase simulator li*e SystemC this is not particular e&&icient since you create 5 events per cloc* cycle an )e are only intereste in one o& them -the rising e ge.! 'he )ay to solve this is to speci&y the rising e ge on the sensitive list as in sensitive << clk.pos().

Ports and Data Type

SystemC !" Ports

'he port+s ata type is passe on (et)een the angle (rac*ets -67% template class.

"n VHDL you can speci&y a range &or your vectors (ut you can+t o this in SystemC

/ea ing an )riting &rom ports

/ea ing &rom an )riting to an "O ports is straight&or)ar ! Unli*e in VHDL you only have one assignment operator 898 &or (oth signals an varia(les! "t is there&ore recommen e to use the port metho s )hen rea ing &rom -!rea -.. an )riting to -!)rite-.. a por

"nitialising a ports
An SC_MODULE is create )hen it is instantiate an at that time the constructor -SC_C'O/. is automatically calle ! "t is uring this construction phase that ports% signals an varia(le are initialise ! 'o initialise a port you have to use the !initiali:e-. metho uring construction

SystemC Data 'ypes

SystemC e,ten s the C22 ata types )ith some a their e0uivalent VHDL ones! itional types use&ul &or mo eling har )are! 'a(le list a &e) o& these ata types an

Data 'ypes Operations

Logical#Assignment#E0uality Operations

$rocess Synchroni:ation an Deltas

Hierarchy