Lecture 150 Simple BJT Op Amps (1/28/04)

Page 150-1

LECTURE 150 SIMPLE BJT OP AMPS

(READING: Text-GHLM 425-434, 453-454, AH 249-253) INTRODUCTION The objective of this presentation is: 1.) Illustrate the analysis of BJT op amps 2.) Prepare for the design of BJT op amps Outline Simple BJT Op Amps Two-stage Folded-cascode Summary

ECE 6412 - Analog Integrated Circuit Design - II Lecture 150 Simple BJT Op Amps (1/28/04)

P.E. Allen - 2002 Page 150-2

SIMPLE TWO-STAGE BJT OP AMPS BJT Two-Stage Op Amp Circuit:

VCC
IBias I3 Q3 Q4 I1 vIN + Q5 Q8 x1 x1 VEE I5 Q1 I2 Q2 I7 Q7 xn
Fig. 150-01

I4 Cc

Q6 I6 vOUT CL

DC Conditions: I5 = Ibias, I1 = I2 = 0.5I5 = 0.5Ibias, I7 = I6 = nIBias Vicm(max) = VCC - VEB3 - VCE1(sat) + VBE1 Vicm(min) = VEE +VCE5(sat) + VBE1 Vout(max) = VCC - VEC6(sat) Vout(min) = VEE + VCE7(sat) Notice that the output stage is class A Isink = I7 and Isource = FI5 - I7
ECE 6412 - Analog Integrated Circuit Design - II P.E. Allen - 2002

Lecture 150 Simple BJT Op Amps (1/28/04)

Page 150-3

Two-Stage BJT Op Amp - Continued Small Signal Performance: Assuming differential mode operation, we can write the small-signal model as,
Cc gm1vin 2 R1 C1 + g v v1 m2 in 2 + v2 - gm6v2 R3 C3 + vout Fig. 150-02

gm4v1

R2

C2

where, 1 1 R1 = g ||r3||r4||ro3 g R2 = r6|| ro2|| ro4 r6 and R3 = ro6|| ro7 m3 m3 C1 = C3+C4+Ccs1+Ccs3 C2 = C6+Ccs2+Ccs4 and C3 = CL +Ccs6+Ccs7 Note that we have ignored the base-collector capacitors, C, except for M6, which is called Cc. Assuming the pole due to C1 is much greater than the poles due to C2 and C3 gives
gm1vin R2 C2 + v2 - gm6v2 R3 C3 + vout Fig. 150-03
ECE 6412 - Analog Integrated Circuit Design - II Lecture 150 Simple BJT Op Amps (1/28/04) P.E. Allen - 2002 Page 150-4

Two-Stage BJT Op Amp - Continued Summary of the small signal performance: Midband performanceAo = gmIgmIIRIRII gm1gm6r6(ro6||ro7) = gm1F6(ro6||ro7), Rout = ro6||ro7, Rin = 2r1 RootsgmII gm6 Zero = C = C c c -g m 1 -gmII -gm6 -1 -1 Poles at p1 gmIIRIRIICc = gm6r6(ro6||ro7)Cc = AoCc and p2 CII CL Assume that F =100, gm1=1mS, gm6 =10mS, ro6=ro7=0.5M, Cc=5pF and CL=10pF: Ao=(1mS)(100)( 250k)=25,000V/V, Rin 2(F/gm1)2(100k)=200k, Rout=250k 10mS Zero = 5pF = 2x109 rads/sec j 3 -8x10 or 318.3MHz, -1mS -2x108 9 -109 2x10 Fig. 150-04 p1 = (25,000)5pF = 25,000 = -8000 rads/sec or 1273Hz, and p2 = -10mS/10pF = -109 rads/sec or 159.15MHz
ECE 6412 - Analog Integrated Circuit Design - II P.E. Allen - 2002

Lecture 150 Simple BJT Op Amps (1/28/04)

Page 150-5

Slew Rate of the Two-Stage BJT Op Amp Remember that slew rate occurs when currents flowing in a capacitor become limited and is given as dvC Ilim = C dt where vC is the voltage across the capacitor C.
VCC Q6 I6 ICL vout VCC Q6 I6=0 ICL

Q3

Q4

Cc I5
Assume a virtural ground

Q3

Q4

Cc I5
Assume a virtural ground

vout

vin>>0 +

Q1

Q2

CL I7
Q7

vin<<0 +

Q1

Q2

CL I7
Q7

I5 + VBias -

I5 + VBias -

Q5 VEE Positive Slew Rate

Q5 VEE Negative Slew Rate

Fig. 150-05

I 5 I6 -I5 -I7 I5 SR+ = minCc, CL = Cc because I6>>I5

I5 I7-I5 I5 SR- = minCc, CL = Cc if I7>>I5.

Therefore, if CL is not too large and if I7 is significantly greater than I5, then the slew rate of the two-stage op amp should be, I5 SR = Cc
ECE 6412 - Analog Integrated Circuit Design - II Lecture 150 Simple BJT Op Amps (1/28/04) P.E. Allen - 2002 Page 150-6

Folded-Cascode BJT Op Amp Circuit

Q3 VBias
IC3

VCC Q10
iC10

VCC Q11
iC11 VBE + VCE(sat)

Q10
iC10

Q11
iC11 iout

+ vin iC1

Q1 Q2

Q8
iC2 Q6 VBias

Q9 i Q7

out

vout

Q8 Q9 Q6

vout

Q7

RA
VBias Q4
Fig. 150-06

RB

IC4

IC5

VBE + VCE(sat) VBE

Q4 IC4 Q5 IC5

Q5

VEE Simplified circuit

VEE Biasing details of the output

DC Conditions: I3 = Ibias, I1 = I2 = 0.5I5 = 0.5Ibias, I4 = I5 = kIBias, I10 = I11 = kIBias-0.5Ibias (k>1) Vicm(min) = VEE+VCE4(sat)+VEC1(sat)-VBE1 Vicm(max) = VCC-VCE3(sat)+VEB1 Vout(max) = VCC-VEC9(sat)-VEC11(sat) Vout(min) = VEE+VCE5(sat)+VCE7(sat) Notice that the output stage is push-pull Isink and Isource are limited by the base current.
ECE 6412 - Analog Integrated Circuit Design - II P.E. Allen - 2002

Lecture 150 Simple BJT Op Amps (1/28/04)

Page 150-7

Folded-Cascode BJT Op Amp - Continued Small-Signal Analysis:

gm6vbe6 gm7vbe7

RA
gm1vin 2

RB i10 gm2vin 2

i7 ro11 + vout -

ro1

ro4

r 6

vbe6 ro6 1 gm10 +

ro2

ro5

r 7

vbe7 ro7 i 10 +

Fig. 150-07

ro7+Pro11/2 r7 where RA 1/gm6 and RB 1+gm7ro7 2 if ro7 ro11 -gm1r6vin -gm1vin gm2r7vin gm2r7vin gm2vin i10 2(r6+RA) i = 7 2(r7+RB) 2(r7+0.5r7) 2 3 vout 5 5 vout = (i7-i10)Routvin = 6 (gm1Rout)vin if gm1 = gm2 vin = 6 (gm1Rout) Rout = Pro11|| [ (ro5||ro2)] and Rin = 2r1 Assume that FN =100, FP =50, gm1 = gm2 =1mS, roN = 1M, and roP = 0. 5M: vout Rout = 14.285 M and Rin = 100k vin = 14,285V/V

ECE 6412 - Analog Integrated Circuit Design - II Lecture 150 Simple BJT Op Amps (1/28/04) P.E. Allen - 2002 Page 150-8

Folded-Cascode BJT Op Amp - Continued Frequency response includes only 1 dominant pole at the output (self-compensation), -1 p1 = Rout CL There are other poles but we shall assume that they are less than GB If CL = 25pF, then |p1| = 2800 rads/sec. or 446Hz GB = 6.371 MHz Checking some of the nondominant poles gives: gm6 1 |pA| = RACA = CA 159MHz if CA = 1pf (the capacitance to ac ground at the emitter of Q6) 1 2 |pB| = RBCB = r7CB 6.37MHz if CB = 1pf (the capacitance to ac ground at the 100 emitter of Q7) 80 This indicates that for small capacitive 60 loads, this op amp will suffer from 40 higher poles with respect to phase 20 margin. Capacitive loads greater than 0 25pF, will have better stability (and less -20 GB). -40
VdB(3)

100

1000

104

105 106 Frequency (Hz)

107

108

Fig. 150-08

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002

Lecture 150 Simple BJT Op Amps (1/28/04)

Page 150-9

SUMMARY Two stage op amp gives reasonably robust performance as an on-chip op amp DC balance conditions insure proper mirroring and all transistors in saturation Slew rate of the two-stage op amp is I5/Cc Folded cascode op amp offers wider input common voltage range Folded cascode op amp is a self-compensated op amp because the dominant pole at the output and proportional to the load capacitor

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002