Sie sind auf Seite 1von 11

INELECSHARE.ICR38.NET INELEC.COMXA.

COM
Page 1

Detailed Z80 instruction set


# ~ : number of machine cycles

Table of Contents 1- 8-bit Load Instructions 2- 16-bit Load Instructions 3- Exchange, Block Transfer and Search Instructions 4- 8-bit Arithmetic and Logical Instructions 5- 16-bit Arithmetic Instructions 6- General Purpose Arithmetic and CPU Control Instructions 7- Rotate and Shift Instructions 8- Bit Manipulation Instructions 9- Input and Output (I/O) Instructions 10- Jump Instructions 11- Call and Return Instructions

Page 2 3 4 5 6 6 7 8 9 10 11

Z80 Instruction Set

Page 1 of 11

EE422

2009/2010

INELECSHARE.ICR38.NET INELEC.COMXA.COM
Page 2

8-bit Load Instructions


Mnemonic LD r, r LD p, p* LD q, q* LD r, n LD p, n* Opcode Opcode # of # of ~ 76 543 210 Hex Bytes 01 r r 1 1 11 011 101 DD 2 2 p p 01 p p 11 111 101 FD 2 2 q q 01 q q 00 r 110 2 2 rn n 11 011 101 00 p 110 DD 3 3 pn n 11 111 101 00 q 110 FD 3 3 qn n 01 r 110 1 2 r (HL) 11 011 101 01 r 110 DD 3 5 r (IX + d) d 11 111 101 01 r 110 FD 3 5 r (IY + d) d 01 110 r 1 2 (HL) r 11 011 101 01 110 r DD 3 5 (IX + d) r d 11 111 101 01 110 r FD 3 5 (IY + d) r d 00 110 110 36 2 3 (HL) n n 11 011 101 00 110 110 DD 4 5 (IX + d) n d 36 n 11 111 101 00 110 110 FD 4 5 (IY + d) n 36 d n 00 001 010 0A 1 2 A (BC) 00 011 010 1A 1 2 A (DE) 00 111 010 n 3A 3 4 A (nn) n 00 000 010 02 1 2 (BC) A 00 010 010 12 1 2 (DE) A 00 110 010 n 32 3 4 (nn) A n 11 101 101 ED 2 2 AI b b b 0 b IFF2 0 01 010 111 57 11 101 101 ED 2 2 AR b b b 0 b IFF2 0 01 011 111 5F 11 101 101 ED 2 2 IA 01 000 111 47 11 101 101 ED 2 2 RA 01 001 111 4F r, r means any of the registers A, B, C, D, E, H, L. p, p means any of the registers A, B, C, D, E, IXH, IXL. q, q means any of the registers A, B, C, D, E, IYH, IYL. ddL, ddH refer to high order and low order eight bits of the register respectively. * means unofficial instruction. = flag is not affected, 0 = flag is reset, 1 = flag is set, b = flag is set according to the result of the operation, IFF2 = the interrupt flip-flop 2 is copied. Symbolic Operation r r Flags S Z F5 H F3 P/V N C No. of T States 4 8 8 7 11 Comments r, r 000 001 010 011 100 101 111 Reg. B C D E H L A

p, p Reg. 000 001 010 011 100 101 111 q, q 000 001 010 011 100 101 111 B C D E IXH IXL A Req. B C D E IYH IYL A

LD q, n* LD r, (HL) LD r, (IX + d)

11 7 19

LD r, (IY + d) LD (HL), r LD (IX + d), r

19 7 19

LD (IY + d), r LD (HL), n

19 10

LD (IX + d), n

19

LD (IY + d), n LD A, (BC) LD A, (DE) LD A, (nn) LD (BC), A LD (DE), A LD (nn), A LD A, I LD A, R LD I, A LD R, A

19 7 7 13 7 7 13 9 9 9 9 R is written after it is increased. R is read after it is increased.

Notes:

Flag Notation:

Z80 Instruction Set

Page 2 of 11

EE422

2009/2010

INELECSHARE.ICR38.NET INELEC.COMXA.COM
Page 3

16-bit Load Instructions


Mnemonic LD dd, nn Symbolic Operation dd nn Flags S Z F5 H F3 P/V N C Opcode 76 543 210 00 dd0 001 n n 11 011 101 00 110 001 n n 11 111 101 00 110 001 n n 00 101 010 n n 11 101 101 01 dd1 011 n n 11 011 101 00 101 010 n n 11 111 101 00 101 010 n n 00 100 010 n n 11 101 101 01 dd0 011 n n 11 011 101 00 100 010 n n 11 111 101 00 100 010 n n 11 111 001 11 011 101 11 111 001 11 111 101 11 111 001 Opcode Hex # of Bytes 3 # of ~ 3 No. of T States 10 dd 00 01 02 03 Comments Pair BC DE HL SP

LD IX, nn

IX nn

DD 21

14

LD IY, nn

IY nn L (nn) H (nn+1) ddL (nn) ddH (nn+1) IXL (nn) IXH (nn+1) IYL (nn) IYH (nn+1) (nn) L (nn+1) H (nn) ddL (nn+1) ddH (nn) IXL (nn+1) IXH (nn) IYL (nn+1) IYH SP HL SP IX SP IY

FD 21

14

LD HL, (nn)

2A

16

LD dd, (nn)

ED

20

LD IX, (nn)

DD 2A

20

LD IY, (nn)

FD 2A

20

LD (nn), HL

22

16

LD (nn), dd

DD

20

LD (nn), IX

DD 22

20

LD (nn), IY LD SP, HL LD SP, IX LD SP, IY

FD 22 F9 DD F9 FD F9

4 1 2 2

6 1 2 2

20 6 10 10

PUSH qq

PUSH IX

PUSH IY

POP qq

POP IX

POP IY

Notes: Flag Notation:

SP SP 1 (SP) qqH 11 qq0 101 1 3 11 SP SP 1 (SP) qqL SP SP 1 11 011 101 DD (SP) IXH 2 4 15 11 100 101 E5 SP SP 1 (SP) IXL SP SP 1 11 111 101 FD (SP) IYH 2 4 15 11 100 101 E5 SP SP - 1 (SP) IYL (SP) qqL SP SP + 1 11 qq0 001 1 3 10 (SP) qqH SP SP + 1 (SP) IXL 11 011 101 DD SP SP + 1 2 4 14 11 100 001 E1 (SP) IXH SP SP + 1 (SP) IYL 11 111 101 FD SP SP + 1 2 4 14 11 100 001 E1 (SP) IYH SP SP + 1 dd is any of the register pair BC, DE, HL, SP. qq is any of the register pair BC, DE, HL, AF. = flag is not affected, 0 = flag is reset, 1 = flag is set, b = flag is set according to the result of the operation.

qq 00 01 10 11

Pair BC DE HL AF

Z80 Instruction Set

Page 3 of 11

EE422

2009/2010

INELECSHARE.ICR38.NET INELEC.COMXA.COM
Page 4

Exchange, Block Transfer and Search Instructions


Mnemonic EX DE, HL EX AF, AF EXX EX (SP), HL EX (SP), IX EX (SP), IY Symbolic Flags Opcode Opcode # of No. of T # of ~ Operation S Z F5 H F3 P/V N C 76 543 210 Hex Bytes States 11 101 011 EB 1 1 4 DE HL 00 001 000 08 1 1 4 AF AF BC BC 11 011 001 D9 1 1 4 DE DE HL HL (SP+1) H 11 100 011 E3 1 5 19 (SP) L 11 011 101 DD (SP+1) IXH 2 6 23 11 100 011 E3 (SP) IXL 11 111 101 FD (SP+1) IYH 2 6 23 11 100 011 E3 (SP) IYL (DE) (HL) 11 101 101 ED DE DE + 1 1 2 3 2 4 16 b 0 b b 0 10 100 000 A0 HL HL + 1 BC BC 1 (DE) (HL) DE DE + 1 21 11 101 101 ED 2 5 HL HL + 1 1 2 b 0 b 0 0 10 110 000 B0 2 4 16 BC BC 1 repeat until: BC = 0 (DE) (HL) 11 101 101 ED DE DE 1 1 2 3 2 4 16 b 0 b b 0 10 101 000 A8 HL HL 1 BC BC 1 (DE) (HL) DE DE 1 21 11 101 101 ED 2 5 HL HL 1 1 2 b 0 b 0 0 10 111 000 B8 2 4 16 BC BC 1 repeat until: BC = 0 A - (HL) 11 101 101 ED 4 4 5 4 6 3 2 4 16 HL HL + 1 b b b b b b 1 10 100 001 A1 BC BC 1 A - (HL) HL HL + 1 21 2 5 11 101 101 ED BC BC 1 4 4 5 4 6 3 b b b b b b 1 10 110 001 B1 Repeat until: 2 4 16 A = (HL) or BC = 0 A - (HL) 11 101 101 ED 4 4 5 4 6 3 HL HL 1 2 4 16 b b b b b b 1 10 101 001 A9 BC BC 1 A - (HL) HL HL 1 21 2 5 11 101 101 ED BC BC 1 4 4 5 4 6 3 b b b b b b 1 10 111 001 B9 Repeat until: 2 4 16 A = (HL) or BC = 0 1 F5 is a copy of bit 1 of A + last transferred byte, thus (A + (HL))1 2 F3 is a copy of bit 3 of A + last transferred byte, thus (A + (HL))3 3 P/V flag is 0 if the result of BC 1 = 0, otherwise P/V = 1. 4 These flags are set as in CP (HL) 5 F5 is copy of bit 1 of A last compared address - H, thus (A (HL) H)1. H is as in F after the comparison. 6 F3 is copy of bit 3 of A last compared address - H, thus (A (HL) H)3. H is as in F after the comparison. = flag is not affected, 0 = flag is reset, 1 = flag is set, b = flag is set according to the result of the operation. Comments

LDI

LDIR

if BC 0 if BC = 0

LDD

LDDR

if BC 0 if BC = 0

CPI

CPIR

if BC 0 and A (HL). if BC = 0 or A = (HL)

CPD

CPDR

if BC 0 and A (HL). if BC = 0 or A = (HL)

Notes:

Flag Notation:

Z80 Instruction Set

Page 4 of 11

EE422

2009/2010

INELECSHARE.ICR38.NET INELEC.COMXA.COM
Page 5

8-bit Arithmetic and Logical Instructions


Mnemonic ADD A, r ADD A, p* ADD A, q* ADD A, n ADD A, (HL) ADD A, (IX + d) Symbolic Operation AA+r AA+p AA+q AA+n A A + (HL) A A + (IX + d) A A + (IY + d) A A + s + CY AA s A A s CY A A AND s A A OR s A A XOR s As rr+1 pp+1 qq+1 (HL) (HL) + 1 (IX + d) (IX + d) + 1 (IY + d) (IY + d) + 1 Flags S Z F5 H F3 P/V N C b b b b b V 0 b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b 1 b b b b b b b b b b b b b b b b 1 0 0 b b b b b b b b b b b b b b b b b b b 1 b b b b b b b V V V V V 0 0 0 0 0 b b b b b b b b b 0 0 0 b Opcode 76 543 210 10 000 r 11 011 101 10 000 p 11 111 101 10 000 q 11 000 110 n 10 000 110 11 011 101 10 000 110 d 11 111 101 10 000 110 d 001 010 011 100 110 101 111 00 r 100 11 011 101 00 p 100 11 111 101 00 q 100 00 110 100 11 011 101 00 110 100 d 11 111 101 00 110 100 d Opcode Hex DD FD # of Bytes 1 2 2 2 1 DD 3 # of ~ 1 2 2 2 2 5 No. of T States 4 8 8 8 7 19 Comments r 000 001 010 011 100 101 111 Reg. B C D E H L A p 000 001 010 011 100 101 111 Reg. B C D E IXH IXH A

ADD A, (IY + d) ADC A, s SUB A, s SBC A, s AND s OR s XOR s CP s INC r INC p* INC q* INC (HL) INC (IX + d)

V V V V P P P V V V V V V

0 0 1 1 0 0 0 1 0 0 0 0 0

FD

19 s is any of r, n, (HL), (IX+d), (IY+d), p, q as shown for the ADD instruction. The underlined bits replace the underlined bits in the ADD set.

1 DD FD 2 2 1 DD 3

1 2 2 3 6

4 8 8 11 23 q 000 001 010 011 100 101 111 Reg. B C D E IYH IYL A

b b b b b b b b b b

INC (IY + d)

FD

23 m is any of r, p, q, (HL), (IX+d), (IY+d), as shown for the INC instruction. DEC same format and states as INC. Replace 100 with 101 in opcode.

DEC m

mm1

b b

101

Notes:

Flag Notation:

F5 and F3 are copied from the operand (s), not from the result of (A s). The V symbol in the P/V flag column indicates that the P/V flag contains the overflow of the operation. Similarly the P symbol indicates parity. r means any of the registers A, B, C, D, E, H, L. p means any of the registers A, B, C, D, E, IXH, IXL. q means any of the registers A, B, C, D, E, IYH, IYL. ddL, ddH refer to high order and low order eight bits of the register respectively. CY means the carry flip-flop. * means unofficial instruction. = flag is not affected, 0 = flag is reset, 1 = flag is set, b = flag is set according to the result of the operation.

Z80 Instruction Set

Page 5 of 11

EE422

2009/2010

INELECSHARE.ICR38.NET INELEC.COMXA.COM
Page 6

16-bit Arithmetic Instructions


Mnemonic ADD HL, ss ADC HL, ss SBC HL, ss ADD IX, pp ADD IY, rr INC ss INC IX INC IY DEC ss DEC IX DEC IY Opcode Opcode # of No. of T # of ~ 76 543 210 Hex Bytes States 00 ss1 001 1 3 11 11 101 101 ED 2 4 15 HL HL + ss + CY b1 b1 b2 b2 b2 V1 0 b1 01 ss1 010 11 101 101 ED 2 4 15 HL HL ss CY b1 b1 b2 b2 b2 V1 1 b1 01 ss0 010 11 011 101 2 2 2 1 DD 2 4 15 IX IX + pp b b b 0 b 00 pp1 001 11 111 101 2 2 2 1 FD 2 4 15 IY IY + rr b b b 0 b 00 rr1 001 00 ss0 011 1 1 6 ss ss + 1 11 011 101 DD 2 2 10 IX IX + 1 00 100 011 23 11 111 101 FD 2 2 10 IY IY + 1 00 100 011 23 00 ss1 011 1 1 6 ss ss 1 11 011 101 DD 2 2 10 IX IX 1 00 101 011 2B 11 111 101 FD 2 2 10 IY IY 1 00 101 011 2B The V symbol in the P/V flag column indicates that the P/V flag contains the overflow of the operation. ss means any of the registers BC, DE, HL, SP. pp means any of the registers BC, DE, IX, SP. rr means any of the registers BC, DE, IY, SP. 16 bit additions are performed by first adding the two low order eight bits, and then the two high order eight bits. 1 Indicates the flag is affected by the 16 bit result of the operation. 2 Indicates the flag is affected by the 8 bit addition of the high order eight bits. CY means the carry flip-flop. = flag is not affected, 0 = flag is reset, 1 = flag is set, b = flag is set according to the result of the operation. Symbolic Operation HL HL + ss Flags S Z F5 H F3 P/V N C 2 2 2 1 b b b 0 b Comments ss 00 01 10 11 pp 00 01 10 11 rr 00 01 10 11 Reg. BC DE HL SP Reg. BC DE IX SP Reg. BC DE IY SP

Notes:

Flag Notation:

General Purpose Arithmetic and CPU Control Instructions


Mnemonic Symbolic Flags Opcode Opcode # of # of No. of T Comments Operation S Z F5 H F3 P/V N C 76 543 210 Hex Bytes ~ States Converts A into packed BCD following add or b b b b b P b 00 100 111 27 1 1 4 subtract with BCD operands. __ 1 1 00 101 111 2F 1 1 4 Ones complement. AA b 1 b 1 11 101 101 ED A0A 2 2 8 Twos complement. b b b b b V 1 b 01 000 100 44 __ 1 2 1 00 111 111 3F 1 1 4 Complement carry flag. CY CY b b b 0 b 1 1 00 110 111 37 1 1 4 CY 1 b 0 b 0 1 No operations 00 000 000 00 1 1 4 CPU halted 01 110 110 76 1 1 4 IFF1 0 11 110 011 F3 1 1 4 IFF2 0 IFF1 1 11 111 011 FB 1 1 4 IFF2 1 11 101 101 ED Set interrupt 2 2 8 01 000 110 46 mode 0 11 101 101 ED Set interrupt 2 2 8 01 010 110 56 mode 1 Set interrupt 11 101 101 ED 2 2 8 mode 2 01 011 110 5E The V symbol in the P/V flag column indicates that the P/V flag contains the overflow of the operation. Similarly the P symbol indicates parity. 1 F5 and F3 are a copy of bit 5 and 3 of register A _ 2 H contains the previous carry state (after instruction H C) 3 No interrupts are issued directly after a DI or EI. 4 This instruction has other unofficial opcodes, see Opcodes list. CY means the carry flip-flop. = flag is not affected, 0 = flag is reset, 1 = flag is set, b = flag is set according to the result of the operation.

DAA

CPL NEG
4

CCF SCF NOP HALT DI EI


3

IM 0 IM 1 IM 2

Notes:

Flag Notation:

Z80 Instruction Set

Page 6 of 11

EE422

2009/2010

INELECSHARE.ICR38.NET INELEC.COMXA.COM
Page 7

Rotate and Shift Instructions


Mnemonic RLCA RLA RRCA RRA RLC r RLC (HL) Symbolic Operation S Z F5 b b b b b b b Flags H F3 0 b 0 b 0 b 0 b 0 0 b b b P/V N 0 0 0 0 P P 0 0 C b b b b b b b Opcode 76 543 210 00 000 111 00 010 111 00 001 111 00 011 111 11 001 011 00 000 r 11 001 011 00 000 110 11 011 101 11 001 011 d 00 000 110 11 111 101 11 001 011 d 00 000 110 11 011 101 11 001 011 d 00 000 r 11 111 101 11 001 011 d 00 000 r 010 001 011 100 110 101 111 11 101 101 01 101 111 Opcode Hex 07 17 0F 1F CB CB DD CB # of Bytes 1 1 1 1 2 2 # of ~ 1 1 1 1 2 4 No. of T States 4 4 4 4 8 15 r 000 001 010 011 100 101 111 Comments

b b b b b b

RLC (IX + d)

23

Reg. B C D E H L A

RLC (IY + d) r (IX + d) RLC r (IX + d) r r (IY + d) RLC r (IY + d) r

b b

FD CB

23

LD r,RLC (IX + d)*

b b

DD CB

23

LD r,RLC (IY + d)* RL m RRC m RR m SLA m SLL m* SRA m SRL m RLD RRD

b b b b b b b b b b b b b b b b

b b b b b b b b b b

0 0 0 0 0 0 0 0 0 0

b b b b b b b b b b

P P P P P P P P P P

0 0 0 0 0 0 0 0 0 0

b b b b b b b b

FD CB

23

Instruction format and states are the same as RLC. Replace 000 with new number.

b b b b

ED 6F

18

Notes: Flag Notation:

11 101 101 ED 2 5 18 01 100 111 67 The P symbol in the P/V flag column indicates that the P/V flag contains the parity of the result. r means any of the registers A, B, C, D, E, H, L. * means unofficial instruction. CY means the carry flip-flop. = flag is not affected, 0 = flag is reset, 1 = flag is set, b = flag is set according to the result of the operation.

Z80 Instruction Set

Page 7 of 11

EE422

2009/2010

INELECSHARE.ICR38.NET INELEC.COMXA.COM
Page 8

Bit Manipulation Instructions


Mnemonic BIT b, r BIT b, (HL)
5

Symbolic Operation _ Z rb ___ Z (HL)b _____ Z (IX + d)b

Flags S Z F5 H F3 P/V N C b b b b b b
1 1 1

b b b

1 1

b b b

b b b

0 0

BIT b, (IX + d)

BIT b, (IY + d)

_____ Z (IY + d)b rb 1 (HL)b 1

b b

SET b, r SET b, (HL)

Opcode 76 543 210 11 001 011 01 b r 11 001 011 01 b 110 11 011 101 11 001 011 d 01 b 110 11 111 101 11 001 011 d 01 b 110 11 001 011 11 b r 11 001 011 11 b 110 11 011 101 11 001 011 d 11 b 110 11 111 101 11 001 011 d 11 b 110 11 011 101 11 001 011 d 11 b r 11 111 101 11 001 011 d 11 b r

Opcode Hex CB CB DD CB

# of Bytes 2 2

# of ~ 2 3

No. of T States 8 12

Comments r 000 001 010 011 100 101 111 Reg. B C D E H L A

20

FD CB CB CB

20 b 000 001 010 011 100 101 110 111 Bit. 0 1 2 3 4 5 6 7

2 2

2 4

8 15

SET b, (IX + d)

(IX + d)b 1

DD CB

23

SET b, (IY + d)

(IY + d)b 1 r (IX + d) rb 1 (IX + d) r r (IY + d) rb 1 (IY + d) r mb 0 m r, (HL), (IX+d), (IY+d)

FD CB

23

LD r,SET b, (IX + d)*

DD CB

23

LD r,SET b, (IY + d)*

FD CB

23 To form new opcode replace 11 of SET b, s with 10. Flags and states are the same.

RES b, m

10

Notes:

Flag Notation:

The notation mb indicates bit b (0 to 7) of location m. BIT instructions are performed by an bitwise AND. 1 S is set if b = 7 and Z = 0 2 F5 is set if b = 5 and Z = 0 3 F3 is set if b = 3 and Z = 0 4 P/V is set like the Z flag 5 This instruction has other unofficial opcodes * means unofficial instruction. = flag is not affected, 0 = flag is reset, 1 = flag is set, b = flag is set according to the result of the operation.

Z80 Instruction Set

Page 8 of 11

EE422

2009/2010

INELECSHARE.ICR38.NET INELEC.COMXA.COM
Page 9

Input and Output Instructions


Mnemonic IN A, (n) IN r, (C) IN (C)* or IN F, (C)* INI Symbolic Operation A (n) r (C) Just affects flags, value is lost. (HL) (C) HL HL + 1 BB1 (HL) (C) HL HL + 1 BB1 Repeat until B=0 (HL) (C) HL HL 1 BB1 (HL) (C) HL HL 1 BB1 Repeat until B=0 (n) A (C) r (C) 0 Flags S Z F5 H F3 P/V N C b b b
1

0 0 b
3

b b b
1

P P X

0 0 b
2

b
3

b b b b b b
1 1

Opcode 76 543 210 11 011 011 n 11 101 101 01 r 000 11 101 101 01 110 000 11 101 101 10 100 010

Opcode Hex DB ED ED 70 ED A2

# of Bytes 2 2 2 2

# of ~ 3 3 3 4

No. of T States 11 12 12 16

Comments r 000 001 010 011 100 101 111 Reg. B C D E H L A

INIR

0 1

11 101 101 10 110 010

ED B2

2 2

5 4

21 16

if B 0 if B = 0

IND

b b

11 101 101 10 101 010

ED AA

16

INDR

0 1

11 101 101 10 111 010 11 010 011 n 11 101 101 01 r 001 11 101 101 01 110 001

ED BA

2 2

5 4

21 16

if B 0 if B = 0

OUT (n), A OUT (C), r OUT (C), 0* OUTI

D3 ED ED 71

2 2 2

3 3 3

11 12 12

OTIR

OUTD

OTDR

Notes:

Flag Notation:

(C) (HL) 11 101 101 ED 1 1 1 1 2 4 16 HL HL + 1 b b b X b X X X 10 100 011 A3 BB-1 (C) (HL) HL HL + 1 21 11 101 101 ED 2 5 if B 0 0 1 0 X 0 X X X BB1 10 110 011 B3 2 4 16 if B = 0 Repeat until B=0 (C) (HL) 11 101 101 ED 1 1 1 1 2 4 16 HL HL 1 b b b X b X X X 10 101 011 AB BB1 (C) (HL) HL HL 1 21 11 101 101 ED 2 5 if B 0 0 1 0 X 0 X X X BB1 10 111 011 BB 2 4 16 if B = 0 Repeat until B=0 The V symbol in the P/V flag column indicates that the P/V flags contain the overflow of the operation. Similarly the P symbol indicates parity. r means any of the registers A, B, C, D, E, H, L. 1 flag is affected by the result of B B 1 as in DEC B. 2 N is a copy bit 7 of the last value from the input (C). 3 this flag contains the carry of ( ( (C + 1) AND 255) + (C) ) 4 this flag contains the carry of ( ( (C 1) AND 255) + (C) ) * means unofficial instruction. = flag is not affected, 0 = flag is reset, 1 = flag is set, X = flag is unknown, b = flag is set according to the result of the operation.

Z80 Instruction Set

Page 9 of 11

EE422

2009/2010

INELECSHARE.ICR38.NET INELEC.COMXA.COM
Page 10

Jump Instructions
Mnemonic JP nn Symbolic Operation PC nn Flags S Z F5 H F3 P/V N C Opcode 76 543 210 11 000 011 n n Opcode Hex C3 # of Bytes 3 # of ~ 3 No. of T States 10 ccc 000 001 010 011 100 101 110 Condition NZ Z NC C PO PE P Comments

JP cc, nn

if cc is true, PC nn

11 ccc 010 n n

10

JR e JR ss, e JP HL JP IX JP IY DJNZ e Notes: Flag Notation:

PC PC + e if ss is true PC PC + e PC HL PC IX PC IY

00 011 000 e 2 00 sss 000 e 2 11 101 001 11 011 101 11 101 001 11 111 101 11 101 001

18

2 2 2 1 2 2

3 3 2 1 2 2

12 12 7 4 8 8

111 M if ss is true if ss is false sss Condition 111 C 110 NC 101 Z 100 NZ if B = 0 if B 0

E9 DD E9 FD E9

BB1 00 010 000 2 2 8 10 if B 0 2 3 13 e 2 PC PC + e e is a signed twos-complement number in the range <126, 129> e 2 in the opcode provides an effective number of PC + e as PC incremented by 2 prior to the addition of e. = flag is not affected, 0 = flag is reset, 1 = flag is set, b = flag is set according to the result of the operation.

Call and Return Instructions


Z80 Instruction Set Page 10 of 11

EE422

2009/2010

INELECSHARE.ICR38.NET INELEC.COMXA.COM
Page 11
Mnemonic Symbolic Operation SP SP 1 (SP) PCH SP SP 1 (SP) PCL PC nn if cc is true, SP SP 1 (SP) PCH SP SP 1 (SP) PCL PC nn PCL (SP) SP SP + 1 PCH (SP) SP SP + 1 if cc is true, PCL (SP) SP SP + 1 PCH (SP) SP SP + 1 PCL (SP) SP SP + 1 PCH (SP) SP SP + 1 PCL (SP) SP SP + 1 PCH (SP) SP SP + 1 IFF1 IFF2 SP SP 1 (SP) PCH SP SP 1 (SP) PCL PC p
1

Flags S Z F5 H F3 P/V N C

Opcode 76 543 210 11 001 101 n n

Opcode Hex

# of Bytes

# of ~

No. of T States

Comments

CALL nn

CD

17

CALL cc, nn

11 ccc 100 n n

3 3

3 5

10 17

if cc is false if cc is true

RET

11 001 001

C9

10

RET cc

11 ccc 000

1 1

1 3

5 11

if cc is false if cc is true ccc 000 001 010 011 100 101 110 111 t 000 001 010 011 100 101 110 111 Condition NZ Z NC C PO PE P M p 0h 8h 10h 18h 20h 28h 30h 38h

RETI

11 101 101 01 001 101

ED 4D

14

RETN

1,2

11 101 101 01 000 101

ED 45

14

RST p

11 t 111

11

Notes: Flag Notation:

This instruction has other unofficial opcodes, see Opcode list. Instruction also IFF1 IFF2

= flag is not affected, 0 = flag is reset, 1 = flag is set, b = flag is set according to the result of the operation.

Z80 Instruction Set

Page 11 of 11

EE422

2009/2010