Structural Design : Intel, Folsom FSM: what is FSM, diff b/wn Mealy n Moore, Binary and one hot

encoding, how many flip flops fr traffic controller 2:1 MUX: one small application, he gave an opeartion of the device and asked me to tell the circuit. its mux What is Electron Migration, how to reduce it. what is Setup , Hold time and der violations, clock skew and is is adv for skew. PVT qns: what happens to Freq at higher temp. (better explain inversion temp effect) asked me to reduce boolean eqn: I used K map. what is pipelining, cache coherence, snoopy protocol, MESI, TLB synchronous flip flop verilog code difference between chop and chomp in perl what are regular expressions how to display files, how to display files of particular ownership in a dir, how to find status of tests running in back grnd, how to find disk size, how to find info abt partiicular instrctn, how to debug perl code, (use perl -d <file name>), then u can select break point what is diff b/w sram and dram, n their applications what is synthesis, tell some non-synthezable examples what is initial block in verilog and how is it different frm always, what is sensitivity list what is diff b/w blocking and non blocking, what is hash table n how is it different frm BST diff b/w flip flop and latch, diff b/w comppiler and interpreter rise time depends on which parameters, dynamic power consumption parameters in CMOS explain physical design flow, what is floor planning , partioning why partioning in p&R and as well in Synthesis. give some trade offs during partioning. what is clock skew, PVT, what happens to setup with positive skew, what is CTS, what r the diff structures used in CTS. there are 2 flip flops , one at left corner n other at right corner, how will u design to get clock skew zero. basically he is expecting u to answer abt .CTS and plz explain that, what happens to hold if Vds is reduced, what to setup if temp is increased and decreased. he is expecting to explain clearly about the fast and slow corners with proper reasons. try to read as much u can Electron Migration. we were discussing abt this nearly for 30 mins,.. he has given some real time problem and asked me to design following some constarints, (ex: increase metal width, reduce the temperature, place more via for solving Electron Migration). design tecniques to reduce critical path , rise time and fall time UNIX and Perl: Hash, duplicate program algorithm, when to use hash, how to copy files from one folder to other folder if u have number of files are above the critical value.( I said I will write a perl script to copy files like: Cp a* <dest> , like that using a-z). he kept on asking similar kind of algorithms with using hash and how to display their keys n index. system operation in perl, regular expression and asked me some qns based on that giving some patterns, asked me what is $_ variable and what are $1 - $9 variables,

He discussed about my Intel work :) Circuit Design Team : FDC, Intel, Folsom: there are 2 inverters, 2nd inv size is 4:2, then size the 1st inerter and also size the nand gate inverter given one path wtih many gates n ask u to optimise: use demorgans law given 3 flip flops and 2 combi logic between them, theres is setup time violation at first path, there is +ve slack at second path, design the circuit to remove setup time prob(ans: combine the combi logic and split them in to 2 equal parts) System Validation: Intel, Folsom: memory leakage page fault. segmentation fault. how to find seg fault bit shifting, addition, with carry, without carry, bitwise operations, and or xor number system conversions (eg. hex to binary so on) hashing? hash table? binary search tree (difference between BST and hash table) page size? (problem based on it) - simple problem (no. of pages = total address space / page size) parts of a computer ram harddisk memory controller, processor so on - need to know all parts cache? why cache? snoopy schemes? cache controller? why we need it? pipelining? memory cycle? Branch Target Buffer Explain memeory Hierarchy how to reduce miss rate how to reduce miss penalty

video connectors? know about all video connectors vga, dvi, hdmi just basic info enough what is bios? a little about it DMA? Polling? Interrupts? Bitwise map? Logic Analyzer? Oscilloscopes? Basic working differences between the two all that you have done with these devices how you can measure/debug using them? Debugging skills in general. Example question: If you open your laptop and screen is blank what all would you do?. If a music player doesn't play a song, what all would you do? PCI? Peripheral component interconnect Front End : Intel, Austin

1. CMOS inverter and sizing 2. ids vs vds curve and short circuit current graph 3. nand gate sizing 4. vtc curve 5. if pmos is of similar sizing to nmos then wat is the vtc curve? which is the better curve? what all better?? from customer point of view 6. he gave me a circuit and asked me to reduce timing between two points? just asked to brainstorm my ideas

1. cache coherency 2. comp arch project 3. write through and write back cache 4. one sequence follower circuit 11 detector 5. asked about design lab project

1. gave me two opcodes and pass it through data path control 2. 16 bit adder design and asked me to draw many circuits in it. 3. system verilog code and asked me to draw d after synthesis circuit

1. simple k-map 2. system with a serial input. system detects every 3 bits and gives out an output. for 001 s-signal is high/ 010- r-signal is high/ 011 one other signal. sources of clock skew and jitter Physical Verification at Intel: (PHONE) what is diff b/w LVS and DRC, what is DRC many qns from resume: did u simulate ur layout

can u explain ur kogge stone adder with any other adder, its advantages n disadvantages can u compare DWT with any other processor n explain its pros n cons u have 1000 cubes which makes one whole cube , remove the outer layer of the cube n how many cubes will be left.(they will mention the area of each cube, I dont remember exactly) STRUCTURAL DESIGN TEAM AT INTEL: Folsom (ONSITE)

round 1: All questions were from partitioning, routing, placement. No general questions. He would draw scenarios on board and ask to solve them. Slightly vague round. But he expects less. round 2: Asked to code two very simple perl programs on his laptop to remove some pattern from some file. It was easy. General questions on partitioning, placement, routing, floorplanning, power and ground lines so on and so forth. Study concepts of floorplanning placement routing electromigration very well. round 3: Full of STA. All basic scenarios asking what timing violation will occur how you can solve them so on. Again no general questions all were scenario drawn on board and asked to draw timing waveforms and show where what kind of violations occur. Technical questions from internship not very hard ones eg: what is clock gating? etc round 4: 30 minutes behavioral. what is your idea of good team. what is your idea of a bad team. experiences of bad team circumstances if any. what is your ideal dream role etc. next 30 minutes about sram project full explanation. In that he asks questions from what you explain. example: we designed for this particular value of snm and he'd ask what snm is. If you say 'noise' while explaining what snms are, he asked what is noise? When I said it can be capacitive coupling noise or inductive switching noise he asked what those are, so on... Circuit Design : FDC, Intel, Folsom (Onsite) KoggeStone Adder: full structure of kogge stone adder fr 8bit, explain Black odd, grey, grey odd n even cells.. draw critical path , try if u can optimise more. get prepared with adv n dis adv of this design with some other design. as usual PVT qns they will ask but jus bacis (like what will happen to leakage power at higher temp, thty didnt ask any thing else)

SRAM:

read operation, sizes , area, power speed improvement. adv of splitting in to banks, SA operation (we did not use any external circuitry) they asked some qns frm internship....

Circuit Design:

have an 6 input seq, design a circuit it will count if you have >= 2 1's in the sequence.... I tried Full adders and did some thing...basically they are seeing ur approach n ur optimisation skills...

Verification Team, Qualcomm, Raleigh: (phone) Which one is faster among linked list n array (array is faster, bcoz arranged in order, LL is in random order) What is virtual function, polymorphism Internship experience Diff b/w blocking n non blocking statement How do u pop out last element of a array Pre si validation : Oregon, Intel (phone) Cache coherency, snoopy protocols Why cache What is Page table entry, virtual memory What is valid bit n dirty bit Why TLB Problem on tag, index, offset Cache mappings n replacement algorithms Which one is better in hard ware implementation (write back and write thru cache)

How many tag comparators r needed for each mapping Testing Position: Qualcomm, Sand Diego 1ST INTERVIEW:(More of semiconductor devices but asked varied questions from rf digital also...this interview was kinda tricky since it had rf and all) Draw the cross section of nmos Explain operation of nmos EX-OR using mux(explain how u arrived at the solution by applying different inputs and which one suits ex-or) Given a multiplier(rf multiplier) with two input signals.What is the frequency spectrum of this? If you have a 8MHz video signal what is the sampling frequency Explain about discrete fourier transform and fast fourier transform. what are the differences VI characteristics of nmos threshold voltage of nmos...temperature dependence, W and L dependence..how will VI curve shift if different parameters are varied(like Vt,Temp,Oxide thickness) a circuit with R and C in series. Is this a low pass high pass or band pass filter. Why? replace R with L. Now is this low pass high pass or band pass? derive the transfer function for the above R L circuit. A 4 digit number PQRS= 9(SRQP) find the 4 digit number 2ND INTERVIEW:(More of Static timing analysis and this guy was kind of irritating..for every answer he was smiling sarcastically and asking..oh really? are u sure etc) My internships with Intel-particularly the architectural validation internship. dc char of cmos inverter explain how the pmos and nmos behave in different parts of the dc char what happens if clock is delayed in a system what is setup and hold time which is ok to have..setup violation or hold violation? why? how to rectify setup violation and how to rectify hold violation? write max time and min time equation design a simple edge detector circuit.it shud not use more than 2 gates. rf proj(he said his team has a gal frm uf and she also had same proj wen he interviewed her :P ) sram operation how to size the transistors in sram what is cell flipping in sram how did u measure the area of the sram how did u calculate noise margin write the Ids equation for nmos how does current Ids vary if supply voltage is increased decreased etc 3RD INTERVIEW(very standard) DFT ATPG, a circuit was given with SA0 fault how to diagonise fault what is path sensitizing threshold voltage of nmos cross section of nmos with operation and vi char

sram operation sizing of sram what kind of spice modelling and what spice scripts did u use while designing sram internship experience comp arch project basic timing analysis How to reduce delay in a system he asked a puzzle too..forgot..if i remem ll send !! System Validation: Intel, Folsom . Verification/Validation : (i) What are some of the tools you have used for debugging. (ii) What is your strategy to debug an error in a code. (iii) How will you a test a black box (iv) Explain a previous situation where you solved a bug and the steps you took. (v) How does a gdb debugger work? Have you used it? (vi) I will give you an object say TV how will you test it? Come up with a test plan to test the product. 2. Programming - C/C++ . You will be asked to write code (i) Problems based on Recursive functions (ii) Programs based on Arrays (iii) Programs based on Linked list (iv) What is use of static,volatile, virtual functions, inheritence, polymorphism, etc 3. Computer Architecture (i) Pipelining (ii) Basics of number system(binary,hex), shifting , xor, and, (iii) Design a given function using only nand gates (iv) Draw a full adder using gates (v) What is virtual memory ? Why is it used? What are pages? What is a page fault? (vi) Branch predictors,tomasulo, schedulers, (vii) Caches, types, use and all sort of questions on this area 4. Behavioral - HR round (i) Explain a situation where you had to disagree to a team's decision and how you delt with it. (ii) Explain a situation where you took up leadership responsibility (iii) Explain a situation where you had to mentor someone (iv) Did you have difference of opinion with your manager? (v) Explain a situation where you showed team work Onsite - for me: Computer architecture round: What happens when a key in keyboard is pressed. Questions on components of a computer system. Frequency divider circuit.

Counter circuit. Simple cache block replacement problem. Bitwise operations. C++: Pointer based problems If word stored is intel make it store letni without allocation of additional memory. If words my cafe are stored, then make it store cafe my without allocation of additional memory. Linked list inserting new entry code few pointer based problems. Some Miscellaneous questions: 1. 2. 3. 4. 5. What is logical effort? Logical effort for NAND and NOR? Why 2:1 ratio for Inverter? 3 input NOR with 3:1 ratio What are Universal Gates? Ans: NAND, NOR and Mux. Realize XOR gate with NAND? Design 4:1 Mux with 2:1 Mux? Ans. 2 parallel and 1 series, Select line S0 to 1st stage and S1 to 2nd stage Mux. 6. What is Cache Memory? How does it increase the performance? 7. What are RISC and CISC? 8. What do you know about device physics? 9. What is FSM? What are Mealy and Moore model? 10. Draw the FSM for this question? 11. X and Y inputs, X: 101 and Y: 111 when we X and Y as given above Z=1. Draw the FSM and which type of FSM Model is it and Why? 12. How do you open a file in Verilog? Ans. 13. Swap two variables in Verilog without using a third variable? 14. What are Blocking and Non-Blocking? 15. What is inter statement and Intra statement delay in Verilog? 16. How to write code in Verilog? Ans. Module and End module explanation 17. What are sensitivity list? What happens when you dont write them? Ans. You infer a latch. What does infer a latch mean? 18. Do we need to initialize sensitive lists them for combinational circuits as well? 19. Caps parallel and series connections net Cap values? 20. We have an RC network? What is time constant? T=0.69RC when 50% output and T=2.2RC when 90% output? 21. What happens to the resistance and Cap when you increase length and when you increase area? Talk cap increases. 1. What is an Op amp? 2. Can we design a Low gain Op amp (eg: gain around 0.05 or so) and where is it used? 3. Tell about Serial Links ,

4. How do you communicate in serial Links? 5. What are Linked Lists 6. Can you have Nested Linked Lists and if so where are they used? 7. What is Multi-fingering? 8. Describe the different Layout Techniques used in your Layout. 9. What is Faradays Law of Electromagnetics? 10. Describe the formulae for the above Law? 11. Why is there a negative sign in the formulae? What does that mean? 12. What all courses have you done? Static variable Pass by value and pass by refrence The for loop output for two cases o For (i=n; i<=2; i--) { For (j=I; j<=1; j--) { print i,j ; } } Answer : for n=4 : 4,3 4,2 4,1 3,2 3,1 2,1 What is inheritance and friendship in OOP What is the diff command in unix shell What iis the awk command in unix shell What is stl(it means standard template lib in c++) What is hashing Reduce Boolean expression: A_barB+ABC+BC_bar answer: B What is virtual memory What is cache and how does it improve performance Give a case in MOSEI that highlights one of its main disadvantages Genral questions: Why is man hole round? If you push the power button on your computer it doesnt power on, what will you do to power it. PLL

NVIDIA 1) Tell me an algorithm to calculate the size of your L1 Cache. Block size and associativity of the L1 if we have just CPU, L1 and memory with write allocate policy. 2) What is that which you can do with object oriented like c++ when compared to structured language like C? 3) Explain Virtual Functions and virtual classes

4) Do we have something like virtual constructors and virtual destructors in C++? If they are there, what is the need? 5) Then there was screen sharing interview where I had to code: a. Use C++ reference and calculate square of an integer b. Implement the memcopy() standard library function. 6) The first phone was easier: a. He had asked stuff from my projects and internship b. He had asked basic questions on cache. Replacement policies, victim cache and some coherency questions. c. Some system Verilog constructs for verif which are not there in Verilog. Qualcomm DQ event: Raleigh ASIC Design/Verif Team 1) How do you approach to test a design? Briefly give the whole procedure. 2) Asked to write some sample C functions to mask some bits in a register. 3) Asked how I verified one of my projects, which was horrible as he was expecting an industry based verification from me. 4) Asked me to write a constrained variable in system Verilog by giving somewhat difficult constraints. 5) Set up and Hold time. Briefly explain them. How do you correct the system if there are these timing violations? 6) Do you know about Clock Domain Crossing? As I knew, they asked me to write a Verilog code for the logic dictating the empty and full indication of an async fifo. Software Modeling Team 1) Asked about my interbsjip for like 10 min. 2) Next 45 min was writing code on the white board for doubly linked list methods. IP verification team 1) Asked very specific details about my internship. 2) Next 30 min was white board coding in system Verilog. They explained me a system which accepts requests from multiple peripherals and it should throw an error message if a 2nd request is got from the same peripheral at any point of time before the 1st request is acknowledged with a response. In between these 2 there can be any number of requests from the other peripherals. I had to write a system Verilog test from scratch. Requset and response had an address, peripheral ID. Backend SOC characterization Team 1) He asked me some questions on the CMOS circuits wrt power, timing and temperature

2) He asked me about BIST and SCAN chains 3) I had a ATPG project called PODEM which is an algorithm and he asked me to explain them. 4) Some other questions about the frequency and voltage of operation which may cause different kind of violations (set up/ hold). He asked me to explain them with a frequency versus voltage curve. Intel : Oregon Low power techniques, diff btwn static n dynamic CMOS how did we use metal layers, what is logic minimization all projects discussion any idea abt STA. NAND 2i/p dynamics CMOS impllementation Poly or Metal has more resistance

AMD qs: Boston -how did u simulate timing and power of layout -which tool you used -what is bubble shifting -gave cct of two ffs connected with combinational cct in between - how to simulate timing for this, what is worst case clock input condition, skew will affect what worst case, how to tackle it -what is electromigration-given an inverter connected to long wire and load where will u see unidirectional electromigration and bidirectional -two long wires in parallel with inverters at both ends of each- one wire goes from 0-1 whats the effect on other wire, whats the waveform, which node is miller effect seen, why waveform settles to zero after rise, how to avoid glitch from affecting next inverter NVIDIA qs: CA -how did you optimize your design -did u see hold time violation -clock dividers - divide by 3 and with 50% duty cycle -using 8:8 rom as comparator for 4 4bit nos -code for pairing nos (all poss combinations) in a given list of nos that add up to a specific sum

Juniper qs: California Round 1: -What is Moore/Mealy machines..differences

-Asynchronous FIFO -Random, constrained random and directed testing, -Assertions -Testing at interface of blocks -Code coverage -Intel verification experience in detail Round 2: -Intel verification in detail -Write code for: given a put function that takes in random no as input and a get function that returns a number as output. put is called 100 times and then get is called 100 times. write function such that output of get function is in ascending order and sorted. which data structure will you use -if the above code had to be called million times what data structure would you use - associative arrays and hash implementation -design a circuit that outputs a pulse whenever input goes from 1->0 or 0->1 at clock edge Round 3: -virtual functions -code for circuit that takes 16 bit input, counts the leading ones and gives output -extend above logic for 64 bit no divided into 4 blocks of 16 bits each -what is clock skew -how it affects circuit -setup and hold time constraints -solving set up and hold time failures in manufactured chip

INTEL, FDC: Folsom 1) If there are 256 numbers (0 to 255) that can come in any sequence....and a number can come any number of times....then design a hardware which stores the count for each number at any point of time. Answer : Register file with 256 locations.....each location is indexed by the location number (i.e. 0 to 255) and the content of each location is the count for that particular number. Then you may use a mux to select one of the locations...and an adder to increment the content by 1 and then store the incremented value back in the same location. Then they asked me some timing questions based on my design...setup and hold violations etc. 2) there are two components X and Y. Truth tables for X and Y are as follows: A

001 01z 10z 11z

B 00z 01z 10z 110 Now make a xor gate using component A and B.

Intel @ Oregon: Circuit Design Round: 1. Logical reduction of circuit. . Had nand and other logic gates and the aim is to reduce the gates (using NAND logic where there will be a false path) 2. Capacitances - two metals running parallel . orthogonally. Side wall capacitance 3. When wire length is reduced by 2 delay will be reduced by? RTL/Computer Architecture: 1. Basic Verilog Codes with sync and async reset 2. Mux implementation 3. Pipelining - basic questions 4. Types of caches and advantages in detail - their trade off\ Logic Design 1. Circuit Reduction 2. State diagram for vending machine which accepts dimes, nickles and quarters . (Trick is to do it in reduced number of states) 3. After state diagram, state table Some HR questions like 1. What would you do if you come across a team member who is very adamant 2. team work and examples where team work was useful, challenges faced and how did we overcome it

LSI: Minneapolis

if you are taking design lab this sem....be ready to answer questions on verification stuff..like DFT, BIST , Synthesis, if u have mentioned u know any scripting lang like perl..expect ques on it as well...interviews won't be much hard...if u r good with these thnigs..it shldnt be a prob...be a bit prepared abt comp arch..not much..but basics like cache, pipelining, ur project work..u shld be able to ans anything asked on ur projects...adder structure n how it is diff from others..things u learned from layout..this wont be asked much though bottomline...verification like dft,bist,verilog is imp digital design very imp...static timing analysis will be asked fr sure...fav topic ahe ..setup n hold time..how to overcome setup/hold time violations i guess this shld be enough..be ready with some basics of perl scripting n verilog/dft techniques