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Is about the shift registers in the Digital logic design an digital system design. In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, in which the output of each flip-flop is connected to the "data" input of the next flip-flop in the chain, resulting in a circuit that shifts by one position the "bit array" stored in it, shifting in the data present at its input and shifting out the last bit in the array, at each transition of the clock input. More generally, a shift register may be multidimensional, such that its "data in" and stage outputs are themselves bit arrays: this is implemented simply by running several shift registers of the same bit-length in parallel.
Shift registers can have both parallel and serial inputs and outputs. These are often configured as serial-in, parallel-out (SIPO) or as parallel-in, serial-out (PISO). There are also types that have both serial and parallel input and types with serial and parallel output. There are also bi-directional shift registers which allow shifting in both directions: L→R or R→L. The serial input and last output of a shift register can also be connected to create a circular shift register. These are the simplest kind of shift registers. The data string is presented at 'Data In', and is shifted right one stage each time 'Data Advance' is brought high. At each advance, the bit on the far left (i.e. 'Data In') is shifted into the first flip-flop's output. The bit on the far right (i.e. 'Data Out') is shifted out and lost.
The data are stored after each flip-flop on the 'Q' output, so there are four storage 'slots' available in this arrangement, hence it is a 4-Bit Register. To give an idea of the shifting pattern, imagine that the register holds 0000 (so all storage slots are empty). As 'Data In' presents 1,0,1,1,0,0,0,0 (in that order, with a pulse at 'Data Advance' each time—this is called clocking or strobing) to the register, this is the result. The left hand column corresponds to the left-most flip-flop's output pin, and so on.
So the serial output of the entire register is 10110000. It can be seen that if data were to be continued to input, it would get exactly what was put in, but offset by four 'Data Advance' cycles. This arrangement is the hardware equivalent of a queue. Also, at any time, the whole register can be set to zero by bringing the reset (R) pins high.
This arrangement performs destructive readout - each datum is lost once it has been shifted out of the right-most bit. This configuration allows conversion from serial to parallel format. Data is input serially, as described in the SISO section above. Once the data has been inputted, it may be either read off at each output simultaneously, or it can be shifted out and replaced.
In cases where the parallel outputs should not change during the serial loading process, it is desirable to use a latched output. In a latched shift register (such as the 74595) the serial data is first loaded into an internal shift register, then upon receipt of a load signal the state of the shift register is copied into a set of output registers. In general, the practical application of the serial-in/parallel-out shift register is to convert data from serial format on a single wire to parallel format on multiple wires.
Is about the shift registers in the Digital logic design an digital system design. In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, in which the output of each flip-flop is connected to the "data" input of the next flip-flop in the chain, resulting in a circuit that shifts by one position the "bit array" stored in it, shifting in the data present at its input and shifting out the last bit in the array, at each transition of the clock input. More generally, a shift register may be multidimensional, such that its "data in" and stage outputs are themselves bit arrays: this is implemented simply by running several shift registers of the same bit-length in parallel.
Shift registers can have both parallel and serial inputs and outputs. These are often configured as serial-in, parallel-out (SIPO) or as parallel-in, serial-out (PISO). There are also types that have both serial and parallel input and types with serial and parallel output. There are also bi-directional shift registers which allow shifting in both directions: L→R or R→L. The serial input and last output of a shift register can also be connected to create a circular shift register. These are the simplest kind of shift registers. The data string is presented at 'Data In', and is shifted right one stage each time 'Data Advance' is brought high. At each advance, the bit on the far left (i.e. 'Data In') is shifted into the first flip-flop's output. The bit on the far right (i.e. 'Data Out') is shifted out and lost.
The data are stored after each flip-flop on the 'Q' output, so there are four storage 'slots' available in this arrangement, hence it is a 4-Bit Register. To give an idea of the shifting pattern, imagine that the register holds 0000 (so all storage slots are empty). As 'Data In' presents 1,0,1,1,0,0,0,0 (in that order, with a pulse at 'Data Advance' each time—this is called clocking or strobing) to the register, this is the result. The left hand column corresponds to the left-most flip-flop's output pin, and so on.
So the serial output of the entire register is 10110000. It can be seen that if data were to be continued to input, it would get exactly what was put in, but offset by four 'Data Advance' cycles. This arrangement is the hardware equivalent of a queue. Also, at any time, the whole register can be set to zero by bringing the reset (R) pins high.
This arrangement performs destructive readout - each datum is lost once it has been shifted out of the right-most bit. This configuration allows conversion from serial to parallel format. Data is input serially, as described in the SISO section above. Once the data has been inputted, it may be either read off at each output simultaneously, or it can be shifted out and replaced.
In cases where the parallel outputs should not change during the serial loading process, it is desirable to use a latched output. In a latched shift register (such as the 74595) the serial data is first loaded into an internal shift register, then upon receipt of a load signal the state of the shift register is copied into a set of output registers. In general, the practical application of the serial-in/parallel-out shift register is to convert data from serial format on a single wire to parallel format on multiple wires.
Is about the shift registers in the Digital logic design an digital system design. In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, in which the output of each flip-flop is connected to the "data" input of the next flip-flop in the chain, resulting in a circuit that shifts by one position the "bit array" stored in it, shifting in the data present at its input and shifting out the last bit in the array, at each transition of the clock input. More generally, a shift register may be multidimensional, such that its "data in" and stage outputs are themselves bit arrays: this is implemented simply by running several shift registers of the same bit-length in parallel.
Shift registers can have both parallel and serial inputs and outputs. These are often configured as serial-in, parallel-out (SIPO) or as parallel-in, serial-out (PISO). There are also types that have both serial and parallel input and types with serial and parallel output. There are also bi-directional shift registers which allow shifting in both directions: L→R or R→L. The serial input and last output of a shift register can also be connected to create a circular shift register. These are the simplest kind of shift registers. The data string is presented at 'Data In', and is shifted right one stage each time 'Data Advance' is brought high. At each advance, the bit on the far left (i.e. 'Data In') is shifted into the first flip-flop's output. The bit on the far right (i.e. 'Data Out') is shifted out and lost.
The data are stored after each flip-flop on the 'Q' output, so there are four storage 'slots' available in this arrangement, hence it is a 4-Bit Register. To give an idea of the shifting pattern, imagine that the register holds 0000 (so all storage slots are empty). As 'Data In' presents 1,0,1,1,0,0,0,0 (in that order, with a pulse at 'Data Advance' each time—this is called clocking or strobing) to the register, this is the result. The left hand column corresponds to the left-most flip-flop's output pin, and so on.
So the serial output of the entire register is 10110000. It can be seen that if data were to be continued to input, it would get exactly what was put in, but offset by four 'Data Advance' cycles. This arrangement is the hardware equivalent of a queue. Also, at any time, the whole register can be set to zero by bringing the reset (R) pins high.
This arrangement performs destructive readout - each datum is lost once it has been shifted out of the right-most bit. This configuration allows conversion from serial to parallel format. Data is input serially, as described in the SISO section above. Once the data has been inputted, it may be either read off at each output simultaneously, or it can be shifted out and replaced.
In cases where the parallel outputs should not change during the serial loading process, it is desirable to use a latched output. In a latched shift register (such as the 74595) the serial data is first loaded into an internal shift register, then upon receipt of a load signal the state of the shift register is copied into a set of output registers. In general, the practical application of the serial-in/parallel-out shift register is to convert data from serial format on a single wire to parallel format on multiple wires.
A Register is a digital circuit that both stores data and moves data. The term shift register is used to highlight that the register also moves data. Since a shift register stores data it implemented using flip-flops. The flip-flop operation required is that of a D-type flip flop. Remember that the truth table for a D-type flip-flop is as follows:
Inputs Outputs Description D C Q Q
D D D Follows D
In other words, when a clock edge is detected (in this case rising clock edge) the output Q becomes equal to the input D. The D-type flip-flop can be implemented from a JK flip-flop as follows:
We can say that when a clock edge is detected the D-type flip-flop stores the value of D. For each bit that we want to store we require a flip-flop. Therefore if we require to store 4 bits then 4 flip-flops are needed. Each flip-flop stores one bit, that is each stage (the number of stages is often used to refer to the number of flip-flops a register contains and hence the number of bits it can store) of the register stores one bit.
There are a variety of implementations of shift registers. Simplified diagrams are shown below naming the various types possible (4-bit shift registers are shown).
K
J
C Q Q D C Q Q D C Q
Q
1. Serial-in Serial-out Data in Data out 1(a) Left to Right Data out Data in 1(b) Right to Left 111
4. Serial-in Parallel-out Data in Data out 3. Parallel-in Serial-out Data in Data out 2. Parallel-in Parallel-out Data in Data out Data in Data out 1(c) Rotate Left Data out Data in 1(d) Rotate Right 112 Note that the variations that exist for Serial-in Serial-out shift registers also exist for the other types of shift register. They are not shown here for simplicity.
The remaining sections of this chapter look at the implementation of each of the four types of shift register.
10.2 Serial-In Serial-Out Shift Registers
A Serial-in Serial-out shift register can be implemented using D-type flip-flops joined together, the output of one flip-flop used as the input to the next flip-flop. The circuit for a 4-bit Serial-in Serial-out shift register is shown below.
The operation of the serial-in Serial-out shift register can be easily explained. Consider the circuit shown. On each clock edge (rising in this case) we can say the following about the outputs of each stage of the register (i.e. each D-type flip-flop in the register):
Data out = Q 3 = D 3 = Q 2 ; Q 2 = D 2 = Q 1 ; Q 1 = D 1 = Q 0 ; Q 0 = D 0 = Data in;
Which simplifies to:
Data out = Q 2 ; Q 2 = Q 1 ; Q 1 = Q 0 ; Q 0 = Data in;
Hence we can use these equations to step through the register's operation.
Consider that all the flip-flops outputs are 0. If Data in is LOW, i.e. 0, and a rising clock edge occurs then the equations listed can be applied to determine the new outputs of the flip-flops, i.e.
D 0 C Q 0
D 3 C Q 3
D 1 C Q 1
D 2 C Q 2 Data in CLK Data out On each rising clock edge On each rising clock edge 113 Data out = Q 2 = 0; Q 2 = Q 1 = 0; Q 1 = Q 0 = 0; Q 0 = Data in = 0;
Q 0 Q 1 Q 2 Q 3 = Data out 0 0 0 0
There is no change. If Data in is HIGH, i.e. 1, and a rising clock edge occurs then once again the equations listed can be applied to determine the new outputs of the flip- flops, i.e.
Data out = Q 2 = 0; Q 2 = Q 1 = 0; Q 1 = Q 0 = 0; Q 0 = Data in = 1;
Q 0 Q 1 Q 2 Q 3 = Data out 1 0 0 0
A 1 is now present at the output of the first flip-flop. If Data in remains HIGH, i.e. 1, and another rising clock edge occurs then the flip-flop outputs become:
Data out = Q 2 = 0; Q 2 = Q 1 = 0; Q 1 = Q 0 = 1; Q 0 = Data in = 1;
Q 0 Q 1 Q 2 Q 3 = Data out 1 1 0 0
Data in is made LOW, i.e. 0, and another rising clock edge occurs. The flip-flop outputs become:
Data out = Q 2 = 0; Q 2 = Q 1 = 1; Q 1 = Q 0 = 1; Q 0 = Data in = 0;
Q 0 Q 1 Q 2 Q 3 = Data out 0 1 1 0
Data in is made HIGH, i.e. 1, and another rising clock edge occurs. The flip-flop outputs become:
Data out = Q 2 = 1; Q 2 = Q 1 = 1; Q 1 = Q 0 = 0; Q 0 = Data in = 1;
114 Q 0 Q 1 Q 2 Q 3 = Data out 1 0 1 1
We can see that the bit sequence 1101 has been serially shifted into the register. As rising clock edges continue to occur the sequence will be serially shifted out of the shift register, i.e.
Data in is made LOW, i.e. 0, and another rising clock edge occurs. The flip-flop outputs become:
Data out = Q 2 = 1; Q 2 = Q 1 = 0; Q 1 = Q 0 = 1; Q 0 = Data in = 0;
Q 0 Q 1 Q 2 Q 3 = Data out 0 1 0 1
Data in remains LOW, i.e. 0, and another rising clock edge occurs. The flip-flop outputs become:
Data out = Q 2 = 0; Q 2 = Q 1 = 1; Q 1 = Q 0 = 0; Q 0 = Data in = 0;
Q 0 Q 1 Q 2 Q 3 = Data out 0 0 1 0
Data in remains LOW, i.e. 0, and another rising clock edge occurs. The flip-flop outputs become:
Data out = Q 2 = 1; Q 2 = Q 1 = 0; Q 1 = Q 0 = 0; Q 0 = Data in = 0;
Q 0 Q 1 Q 2 Q 3 = Data out 0 0 0 1
Data in is made LOW, i.e. 0, and another rising clock edge occurs. The flip-flop outputs become:
Data out = Q 2 = 0; Q 2 = Q 1 = 0; Q 1 = Q 0 = 0; Q 0 = Data in = 0;
Q 0 Q 1 Q 2 Q 3 = Data out 0 0 0 0 115
At this point the shift register has returned to its original state of 0s at the outputs of the flip-flops. It can be seen therefore that with the circuit given a 4-bit number can be shifted serially into the register, where it is stored, before being shifted serially out of the shift register.
If it is desired that the data be rotated in the shift register the circuit would need to be modified as shown:
If ROTATE is HIGH then the effect is to pass Data in through the AND gate to the OR gate and block the Data out from the OR gate. This is the case because we know that (from Chapter 3) an AND gate will only give an output of 1 when both inputs are 1. When ROTATE is LOW then the effect is to block Data in and pass Data out to the input of the first flip-flop. Then, each time a rising clock edge is detected, the data will be rotated through the shift register.
10.3 Parallel-In Parallel-Out Shift Registers
A Parallel-in Parallel-out shift register can be implemented as follows.
Data in Data out CLK ROTATE
D 0 C Q 0
D 3 C Q 3
D 1 C Q 1
D 2 C Q 2 CLK Q 0 Q 1 Q 2 Q 3
D 0 C Q 0
D 3 C Q 3
D 1 C Q 1
D 2 C Q 2 D 0 D 1 D 2 D 3 Data in Data out 116 The operation of the Parallel-in Parallel-out shift register is straightforward. When a rising clock edge is detected the outputs become equal to the inputs, i.e.
Data out = Q 3 = D 3
Q 2 = D 2
Q 1 = D 1
Q 0 = D 0
= Data in
10.4 Serial-In Parallel-Out Shift Registers
A Serial-in Parallel-out shift register can be implemented using a circuit similar to a Serial-in Serial-out shift register, i.e. the D-type flip-flops are joined together and the output of one flip-flop used as the input to the next flip-flop. The circuit is:
The operation of the Serial-in Parallel-out shift register is the same as that of the Serial-in Serial-out register except that the Data out is n-bits for an n-bit register, in this case n = 4. Hence the data out is Q 0 , Q 1 , Q 2 and Q 3 . In the Serial-in Serial-out register Data out is Q 3 only.
10.5 Parallel-In Serial-Out Shift Registers
The Parallel-in Serial-out shift register is the most complex of the shift registers because it logic to determine whether you are loading data to the register or you are shifting data currently in the register. The circuit for a Parallel-in Serial-out register is shown on the following page. The circuit should be interpreted as follows. Each input to each flip-flop can either be data in or data shifted from the previous flip-flop. Which is required depends on the state of LOAD SHIFT / . If it is HIGH, i.e. we want the register to shift data (not read in new data) then the data in inputs are disabled because they are ANDed with 0. The shift data (the output of the previous flip-flop) is CLK Q 0 Q 1 Q 2 Q 3
D 0 C Q 0
D 3 C Q 3
D 1 C Q 1
D 2 C Q 2 Data out Data in 117 passed through to the input of the next flip-flop because it is ANDed with 1. When LOAD SHIFT / is LOW then we want to load new data to the register. In this case the data in is passed through to the input of each flip-flop and the shift data is blocked. The circuit is shown below:
Notice that the behaviour of the LOAD SHIFT / circuitry is the same as that of the ROTATE circuitry in Section 10.2.