COMP 2

Spec Ref

Topic
Hardware & Software

Revised

3.2.1

Fundamentals of Computer Systems

Classification of Software Types of Program Translators Generations of Programming Language

3.2.2

Fundamental Hardware Elements of Computers

Logic Gates Boolean Algebra Internal & External Hardware Components

3.2.3

Machine Level Architecture

Functional Characteristics of a Processor Structure & Role of a Processor Machine Code & Processor Instructions Fetch Execute Cycle & Role of registers? Input Devices Output Devices

3.2.4

Hardware Devices

Secondary Storage Devices Magnetic Media Optical Media Solid State Memory Internet & its Uses World Wide Web Intranet URL & URI

3.2.5

Structure of the Internet

Domain Names & IP Addresses Internet Registries & Internet Registrars Internet Service Providers Domain Name Server Client-Server Model Common Standard Protocols Web Page Construction

3.2.6

Web Page Design

HTML Style Sheets

3.2.7

Consequences of Uses of Computing

Legal & Ethical Issues Economic & Social Issues

COMP 2
Hardware- electric circuit that a computer is assembled from, the platform on which the software executes Software- sequence of instructions, known as a program, which are understood and executed by a computer Software

System Software

Application Software

Operating System

Library Program

Utility Programs

Translators

General Purpose

Special Purpose

Bespoke

System Software- performs tasks needed to operate the hardware Operating System- interface between the user and the hardware, providing a virtual machine Library Program- compiled procedures available to other programs to use Utility Programs- single task tool to manage the hardware Translators- Assembler: assembly language into machine code Compiler: high level programming language (source code) into object code Interpreter: analyses and executes a high level language program a line at a time Application Software- allows users to performs non-computer tasks General Purpose- can be used for many different tasks Special Purpose- designed to support one specific task Bespoke- written for an individuals specific needs

COMP 2
Low Level Programming Language
(reflects processor architecture)

High Level Programming Language

(source code)

First Generation: Machine code Binary pattern

Second Generation: Assembly language Mnemonic, e.g. ADD 6 Easier to use than machine code, uses less memory space, fast execution

Third Generation: Imperative (procedural) language Problem orientated Easier to maintain & read/write, easier to understand, no need to learn CPU architecture, portable Less efficient, requires more time for translation Compiler, Interpreter

Fourth Generation: Declarative language Defines what, not how Simple syntax, ignores flow of execution, nonprocedural so computer does calculations,

Executed directly by CPU

Must be written in binary code, need to learn CPU architecture, error-prone, not portable -

Unique to specific computers, not portable Assembler

Less efficient, less flexible

Compiler, Interpreter

Logic Gate- electronic circuit that performs a Boolean function A B 0 1 0 1 B 0 1 0 1 B 0 1 0 1 Q 0 0 0 1 Q 0 1 1 1 Q 0 1 1 1

AND

A.B=Q Output is true if all inputs are true

NAND- Output is true if any input is false

0 0 1 1 A

OR

A+B=Q Output is true if either or both inputs are true

0 0 1 1 A

NOR- Output is true when all inputs are false

A+B=Q

XOR
Output is true if either input is true, but not if both are true

0 0 1 1

__ A =Q
Output is the inverse of the input

A 0 1

Q 1 0

Truth Table- shows the result of applying the logical function to all possible combinations of inputs

COMP 2
Processor Main Memory

I/O

Bus
Central Processing Unit (CPU) is made up of the processor, main memory & system bus Main Memory- memory that is directly addressable by the processor Memory Location- a separately addressable area of main memory RAM (Random Access Memory)- volatile main memory in which locations can be accessed directly in any order with the same access time for all reading and writing operations ROM (Read Only Memory)- non-volatile main memory that cannot be written to once set up EEPROM (Electrically Erasable Programmable Read Only Memory)- main memory in which the contents may be altered but writing is 100 time slower than reading Computer Bus- set of parallel wires connecting independent components of a computer system System Bus- main highway connecting processor, main memory and I/O controllers Bus Control Data Address Wires 8-bit 32-bit 32-bit Direction Bidirectional Bidirectional Unidirectional Role Transmit control signals and timing signals Transports data between components Addresses memory and I/O controllers

Processor

Main Memory

VDU Controller

Control Bus Data Bus Address Bus

Peripherals- computer device that is not part of the CPU I/O- allows CPU to communicate with peripherals I/O Device- hardware unit that sends/receives or stores data by communicating with the processor and main memory through an I/O controller I/O Controller- electronic circuit that connects to the system bus and an I/O device, provides correct current and voltage for both Secondary Storage- permanent storage memory that is not directly connected to the processor, type of peripheral (e.g. magnetic hard disk) Processor exchanges data with a peripheral through part of an I/O controller called an I/O port, system bus cannot be directly connected to the processor so it must be connected to the I/O controller which connects to the I/O device

COMP 2
Main Memory Address- a unique numeric code that corresponds to a location in memory Addressable Memory1. 2. 3. 4. Each location in memory has its own unique address Processor selects a location by putting the corresponding address onto the address bus Processor asserts over the control bus whether to write to the location or read from it Processor uses the data bus to transfer bytes between itself and the addressed memory location

NB: system bus is a shared bus as each location shares access with all other locations at all times Stored Program Concept1. Program must be resident in main memory to be executed 2. It is processed by fetching machine code instructions in sequence from main memory 3. These are executed on at a time by the ALU Von Neumann- serial, instruction fetches and data references share same bus, more competition for resources, decreases processing speed Harvard- parallel, instruction fetches and reading/writing of data have separate buses, separate instruction and data memories, no competition for resources, increases processing speed Microcontroller- CPU and I/O on a single chip used as embedded computer, cheap, compact, performs a few dedicated functions (e.g. mp3 player, router) Components of a Processor Program Control Unit- fetches instructions from memory, decodes and executes them) Arithmetic & Logical Unit Registers- very fast memory locations General purpose registers are not assigned a specific role by the processor designer Dedicated registers are assigned a specific role by the processor designer Internal Clock Internal Buses- link PCU, ALU & registers Logic Gates- flow control Purpose Points to a stack holding return addresses (parameters, local variables) Points to the next instruction to be fetched and executed Holds condition codes to indicate outcome of operations Holds the result of the current set of calculations Holds the address of the memory location currently being accessed Holds the data item being transferred to/from the memory location currently being accessed Holds the most recently fetched instruction to be executed while it is decoded and executed

Dedicated Registers SP PC SR ACC MAR MBR CIR Stack Pointer Program Counter Status Register Accumulator Memory Address Register Memory Buffer Register Current Instruction Register

COMP 2
Clock Speed (MHz or GHz) - frequency at which the processor executes instructions Increasing clock speed increases processor speed
[Limits are set as a higher clock speed generates more heat, as does an increase in transistors. Multicore processors have an increased number of transistors and use a lower clock speed. Many processors are put onto one chip so multiple tasks can be run at the same time or a single task can be split into several processors.]

Word Length- number of digits in a binary word Increasing word length increases processor speed Bus Width- number of signal wires (lines) allocated to a bus Increasing address bus width allows more memory to be addressed Increasing data bus width increases processor speed Machine Code Instruction- a binary code that a machine can understand and execute

OP-CODE
Part of a machine code instruction that denotes the basic machine operation

OPERAND

Part of a machine code instruction that represents a single item of binary data (or the address of a single item of binary data

Op Code LOAD ADD STORE

Operand #6 4 5

Meaning Place 6 into ACC Sum contents of accumulator and contents of memory location 4, place result in ACC Place a copy of ACC contents in memory location 5

Compiled High Level Language- program translated into machine code before it is executed on a digital computer Binary codes are often represented in hexadecimal which is: Displayed in less space Less prone to errors Easier to read and understand

Instruction Set- the set of bit patterns/ binary codes for the machine operations that a processor has been designed to perform Step 1 2 3 4 Register Transfer Notation MAR [PC] PC [PC] + 1 MBR [Memory]addressed CIR [MBR] [CIR] decoded Description Contents of PC is transferred to the MAR Contents of PC is incremented by 1 Contents of the addressed memory location is loaded into MBR Contents of MBR is transferred into CIR Instruction held in CIR is decoded and executed

COMP 2
Fetch-Execute Cycle: The address of the next instruction to be executed (contents of Program Counter) is copied into Memory Address Register. At the same time, the contents of the Program Counter is incremented by 1. The instruction held at that memory address is placed in the Memory Buffer Register. The contents of the Memory Buffer Register is copied into Current Instruction Register. The instruction held in the Current Instruction Register is decoded. If necessary, the data is fetched and the instruction is executed by the ALU. The address is sent over address bus. The instruction is transferred to the processor on the data bus and the result is stored in the Accumulator. Address in the MAR is sent down the address bus to main memory. Contents of the addressed location is accessed in main memory and passed down the data bus to the MBR. The two parts of the second step can take place at the same time because: One step does not rely on the other Steps are carried out by different hardware devices Operations are independent Operations use different registers

Internet- a network of computer networks and computers using unique IP addresses and TCP/IP Router- connects networks that use the same link layer Gateway- connects networks the use different link layers