PFL780 User Guide

Polar Fault Locator
PFL Operator Manual
Polar Instruments Ltd
Polar Instruments Ltd. Garenne Park St. Sampson Guernsey Channel Islands GY2 4AF ENGLAND http://www.polarinstruments.com Fax: +44 (0)1481 252476 Email: mail@polarinstruments.com MAN 1609904
PFL FAULT LOCATOR OPERATOR MANUAL

POLAR INSTRUMENTS LTD. HARDWARE WARRANTY
1. Product Warranty. Product hardware is warranted to be free from defects in material and workmanship during the Warranty Period (as defined below). Product hardware is warranted to conform substantially to Polars then current (as of the date of Polars product shipment) published user documentation during the Warranty Period. The Warranty Period is twelve (12) months. Product support beyond these periods may be available at additional cost consult Polar for details. Warranty Claims. Polar shall incur no liability under this warranty if the end user fails to provide Polar with notice of the alleged defect during the applicable Warranty Period and within seven (7) days of delivery to end user or, if the defect would not have been reasonably apparent on inspection, within seven (7) days of its discovery by end user. After receiving such notice, Polar will notify the purchaser of its designation of one of the following problem resolution methods: Return to Factory: The allegedly defective goods must be returned to Polar within seven days of Polars notice and in accordance with Polars instructions advised at the time. Other: Polar will use commercially reasonable efforts to repair, correct or work around the problem by means of telephone support or other means reasonably determined by Polar. Polar shall incur no liability under this warranty if Polars tests disclose that the alleged defect is due to causes not within Polars reasonable control, including alteration or abuse of the goods. Under the Return to Factory alternative, if a Product is determined not to be defective or to have a defect due to causes not within Polars reasonable control, Polar reserves the right to apply a processing charge. 3. Damage in Transit. End user must notify Polar and the carrier of any claim for damage in transit within two (2) days of receipt of the damaged merchandise. Failure to do so may result in the carrier and/or Polar refusing to accept liability in which case end user must pay the purchase price as if the hardware had been delivered without damage. Polars Liability Polars liability, and end users sole and exclusive remedy, shall be limited to the express remedies set forth in this Polar Hardware Warranty. Disclaimer of Warranties. POLAR MAKES NO OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, REGARDING PRODUCTS. ALL OTHER WARRANTIES AS TO THE QUALITY, CONDITION, MERCHANTABILLITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ARE EXPRESSLY DISCLAIMED. Limitation of Liability. POLAR SHALL NOT BE RESPONSIBLE FOR DIRECT DAMAGES IN EXCESS OF THE PURCHASE PRICE PAID BY THE END USER OR FOR ANY SPECIAL, CONSEQUENTIAL, INCIDENTAL, OR PUNITIVE DAMAGE, INCLUDING, BUT NOT LIMITED TO, LOSS OF PROFITS OR DAMAGES TO BUSINESS OR BUSINESS RELATIONS, WHETHER OR NOT ADVISED IN ADVANCE OF THE POSSIBILITY OF SUCH DAMAGES, THE FOREGOING LIMITATIONS SHALL APPLY, NOTWITHSTANDING THE FAILURE OF ANY EXCLUSIVE REMEDIES.
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Copyright Polar Instruments Ltd. 1996 Microsoft and MS-DOS are registered trademarks of Microsoft Corporation IBM is the registered trademark of International Business Machines Corporation.
DECLARATIONS
European Community Directive Conformance Statement

This product conforms to all applicable EC Council Directives, including: EC Council Directive 89/336/EEC on the approximation of the laws of the Member States relating to electromagnetic compatibility. EC Council Directive 73/23/EEC on the harmonisation of the laws of the Member States relating to electrical equipment designed for use within certain voltage limits. A declaration of conformity with the requirements of these Directives has been signed by: POLAR INSTRUMENTS (UK) LTD 11 College Place London Road Southampton England SO1 2FE Harmonised standards applied in order to verify compliance with these Directives: EN 50081-1:1992 EN 50082-1:1992 EN 61010-1:1993 EN 60950
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DECLARATIONS i
SAFETY
WARNING
The LIVE and NEUTRAL lines on this unit are BOTH fused. This unit contains no user-serviceable parts. When the unit is connected to its supply, the opening of covers or removal of panels is likely to expose dangerous voltages. To maintain operator safety, do not operate the unit unless the enclosure is complete and securely assembled.
GROUNDING
This unit must be earthed (grounded); do not operate the instrument with the safety earth disconnected. Ensure the instrument is connected to an outlet with an effective protective conductor terminal (earth). Do not negate this protective action by using an extension cord without a protective conductor. Note: This instrument is fitted with 3-wire grounding type plug designed to fit only into a grounding type power outlet. If a special local plug must be fitted to the power cord ensure this operation is performed by a skilled electronics technician and that the protective ground connection is maintained. The plug that is cut off from the power cord must be safely disposed of. Power cord color codes Power cord color codes are as follows: Europe brown blue green/yellow United States black white green live neutral ground live neutral earth (ground)
CAUTION
Electrical Isolation Always disconnect the board under test from the local mains supply (including ground) before using this instrument.
ii SAFETY
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POWER SUPPLY
Line voltage setting Check that the indicated line voltage setting corresponds with the local mains power supply. See the rear panel for line voltage settings. To change the line voltage settings refer the instrument to a skilled electronics technician. Instructions for changing the line voltage settings are contained in the Service Manual published by Polar Instruments.
PFL OPERATION
This document contains instructions and warnings which must be observed by the user to ensure safe operation. Operating this instrument in ways other than detailed in this manual may impair the protection provided by the instrument and may result in the instrument becoming unsafe. Retain these instructions for later use. The unit is designed for use indoors in an electrical workshop environment at a stable work station comprising a bench or similar work surface. Use only the accessories (e.g. test probes and clips) provided by Polar Instruments. The instrument must be maintained and repaired by a skilled electronics technician in accordance with the manufacturers instructions. If it is likely that the protection has been impaired the instrument must be made inoperative, secured against unintended operation and referred to qualified service personnel. Protection may be impaired if, for example, the instrument:
Shows signs of physical damage Fails to operate normally when the operating instructions are followed Has been stored for prolonged periods under unfavourable conditions Has been subjected to excessive transport stresses Has been exposed to rain or water or been subject to liquid spills
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SAFETY iii
Specifications
ASA Test Facilities

Test Channels (PFL760, PFL780) Test Ranges Junction Logic Low Med High Test Frequencies Low Medium High Pulse Generator DC, Pulse1, Pulse2 Tolerance adjustment ASA Links (PFL760, PFL780) Data logging of test results 90Hz 500Hz 2kHz 0 5V variable level (+/-5%) Pulse width variable (1 to 99%) 1 99% Identifies shorts to Common PFL760, PFL780 128 Vpk 1V 10V 10V 20V 40V Ipk 500A 5mA 150mA 1mA 1mA
ICT Facilities (PFL780 only)

Test Channels Voltage Thresholds Guard Outputs Test Time 40 TTL, CMOS, User Programmable 4 x High, 4 x Low <16ms (at 100% Step Rate) Complies with INT DEF STAN 0053/1 Identifies connected pins, pins stuck-high/low 5V, 5A (Active during ICT test only) Protected by 5A T fuse
ICT Links User Power Supply
iv Specifications
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Environmental operating conditions

The instrument is designed for indoor use only under the following environmental conditions:
Altitude Temperature Relative humidity Mains borne transients
Up to 2000m +5C to +40C ambient RH 80% maximum at 31C derate linearly to 50% at 40C As defined by Installation Category II (Overvoltage Category II) in IEC664 2 (IEC664)
Pollution Degree
Power Requirements
230V 10%, 115V 10% or 100V 10% at 50/60Hz, 110VA.
Channel A and B Protection Fuses

160mA Fast Blow
Physical characteristics (excluding accessories)

Dimensions 443 mm (17.44 in.) wide 114 mm (4.48 in.) high 280 mm (11.02 in.) deep Weight 7.0kg (15.4 lb.)
Symbols
The following symbols are used in this instrument. CAUTION To prevent damage to this product and to ensure its safe use observe the specifications given in this manual when connecting to terminals marked with this symbol. COM This terminal is internally connected to earth (ground).
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Specifications v
ACCESSORIES Standard Accessories

PFL software PFL780) Probe set Pair of Red and Black Test leads Pair of Pulse Generator leads User Supply lead set 16 way test clip and cable PFL780) 40 way test clip and cable PFL780) Foot Pedal PFL780) RS-232 interface cable Accessory pouch Operator manual Power Cord FSW144 (PFL760, FSW150 (PFL720) MMP159 ACC110, ACC111 ACC112 ACC151 (PFL780) ACC107 (PFL760, ACC106 (PFL760, ACC124 (PFL760, ACC142 ACC105 MAN160
Optional Accessories (PFL760, PFL780)

Adaptor Board Adaptor for PC card edge connectors ZIF Test Fixture Instrument carrying case SMD probes 9 25 Pin RS232 Adaptor SOIC Test Clip Set PLCC Test Clip Set DIP IC Test Clip Set 6 types DIP IC Test Clip Set 10 types PFL720 Service Manual PFL760 Service Manual PFL780 Service Manual T41282 T41283 ACC145 ACC125 T131 T141 ACC127 ACC160 ACC161 ACC140 ACC139 MAN168 MAN161 MAN164
vi Specifications
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Contents
DECLARATIONS......................................................................... i European Community Directive Conformance Statement ...... i SAFETY ...................................................................................... ii WARNING ............................................................................. ii GROUNDING ........................................................................ ii Power cord color codes .................................................... ii CAUTION............................................................................... ii Electrical Isolation ............................................................ ii POWER SUPPLY ..................................................................iii Line voltage setting ..........................................................iii PFL OPERATION ..................................................................iii Specifications........................................................................... iv ASA Test Facilities................................................................ iv ICT Facilities (PFL780 only).................................................. iv Environmental operating conditions....................................... v Power Requirements ............................................................. v Channel A and B Protection Fuses........................................ v Physical characteristics (excluding accessories) ................... v Symbols ................................................................................. v ACCESSORIES.................................................................... vi Standard Accessories........................................................... vi Optional Accessories (PFL760, PFL780).............................. vi Contents .................................................................................. vii Introducing the PFL Fault Locator........................................... 1 Introduction to the PFL Fault Locator..................................... 1 Product Registration .............................................................. 1 Analog Signature Analysis ..................................................... 2 Three terminal device testing with the Pulse Generator ... 2 In Circuit Testing.................................................................... 2 Displaying connection and logic faults.............................. 2 The PFL component library.................................................... 2 Areas of application ............................................................... 2 PC Control ............................................................................. 3 System requirements............................................................. 3 Installing the Fault Locator ...................................................... 4 Unpacking.............................................................................. 4 Connecting the PFL to a power supply .................................. 4 Installing the PFL software .................................................... 5
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Contents vii
Specifying the PFL instrument type ..................................6 Specifying the communication port ...................................6 Computer control of the PFL ..................................................6 Running the program .............................................................7 PFL main window .............................................................7 System Configuration.............................................................8 Setting up the PFL control program environment...................8 System Security................................................................8 Loop compensate.................................................................10 Diagnostics ..........................................................................10 Exiting the PFL program ......................................................10 General Description ................................................................11 Analog Signature Analysis ...................................................11 In Circuit Testing ..................................................................11 Controls and connectors ......................................................12 Front Panel .....................................................................12 Rear Panel......................................................................13 Getting started with the Fault Locator...................................14 Live Instrument testing .........................................................14 Live Instrument screen ...................................................14 Using the PFL probes .....................................................14 Defining test conditions ........................................................15 Test Range selection ......................................................15 The PFL Pulse Generator ...............................................19 Testing integrated circuits ....................................................22 Testing devices using Quicktest...........................................22 Comparison testing with Quicktest..................................22 Single board testing with Quicktest.................................28 Asa Device Testing..................................................................29 Signature shapes............................................................29 Testing passive components with ASA ................................30 Testing Resistors ............................................................30 Testing Capacitors..........................................................32 Testing Inductors ............................................................34 ASA testing of semiconductors .............................................35 Testing diodes, LEDs and Zeners...................................35 Testing Transistors .........................................................36 Testing Junction Field Effect Transistors (JFETs) ..........39 Testing MOSFETS ...............................................................40 Testing special devices ........................................................41 Testing Opto-Isolators ....................................................41 Testing four-terminal devices..........................................43
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Testing integrated circuits using ASA .................................. 46 Integrated Circuits .......................................................... 46 Testing Devices in Circuit ............................................... 49 Bus-connected devices .................................................. 50 ICT device testing ................................................................... 51 PFL780 In Circuit Functional Test........................................ 51 Device testing with ICT ........................................................ 51 Testing devices in circuit ................................................ 52 Backdriving..................................................................... 53 The PFL780 Device Library ................................................. 54 ICT testing of digital ICs....................................................... 54 The Power On ICT test ........................................................ 54 Links Test ....................................................................... 55 Functional Test............................................................... 55 Controlling test conditions .............................................. 55 Acquiring device signatures ................................................. 56 Testing the device................................................................ 57 Links diagram ................................................................. 57 Stuck pins....................................................................... 58 Application hints................................................................... 59 Using Loop until Pass when ICT results are unstable .... 59 Initialising devices .......................................................... 59 Isolating devices in circuit .................................................... 59 Bus-connected (tristate) devices .................................... 59 Writing test programs............................................................. 65 The Program window........................................................... 65 Backing up test programs............................................... 66 Working with Test Programs .......................................... 66 Creating a new test program................................................ 66 Adding a board layout bitmap......................................... 66 Adding devices to the test list ......................................... 67 Associating a device with the board image..................... 68 Testing the board via the board image ........................... 69 Board Notes ................................................................... 71 Deleting a device location............................................... 71 Saving the test program ................................................. 71 Naming test programs .................................................... 71 Viewing ASA signatures ...................................................... 72 Viewing ICT data ................................................................. 73 Logic Diagram ................................................................ 73 Viewing Links data............................................................... 73 Board testing........................................................................ 74 Testing a board .............................................................. 74 Advanced Editing................................................................. 75 Using the Advanced Edit dialog box............................... 75 Datalogging.......................................................................... 79 The PFL Datalog function............................................... 79
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Contents ix
Adding devices to the Library with DevLib ...........................81 The PFL User Library...........................................................81 Adding a new device to the Library.................................81 Creating device aliases...................................................82 Maintenance and cleaning ......................................................83 Servicing the PFL.................................................................83 Calibration requirements.................................................83 Troubleshooting ..............................................................83 Cleaning .........................................................................84 Technical Support...........................................................84 APPENDIX B ASA Comparison Algorithm ........................ B1 APPENDIX C PFL Pin numbering formats......................... C1 APPENDIX D Test Clips and Probes .................................. D1 SMD Probes...........................................................................1 Pin numbering...................................................................1 Using the probe ................................................................1 Replacing pins ..................................................................1 Connecting to DIL ICs ............................................................ D3 Connecting to SOICs.............................................................. D4 Connecting to PLCCs, QFPs, etc. ......................................... D5
x Contents
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Introducing the PFL Fault Locator
Introduction to the PFL Fault Locator

The PFL series Fault Locators provide a fast and efficient means of testing electrical components, either in isolation or in circuit. The Fault Locators are designed to run under the control of an IBM PC or compatible host computer within the Windows 95 or Windows NT operating system. The PFL720 is a "virtual instrument" providing two channels of Analog Signature Analysis (ASA). The PFL760 has 128 ASA channels, and allows the user to write and store test programs. The PFL780 extends fault coverage by including digital in circuit functional testing (ICT) in addition to ASA. The PFL760-EX and PFL780-EX versions include all the test facilities of the standard instrument, but the user is not able to write or save programs. These versions can be upgraded to the standard version using the appropriate upgrade kit. Contact your supplier for details.
About this manual

This manual covers all instruments in the PFL family, therefore some of the features described may not be applicable to your instrument.
Product Registration
Registering your product ensures you can be kept up to date when upgrades or enhancements become available. Please register using the form at the front of this manual, or select "Register Software" in the Help About screen to print out a suitable form.
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Introducing the PFL Fault Locator 1
Analog Signature Analysis

Using the Analog Signature Analysis method, safe, low power drive voltages are applied to components to produce an "impedance signature" on the PC screen. All testing is done with power disconnected from the circuit, so there is no risk to the user and components under test cannot be damaged.
Libraries of good signatures can be compiled from good circuit modules and sent to service centres with PFL facilities and used for comparison in place of reference modules.
Good device signatures can be rapidly digitised, viewed and stored on the hard disk of the host computer and printed out as hard copy on a wide range of printers. The PFL can automatically compare signatures of suspect devices with the reference signatures stored on disk and print out test results and good and bad signatures for comparison.
Three terminal device testing with the Pulse Generator An integral Pulse Generator enables three-terminal devices such as transistors, SCRs and Triacs to be tested. See ASA Testing of semiconductors for three terminal device testing procedures.
In Circuit Testing
Using In Circuit Testing (ICT) the PFL780 compares the logical function of a device under test with a model of the corresponding device in its component database. The PFL780 is able to learn the operation of a device in circuit and use that configuration as a reference. Logical high and low guard voltages are provided on the PFL780 front panel to enable isolation of bus-connected devices. Displaying connection and logic faults The ICT software is able to detect and display connected pins and to display a logic timing diagram showing the status of the pins during testing.
The PFL component library

The PFL software includes a comprehensive database of integrated circuits in general use throughout the electronics industry.
Areas of application
The PFL is an ideal instrument for a wide range of applications:
Field Service fault finding.
2 Introducing the PFL Fault Locator
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Manufacturing Repair
goods inwards testing/troubleshooting. rapid diagnostics.
PC Control
The PFL software operates under the control of an IBM PC (or compatible) host computer within the Microsoft Windows environment. Commands and data are transferred over a high speed RS232-C link via one of the host's serial communication ports. The program provides an integrated environment for writing test programs, acquiring, viewing and storing device signatures, and controlling system security. Signatures may be readily digitised and stored for reference on the hard disk of the host computer and compared with the signatures of suspect devices or printed out for hard copy. Programs of device tests can be easily compiled and stored to hard disk and backed up to diskette for archiving or transfer to service organisations, repair centres, etc. The PFL allows the programmer to include a bitmapped image of the board under test in the program test file. The image is stored as part of the test file and provides a graphical means of selecting devices for testing. This feature will be especially useful when testing boards with no component identification.
System requirements
Before installing the PFL control program ensure that the host computer meets the following specifications:
Computer IBM PC or compatible Processor Pentium or better Memory 8Mbytes RAM (16Mbytes recommended) Video card and monitor VGA colour 3" diskette drive CDROM drive 20 Mbytes free space on hard disk RS 232 C Serial communication port Parallel printer port Operating system: Windows 95 (PFL software version v4.7 or lower); Windows 98 (PFL software version v4.7 or lower) Windows NT (PFL software version v5.50 or higher)
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Introducing the PFL Fault Locator 3
Installing the Fault Locator
Unpacking
The instrument is shipped in a sturdy transit pack. Open the pack carefully and remove the instrument and its accessories. Retain the pack for possible future use. If the instrument is damaged in any way contact the local distributor or supplier. The PFL pack should contain the instrument and its standard accessories (listed in the Specifications). Note: If the instrument has been shipped or stored in a cold environment, allow the instrument to reach the temperature of its new location before applying power.
Connecting the PFL to a power supply

Refer to the voltage label on the rear panel of the instrument and make sure that the marked rating is suitable for the local mains power supply. If the rating on the label is not suitable for the local power supply refer the instrument to a skilled electronics technician. Instructions for changing the line voltage settings are contained in the PFL Service Manual. Note: If a special local plug must be fitted to the power cord ensure this operation is performed by a skilled electronics technician and that the protective ground connection is maintained. The plug that is cut off from the power cord must be safely disposed of. Power cord color codes are as follows: Europe
brown blue green/yellow live neutral earth (ground) live neutral ground
United States
black white green
Connect the power cord to the instrument and to the power supply and switch on (the power switch is located at the rear of the instrument under the power inlet socket).
4 Installing the Fault Locator
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If the power on self test is completed successfully the SYSTEM OK LED is illuminated. A flashing SYSTEM OK LED indicates that one or more of the power-on diagnostics failed call your local distributor.
Installing the PFL software

Users are recommended to make working copies of the PFL installation diskettes before installation and store the master diskettes in a safe place. Backing up the installation diskettes
Insert the PFL Program diskette in the diskette drive. Double click the My Computer icon and click the icon for the diskette drive containing the PFL software. From the File menu, choose Copy Disk. Click the drive to Copy from and the drive to Copy to (you can use the same drive for both diskettes) and click Start. Repeat for the other diskettes. Both diskettes must be the same type. Any data on the Copy to disk will be deleted.
Installing the program

Close all other programs. Click the Start button choose Settings. Choose Control Panel Double Click the Add/Remove Programs icon. On the Install/Uninstall tab click the Install button. Insert the first PFL Software diskette in the drive and click Next. When Setup.exe appears in the Command line box click Finish. Follow the instructions on screen. For convenience an icon may be copied to the Desktop or added to the Start Menu by dragging onto the Start Button (see Introducing Windows 95).
The installation program will create the PFL folder and file structure and copy the PFL files onto the hard disk. Follow the instructions on screen to complete the installation. The installation will add the Polar Fault Locator folder (along with the program icons) to the Programs menu.
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Installing the Fault Locator 5
Specifying the PFL instrument type During the installation process it will be necessary to specify the PFL instrument. Select the correct type from the list displayed Note: it is possible to alter the PFL instrument setting after installation via the Config screen. Specifying the communication port During the installation process it will be necessary to specify the serial communication port connected to the PFL. If you are not certain which port is being used, leave this setting at its default. It is not necessary to specify the serial communication parameters they will be set by the PFL control program. Note: it is possible to alter the Com Port setting after installation via the Config screen.
Computer control of the PFL

PFL commands and data are transferred between the PFL and the host computer via a serial communication (RS 232) link using the supplied cable. Connecting the computer to the PFL Ensure the host computer and the PFL are both powered down before connecting cables. Connect the cable between the host computer's serial port and the connector on the rear of the PFL. Ensure the connections are secure. Power up the PFL and the host computer. To ensure correct operation of the instrument and to maintain its EMC compliance it is important to use the cable supplied with the product.
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Running the program

To start the program, double click the Polar Fault Locator icon the PFL opens the Main Screen.
The Polar Fault Locator icon
The PFL Main Screen opens with the most recently used test program displayed.
The PFL recalls the most recently used program (or an empty program named Untitled if no programs have been created).
PFL main window The main window comprises:

The Main Display window The Menu Bar The Tool Bar The Results Bar The Status Bar
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The Tool Bar and Results Bar may be left docked or dragged to a convenient location click the mouse into the Tool Bar area (avoid pressing a button) and drag to a suitable position.
Operating functions may be selected by clicking the associated button on the Tool Bar, or via the menu system, or by moving the highlight via the cursor keys to the desired option and pressing the <Enter> key.
System Configuration
The Utilities menu is provided to allow users to customise the PFL operating environment. From the Utilities menu the PFL programmer can: Select the language option for the instrument
Define passwords and operator access rights Specify which of the hosts serial communication ports will be used to transfer data and commands Add or remove libraries of devices Browse through the list of installed devices Perform a "loop compensation" routine which will null out the effects of capacitance in the hardware. Verify system operation using diagnostics. Change screen colors. Enable or disable prompts and alerts issued by the PFL.
Setting up the PFL control program environment

System Security The Utilities Config command allows a system supervisor to set up a password to protect test programs and system settings from accidental erasure or modification. The PFL system has two security states: Locked and Unlocked. When the system is unlocked, the operator has access to all facilities. When the system is locked test programs cannot be edited and access is blocked to the advanced editing functions, system configuration and the Initialise option (to clear the test results data log). If a user selects a protected function while the system is locked, he will be prompted to enter the password to unlock the system.
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Setting Passwords
To specify a password, from the Utilities menu: Choose the Config command. Click into the Password box and type the new password. The new password replaces the old password (if set). IMPORTANT: Keep a record of your password. Click into the Confirm box and retype the password exactly as in the Password box. The Enable password on exit option (checked by default) activates password protection as the Config dialog box is closed. Unchecking this box allows access to all facilities for the duration of the current session password protection will be activated the next time the PFL program is started.
Reduce Acquisition Priority

Select the Reduce Acquisition Priority box if the time to draw the Live instrument screen is very slow. This may be required on slower PCs and/or graphics cards. For optimum performance it is recommended that this option is not selected.
Changing Prompts
The Prompts tab displays a list of system prompts and alerts which may be enabled or disabled as required. For example, the user can enable or disable: The Board Notes window as a test file is opened System alerts issued when tests could yield invalid results, e.g. when Vcc and Gnd are missing from a device under test or open circuit pins are detected. The QuickStart dialog as the PFL is started The Show tips with device notes option with this box checked the PFL780 alerts the user when acquiring signatures for open collector and tristate devices that guard voltages may be necessary to prevent problems. See Isolating devices in circuit.
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Changing the system colors

Select the Colors tab to display the colors currently used for the PFL screen elements. To change a color click the screen element name in the dialog box then click the Name button. Click on the new color from the Color palette and Click on OK. Note: the PFL does not support dithered colors.
Changing the language option

Select the Language tab to display the current language setting. To alter this setting select the language required from the drop-down menu and Click on OK. If the language required is not displayed, contact your local supplier to determine if it is available.
Upgrading an -EX version instrument

Select the Upgrade tab (this is only displayed if an -EX version instrument is connected to the PC). Enter the code supplied with the upgrade kit.
Loop compensate
The PFL provides the facility to compensate for capacitance in the PFL hardware. Remove the clips from the device under test and from the Utilities menu select Loop compensate; the PFL performs an automatic loop compensation routine to "null out" the effects of stray capacitance.
Diagnostics
Selecting the Diagnostics command displays the Hardware Diagnostics dialog box. Tests can be turned on or off by clicking the associated check boxes. The Hardware Diagnostics include tests on the A and B Channel ASA fuses and the User Power/ICT fuse. See Servicing the PFL for details on changing fuses or for technical support.
Exiting the PFL program

To terminate the current session, select the File menu and choose Exit.
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General Description
Analog Signature Analysis

Using the ASA technique the PFL Fault Locator tests components by applying a current-limited alternating (AC) drive voltage across the component and monitoring the resultant current flow to display impedance signatures. Signatures for different types of components have distinctly different shapes that can be easily distinguished. Two channels, A and B, enable the signatures of a reference and a faulty component or circuit to be compared. Faults in complex circuits can be diagnosed without detailed knowledge of the circuit functions; this facility will be found particularly useful when documentation is not available.
In Circuit Testing
Using ICT, the PFL780 tests integrated circuits by comparing the logical operation of devices under test with the operation of an ideal corresponding device contained in a comprehensive library of digital components. The PFL780 component database includes a wide range of digital devices (from differing logic families) ranging from simple gates to microprocessors. The PFL780 is able to acquire signatures of a device in a known good circuit and use the device/configuration as reference. Device pins that are permanently at logical high or low (e.g. power supply lines and grounds) and interconnecting lines between pins are stored as part of the reference. During the ICT programming and testing process, pin connection and logic diagrams are displayed to show the relationship between control lines and signal inputs and outputs and provide a visual representation of the behaviour of each device pin. Logical high and low guard voltages are available at the PFL780 front panel to enable users to disable components in the vicinity of the device under test so the device may be tested in isolation without removal from circuit.
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General Description 11
Controls and connectors

Front Panel The front panel has connections for:
128 test channels on 4 IDC sockets Channel A and B probes. Two paralleled COM (common return) connectors. Two Pulse Generator paralleled outputs. ICT 5V power supply (PFL780 only). 4 ICT logical high (5V) and low (0V) guard voltages (PFL780 only).
Scanner Channels
Note: Always remember to connect the COM clip
The PFL Scanner provides the facility for rapid scanning of signatures on all pins of an IC under test. Signal return is via the COM connection. Channel A and B probes. The PFL is supplied with a pair of DVM style probes which are connected to the A and B sockets. The Channel A and B probes are connected in parallel with the Scanner inputs to facilitate checking for open circuit clip connection. When using the Live screen the PFL Scanner connectors are isolated and input to the PFL is from the probes only. COM (common return) connectors The PFL incorporates two paralleled COM (common return) connectors connect the COM test clip to the ground of the board (or boards) under test. If two boards are being compared, both grounds must be connected to the instrument's COM sockets. Pulse Generator outputs The PFL incorporates pulse generating circuitry which allows the conduction state of transistors, SCRs, Triacs and other 3terminal devices to be controlled by adjusting the level, width, polarity and time delay of pulsed outputs. Two outputs are provided to permit live comparisons of two boards
12 General Description
Polar Fault Locator
Connect the Pulse Generator cables to the two blue PULSE OUT sockets on the connector panel. The Pulse Generator produces identical outputs between each PULSE OUT socket and the black COM sockets. The PULSE OUT signals are driven individually so that, although the same pulse output appears on both connectors, a load on one output does not affect the other. ICT 5V power supply Use the PFL780 +5V ICT power supply to apply power to a board or device undergoing ICT testing. The +5V ICT power supply applies power only for the duration of the test. ICT guard voltages The PFL780 provides ICT logical high (5V) and low (0V) guard voltages for isolating bus-connected digital devices during testing. Up to 4 guard voltages may be applied to selected device control or enabling lines to isolate the device under test (e.g. to disable devices whose data or address lines share the same bus as the device under test). Rear Panel The IEC power connector, power ON/OFF switch, FOOT SWITCH socket, RS 232 connector and input protection fuses are mounted on the rear of the instrument. FOOT SWITCH socket Connect the Polar Foot Switch (ACC124) to the FOOT SWITCH socket on the PFL rear panel. Pressing the Foot Switch is equivalent to pressing the Test button on the Tool Bar or selecting the Test command from the Device menu. RS232 socket The RS232 socket is used to transfer PFL commands and data between the PFL and the host computer. Use only the supplied cable (ACC126). Ensure the host computer and the PFL are both powered down before connecting cables. Connect the cable between the host computer's serial port and the PFL RS232 socket.
Polar Fault Locator
General Description 13
Getting started with the Fault Locator
Live Instrument testing

Live Instrument screen The PFL Live Instrument screen allows the operator to test devices directly using ASA techniques use the Live Instrument screen to make the impedance signature. Press the Live button the Live Instrument screen is shown below.
Component signatures are displayed on the display window of the host computer's screen. The signatures of devices connected to Channel A are shown in green, Channel B signatures are shown in red. Test techniques for common devices and circuits are discussed in detail in ASA Device Testing. Using the PFL probes The PFL is supplied with a pair of DVM style probes and a clip-on common return lead, which are connected to the A, B and COM sockets respectively.
14 Getting started with the Fault Locator
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Connecting the test cables Connect the Red probe to the Channel A socket, the Black probe to the Channel B socket, and the black test clip to a COM socket. Connect the COM test clip to the ground of the board under test. If two boards are being compared, both grounds must be connected to the instrument's COM sockets. Connect the Channel A and B test probes to the ungrounded ends of the devices under test use Channel A as the reference channel; i.e. connect Channel A to the known good device. Double-click on the signature to fill the display window double-click again to return to the previous display size.
Defining test conditions

Test Range selection The Live Instrument screen provides for both manual and automatic selection of drive voltages and frequencies. This allows rapid selection of the most appropriate voltage and frequency range for a component or circuit under test. To specify test conditions manually, click the voltage and frequency buttons as appropriate, or Tab to the Range, Frequency or Pulser field and change the option setting with the left and right cursor keys. The two device signatures should appear on screen, the Channel A in green, the Channel B signature in red.
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Getting started with the Fault Locator 15
Selecting the Voltage range The PFL provides a range of current limited drive voltages. Only one drive voltage can be selected at a time:
Setting
Junction
Voltage Range
1V AC peak 500A current limit
Application
Use on semiconductor components and circuits, e.g. signal diodes, recommended for testing ICs. Safe for use on most circuits. Ideal for light emitting diodes. Low voltage and current reduce the possibility of over stressing components. Low resistance circuits and power diodes. Not suitable for low power components. Medium resistance circuits or components, Zener and other diodes with breakdown voltages up to 20V. Useful for checking diode leakage. High resistance components. Diodes with breakdown voltages in the 20V to 50V range, and diode leakage.
Logic
10V AC peak 5mA current limit
Low
Med
High
Use the mouse or left and right cursor keys to select the drive voltage to provide meaningful signatures (this will usually mean choosing the range which produces maximum deflection). By selecting the higher voltage ranges larger values of current flow and more recognisable sloping signatures are displayed. Lockout The Lockout option in the Range menu enables the user to prevent ranges from being selected manually or by Auto or Cycle
16 Getting started with the Fault Locator Polar Fault Locator
Selecting the Frequency range The signature produced by a pure resistance is an inclined straight line whose slope (gradient) is dependent on the value of resistance. For a purely resistive component the frequency selected will not significantly affect the appearance of the signatures.
By choosing a different test frequency to vary the impedance, the effect of resistance can be exaggerated or minimised as required.
Due to their energy storage characteristics, reactive components produce a phase shift between voltage and current flow. This is displayed as a circular or elliptical signature. For a pure reactance the major and minor axes of the ellipse align with the display axes. If the resistive component of a circuit is significant compared with the impedance of the reactive component, the elliptical signature will be tilted. In a capacitor more current flows at higher frequencies and produces a larger vertical excursion of the signature. In an inductor more current flows at lower frequencies. See ASA Device Testing for a discussion of semiconductor device signature shapes. The following table is included as a guide to frequency selection. Only one frequency can be selected at a time.
Setting
Low
Application
90Hz signal used to produce signatures of circuits with larger value inductors or capacitors; e.g. components in power supply circuits. 500Hz signal is used for most troubleshooting. 2kHz signal used to produce signatures of circuits with small value inductors or capacitors.
Med
High
Note: some "looping" of the displayed signature (due to stray capacitance) may occur even when the probes are not connected to the circuit under test, especially if High frequency is selected.
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Auto The Auto command automatically selects a range to produce a meaningful display. Channel A will be used to select the range. To stop Auto select a drive range, or select Cycle. Cycle Select Cycle to continuously cycle through each voltage range, displaying the signatures. Drag the Rate setting control to set the dwell time on each range. To stop cycling, select a drive range, or select Auto. Tolerance Drag the Tolerance control (from 1 99%) to change the sensitivity of the signature comparison as a percentage value. Lower values represent a more exacting comparison, higher values will allow greater differences in signatures; start with a value of 5% and adjust for a sensitivity which will allow normal component tolerances but capture faulty devices. Beep
Beep button use the Beep button for hands-off testing.
Click the Beep button to enable an audible warning when the deviation between two signatures under comparison exceeds the value set for Tolerance. This feature enables the operator to probe the devices under test without looking away from the circuit module.
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The PFL Pulse Generator The PFL incorporates pulse generating circuitry which allows the conduction state of transistors, SCRs, Triacs and other 3terminal devices to be controlled by adjusting the level, width, polarity and time delay of pulsed outputs. The Pulse Generator produces identical outputs between the two blue PULSE OUT sockets (which are connected internally in parallel) and the black COM sockets. Note that the PULSE OUT signals are driven individually, so that, although the same pulse output appears on both connectors, a load on one output does not affect the other.
Pulse Generator applications The Pulse Generator allows the operator to carry out a range of tests on a wide variety of three-terminal devices. The level of the pulser can be adjusted on the Live Instrument screen using either the mouse or the cursor keys. Drag the control left or right with the mouse or select it with the mouse or <Tab> key then use the cursor keys. Note: The pulser is turned off if Junction range is selected. See ASA Testing of semiconductors for a detailed discussion of three terminal device testing. Connect the Pulse Generator cables to the two blue, PULSE OUT sockets on the connector panel.
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The Pulser options are summarised in the table below:

Pulse Type
DC Pos
Function
Selects a + DC voltage output. The level is adjusted with the Level control. Selects a DC voltage output. The level is adjusted with the Level control. The P1 pulse starts at the zero crossover point of the AC drive voltage waveform. The pulse width is determined by the Width control and its amplitude by the Level control. Selects a positive going pulsed voltage output with a characteristic shown as Pulse1 Output. Selects a negative going pulsed voltage output with a characteristic shown as Pulse1 Output. Selects a pulsed voltage output of both polarities with a characteristic shown in Pulse1 Output. Pulse width is set by the Width control and amplitude by the Level control. The P2 pulse starts after the zero crossover point at a position in the AC test waveform determined by the Width control. The pulse ends at the next zero crossover point. Its amplitude is varied by the Level control. Selects a positive going pulsed voltage output with a characteristic shown as Pulse2 Output. Selects a negative going pulsed voltage output with a characteristic shown as Pulse2 Output. Selects a pulsed voltage output of both polarities with a characteristic shown in Pulse2 Output. The pulse width is determined by the Width control, the amplitude by the Level control. Adjusts pulse width up to a maximum of half a cycle. Adjusts DC or pulse level between 0V and 5V.
DC Neg
Pulse1
Pulse1 Pos
Pulse1 Neg
Pulse1 Bi Dir
Pulse2
Pulse2 Pos
Pulse2 Neg
Pulse2 Bi-Dir
Width
Level
Only one option DC, Pulse1 or Pulse2 can be selected at any one time.
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Bi-Dir
Pulse1 Output
Bi-Dir
Pulse2 Output
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Testing integrated circuits

All integrated circuits can be tested by probing pairs of terminals (e.g. comparing the signatures of corresponding pins on two boards). Most ICs tested in this way display signatures similar to diodes or Zener diodes. Note that ICs manufactured using different technologies can have distinctly different signatures. This must be considered before diagnosing a device as faulty. See ASA Device Testing for a discussion of IC testing the discussion includes examples of typical IC signatures. Note: The COM lead must be connected to a common point, usually 0V, on each board under test. It may also be useful to examine signatures using the Vcc pin as COM. If the signatures are unstable, connecting both Vcc and ground to COM may solve the problem.
Testing devices using Quicktest

The PFL Quicktest screen allows the operator to test devices and boards without compiling a test program. If known good boards are available the operator can employ comparison techniques to test devices. Quicktest can acquire reference signatures for a device from a known good board then compare the device under test against them. Comparison testing with Quicktest There are three ways to use the Quicktest comparison function:
Enter the device type (Library). Select the ASA button the instrument then automatically determines the number of pins on the device and executes an ASA test. Use Probe if the probes or a Polar SMD probe is being used.
The Quicktest comparison function Library option allows users to choose a device from the component library the library contains pre-defined test parameters for most devices in common use. The pre-defined parameters will be found suitable for most applications. Test parameters (voltage and frequency ranges, etc.) can be modified via the Advanced Edit command in the Device menu.
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ICT Links (PFL780 only) ICT Links checks for interconnected or stuck pins using the device's ICT driver. Where there is no ICT driver for a device the PFL executes an ASA Links test. ASA Links ASA Links identifies pins which are shorted to Common. Note: Only one Links test type may be selected. Comparison testing a device with Quicktest Press the Quicktest button the Quicktest screen is shown (for the PFL780) with the last device tested displayed in the tabbed device window.
In comparison testing Quicktest displays the prompt Clip Reference. Enter the device type in the device type box (type in the device type, e.g. 74LS244 or select the device from the library list). Place the test clip over a known good device and press the Test button or press the Foot Switch to acquire and save reference signatures.
Press the Test button on the Tool Bar to acquire and save signatures.
(If comments or special instructions (See Advanced Edit Notes tab) have been entered for this device, they will be displayed before the signatures are acquired; press OK to continue with test execution.)
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View screens can also be selected by double clicking the device graphic displayed in the associated tabbed window. To view all result screens you can display all open windows choose Tile from the Windows menu. Switch between open views via the Window menu.
The reference signatures can be viewed by switching to the view screens. Press the View ASA, View ICT or View Links buttons to open or choose a view screen. The prompt Clip DUT (device under test) is displayed. Place the test clips over the device under test and press the Test button the device under test is tested against the saved reference signatures.
A Pass or Fail result is displayed in the Results Bar and a green tick or red cross is displayed in the tab to indicate success or failure of the different section of the test. The reference and device under test signatures can be viewed by switching to the view screens. Pressing Test again will reacquire the signatures of the device under test and compare them with the reference. When a new device is to be tested pressing Erase Signatures deletes the signatures of the reference device and device under test. Viewing ASA results The ASA view screen shows a typical ASA result screen. Reference signatures are shown in green, signatures for the device under test are shown in red. The ASA results window shows the reference signatures and signatures for each pin of the device under test for all specified voltage ranges (Junction, Logic, Low, etc.).
ASA signatures for the device under test. Double clicking on a signature screen enables a Live display for the pin.
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You can switch to other voltage ranges by clicking the right mouse button to display the voltage range shortcut menu. Click the right mouse button to select View by Error
By default the ASA signatures are shown in descending order of error, i.e. signatures with the greatest percentage deviation from the reference are shown in the higher rows. Use the scroll arrows on the vertical scroll bar to view the signatures on the other device pins and voltage ranges. Choose View by Pin from the View menu to view the device in pin number order for each voltage range. Click the Maximise button to view the windows full screen.
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Viewing ICT results The ICT view screen shows the ICT Logic Diagram for the device under test. The Logic Diagram is a diagrammatic representation of the logical function of the device in circuit. The logic diagram shows the logic level of each pin at each tested step for the device, showing the relationship between control lines and signal inputs and outputs and providing a visual representation of the behaviour of each device pin.
ICT logic diagram The logic diagram shows the status of each pin at each tested step for the device. Use the up and down cursor keys to view the test waveforms on other pins of the device.
The PFL shows Reference data for the device in green. Logic levels are shown as High, Low, Tristate (shown as a dashed line between the High and Low levels) or Don't Care (shown as a hashed area). Faulty pins will be shown in red. Press the <Space bar> or choose Free Air from the View menu to view the logical functions of the device in "free air", (i.e. the ideal device in the database).
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Viewing Links The Links window shows the result of the Links test for the device.
The Links test:

displays pins that are stuck high and stuck low (i.e. at fixed logical high and low levels) compares connections between pins
Pins that are stuck high (e.g. Vcc) are shown connected to a positive supply rail. Pins that are stuck low (e.g. the GND pin) are shown connected to ground. Link lines matching the reference device are displayed in green. Unexpected links on the device under test will be shown in red, links missing from the device under test appear as gaps.
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Single board testing with Quicktest Auto compensation When a known good board is not available for comparison use the Auto option to execute an ICT test on devices on the board. When a device is connected in circuit its logical operation may be modified from its operation under "free air" conditions. For example, a dual-input NAND gate with both inputs shorted should behave as an inverter. The Auto option automatically compensates for such behaviour. When a device is tested using Auto the PFL780 identifies connected pins and hard-wired inputs on the device under test then builds a software simulation of the device. The device under test is then tested against the software model of the device in its circuit configuration. From the Single Board section select Auto. Clip the device, type the device type in the combo box (or select from the list of recently used devices) and click Test. The test results may be displayed as described earlier If the PFL is unable to autocompensate this device or circuit configuration Quicktest displays a message that the device is being tested against its free air model. If the device is to be tested removed from the circuit, ensure the Testing out of circuit box is checked. Searching for device types (PFL780 only) Use the Search function when a device type is not known (e.g. if the markings have been removed or faded). The PFL780 will search its ICT database for devices with matching behavioural patterns. Devices with matching functional patterns will be listed in the Search text area If the device is to be tested removed from the circuit, ensure the Testing out of circuit box is checked.
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Asa Device Testing
Signature shapes Using the Analog Signature Analysis method, the PFL applies safe, low power drive voltages to components to produce "impedance signatures" on the PC screen.
Normally, the fastest diagnosis is made by comparing two signatures. There is often no need to analyse the shape of the signature in detail.
Impedance signatures are graphs of current against voltage, plotted on a scale which has its origin at the centre of the display screen. Positive voltages and currents are displayed in the upper right quadrant on the display. Negative voltages and currents are displayed in the lower left quadrant (see the diagram below). All signatures are contained within the diamond shaped area formed by the "load lines" joining the ends of the marked axes.
Display X and Y Axis
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Asa Device Testing 29
The table below shows the peak voltage and current for each voltage range.
Range
Junction Logic Low Med High
Peak Voltage
1V 10V 10V 20V 50V PFL Drive Ranges
Peak Current
500A 5mA 150mA 1mA 1mA
Testing passive components with ASA

Testing Resistors The signature produced by a pure resistance is an inclined straight line whose slope (gradient) is dependent on the value of resistance. A high value of resistance will only pass a small current if a low test voltage is applied. The resulting signature may not be easily distinguishable from the open circuit horizontal trace. By selecting the High voltage range a larger current flows and a more recognisable sloping signature is displayed. The Resistance Ranges Table gives the ranges against approximate resistor values for which signatures can be distinguished from a short circuit (vertical trace) or an open circuit (horizontal trace).
Range
Junction Logic Low Med High Resistance Ranges
Resistor Value (Ohms)

1K to 50K 300R to 6K 16.5R to 300R 5K to 60K 12K to 150K
30 Asa Device Testing
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The diagrams below show typical signatures for three resistor values, 2k, 270k and 10K.
2K Resistor Logic Range Low Frequency.
270K Resistor High Range Low Frequency
10K Resistor High Range Low Frequency
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Testing Capacitors Due to their energy storage characteristics, reactive components produce a phase shift between voltage and current flow. This is displayed as a circular or elliptical signature. The diagrams below show typical signatures for three capacitors. For a pure reactance the major and minor axes of the ellipse align with the display axes. If the resistance in circuit is significant compared with the impedance of the reactive component, the elliptical signature is tilted.
22uF Capacitor Low Range Low Frequency
10uF Capacitor Low Range Low Frequency
82pF Capacitor High Range High Frequency
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The diagrams below show the signature of a defective 47uF capacitor which has gone resistive and how the signature of the same type of capacitor should appear for a good part. By choosing a different test frequency to vary the impedance, the effect of resistance can be exaggerated or minimised as required.
47uF Capacitor Low Range Low Frequency Faulty capacitor Resistive
47uF Capacitor Low Range Low Frequency Good component
The table below shows the ranges of capacitors covered by each combination of frequency and drive voltage.
Frequency
Range Logic Low Med High Capacitor Ranges Low 300nF 6uF 6uF 100uF 30nF 300nF 10nF 150nF Med 56nF 1uF 1uF 20uF 5nF 68nF 2nF 30nF High 15nF 300nF 300nF 5uF 1.5nF 15nF 500pF 7nF
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Testing Inductors The table below shows the ranges of inductors covered by each combination of frequency and drive voltage.
Frequency
Range Logic Low Med High Low 500mH 11H 30mH 500mH 10H 110H 20H 300H Med 100mH 2H 6mH 100mH 2H 10H 4H 50H High 25mH 500mH 1.5mH 25mH 500mH 5H 1H 12H
The diagram below shows the signature of a ferrite transformer primary winding with the test voltage range set Low and test frequency set High. This demonstrates the effect of a significant value of resistance causing the inductive ellipse to be tilted.
Ferrite transformer Primary winding Low Range High Frequency
The diagram below shows a similar (defective) transformer with a shorted turn. The operator can select the most suitable test frequency Low, Med or High (see Advanced Edit). In a capacitor more current flows at higher frequencies and produces a larger vertical excursion of the signature. In an inductor more current flows at lower frequencies.
Ferrite Transformer Primary winding Low Range High Frequency Shorted turn
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ASA testing of semiconductors
Testing diodes, LEDs and Zeners When forward biased, a diode exhibits a low resistance and a voltage drop of approximately 0.6V. This produces a signature that is an almost vertical trace close to the Y axis see the diagram below.
Signal diode Logic Range Low Frequency
When reverse biased, the high resistance characteristics of the diode approaches that of an open circuit, producing a horizontal trace close to the X axis. A light emitting diode (LED) shows a similar signature to a conventional diode, except that the forward voltage drop is approximately 1.5V. A Zener diode exhibits the same signature as a conventional diode for voltages below the Zener voltage. When the reverse bias exceeds the Zener voltage, a low resistance signature is displayed. The diagram below shows the signature of an 8.2V Zener diode.
8.2V Zener diode Med Range Low Frequency
When testing Zener diodes the graduations on the display X axis can be used to measure the Zener voltage (see the table for PFL Drive Ranges). Use the voltages ranges below:
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Power diodes Signal diode and LED Zener diode High above 20V
Low Logic Med up to 20V
NOTE: The signatures are inverted if the test probe and COM connections are reversed. Testing Transistors A transistor contains two semiconductor junctions connected "back-to-back" (one between base and collector, the other between base and emitter). The following diagrams show typical signatures for an NPN transistor (base-emitter, basecollector and emitter collector) in which the collector and emitter are N-type material and the base P-type.
NPN Transistor base-emitter Med Range Low Frequency
NPN Transistor base-collector Med Range Low Frequency
36 ASA testing of semiconductors
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NPN Transistor emitter-collector Med Range Low Frequency
The base-emitter signature is similar to that for a Zener diode. High-frequency small signal transistors should not be operated in this mode for long periods. Prolonged reversebreakdown of the base-emitter junction may permanently affect the characteristics of the device. See Three Terminal Testing for a method that does not reverse-bias the transistor base-emitter junction. The base-collector signature is similar to that of a conventional diode. The collector-emitter signature is similar to that of a diode in series with a Zener diode. When the drive voltage is positive (right quadrant) the collector-base is reverse biased and the base-emitter forward biased. The reverse biased collectoremitter prevents current flow, producing an open-circuit signature (a horizontal line). When the drive voltage is negative (left quadrant), the collector-base is forward biased and the base-emitter reverse biased. The base-emitter exhibits Zener breakdown as described above, producing a Zener "tail" signature. See the warning above about operation of the transistor with the base-emitter reverse biased. The signatures for a PNP transistor will be mirror images of those for an NPN transistor. Identifying Transistor Terminals The terminals of an unknown transistor may be identified as follows: Select Logic Range, Low Frequency. Connect the COM clip to one lead of the transistor and probe the other two leads in turn, looking for a match with the signatures shown for NPN transistors (see Testing Transistors). If the signatures are mirror images of the figures, the transistor is a PNP device.
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ASA testing of semiconductors 37
Three Terminal Testing of Transistors A functional test may be carried out by driving the transistor base to verify that this controls conduction between the collector and emitter. The following procedure applies to an NPN transistor. The meaningful part of the signature appears in the upper right quadrant of the display; ignore the lower left quadrant. Except where noted, the procedure for a PNP transistor is identical but displays will be mirror-images (i.e. the meaningful signature will appear in the lower left quadrant):
Connect the collector to Channel A, the emitter to COM and the base to one of the Pulse outputs. Select Logic Range, Low Frequency, DC Pos (for NPN) or DC Neg (for PNP). Set Level to 0. The signature in the right quadrant is a horizontal line, indicating no conduction. As Level is increased, the base-emitter will become forward biased and the transistor will begin to conduct, producing a signature as shown below. This signature is similar to that seen using a conventional curve-tracer except that only a single curve is shown. Increasing Level further will saturate the transistor, producing an almost vertical line close to the Y-axis.
NPN Transistor Low Range Low Frequency collector-emitter DC Neg to base
Since the transistor is being operated as a switch, when it starts to conduct the signature may look more like that shown below (which is inverted because it is for a PNP transistor). This does not indicate a fault, but shows the device switching between normal conduction and saturation. A more stable display may be obtainable by selecting a different voltage range.
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PNP Transistor Logic Range Med Frequency collector-emitter Pulse1 Neg to base
Selecting the Pulse1 Pos output from the Pulse Generator enables both the conducting and non-conducting signatures to be displayed. Leaving Level unchanged from the previous step, rotate the Width control to vary the pulse period. When the pulse is high, the baseemitter is forward-biased and the transistor will conduct. When it is low, the transistor will not conduct, producing an open circuit signature.
Testing Junction Field Effect Transistors (JFETs) The junction field effect transistor (JFET) consists of a bar of semiconductor material (the "channel") and a region doped with material of the opposite semiconductor type to the channel (the "gate"). The gate forms a diode junction with each end of the channel (the "source" and "drain") and these may be tested as conventional diodes. The signature between source and drain (see Three Terminal Testing of Junction FETs) shows a low value, non linear resistance. To obtain a stable display it is usually necessary to connect the gate to the source. An open circuit gate terminal is extremely sensitive to interference from the test signal.
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Three Terminal Testing of Junction FETs The conduction between the source and drain of a JFET is controlled by reverse biasing the gate-source junction. The following procedure applies to an N channel FET.
The meaningful part of the signature appears in the right quadrant of the display; ignore the left quadrant. Except where noted, the procedure for a P channel FET is identical and displays will be mirror-images (i.e. the meaningful signature will appear in the left quadrant): Connect the drain to Channel A, source to COM, and the gate to one of the Pulse outputs. Select Logic range, Low frequency, DC Pos (for P channel) or DC Neg (for N channel). Set Level to 0.
When Level is zero, the drain-source signature will be similar to that shown below. As Level is increased (increasing the reverse bias of the gate-source junction), conduction in the channel is reduced. As Level is further increased, all conduction will cease and the signature in the right quadrant will be a horizontal line.
Junction FET Logic Range Low Frequency drain-source DC Pos to gate
Testing MOSFETS
CAUTION: Observe static precautions whenever handling MOSFETs. Use Logic range for testing (or Low for power MOSFETs). Do not use Med or High ranges. MOSFETs are field effect transistors in which the gate is insulated from the channel. The gate-drain and gate-source tests will usually produce an open-circuit signature, although some MOSFETs have a protection diode between the gate and source. In these cases the gate-source signature will be that for a Zener diode. As in a JFET, source-drain conduction is controlled by the gate-source voltage. However, MOSFETs are available that
40 ASA testing of semiconductors Polar Fault Locator
operate in either "enhancement" or "depletion" mode, where conduction is controlled by forward/reverse bias of the gatesource junction respectively. Three Terminal Testing of MOSFETs
Follow this procedure for an N channel, enhancement mode MOSFET. The meaningful part of the signature appears in the right quadrant of the display; ignore the lower left quadrant. Except where noted, the procedure for a P channel FET is identical and the displays will be mirror-images (the meaningful signature will appear in the left quadrant): Connect the drain to Channel A, source to COM, and the gate to one of the Pulse Generator Outputs. Select Logic range, Low frequency, DC Pos (see note below). Set Level to 0. Note: To determine the polarity required for the gate drive, note that the junction is forward biased for enhancement mode FETs and reverse biased for depletion mode. Thus N channel enhancement mode and P channel depletion mode FETs require positive gate voltage, N channel depletion and P channel enhancement mode FETs require negative gate voltage. When Level is zero, the drain-source signature will be a horizontal line indicating no conduction. As Level is increased (increasing the forward bias of the gatesource junction) conduction in the channel is increased, producing a signature as for the JFET. As Level is further increased, conduction will increase until the signature approaches that of a very low resistance (an almost vertical line).
Testing special devices

Testing Opto-Isolators An opto-isolator consists of an input LED and an electrically isolated output transistor (with base unconnected). The input diode can be checked like a conventional diode. The signature of the output transistor (i.e. its collector-emitter characteristic) will be either a horizontal line (open-circuit) or similar to that of an emitter-collector junction. Three Terminal Testing of Opto-Isolators
The conduction of the output transistor is controlled by light emitted by the input LED. This stimulates the creation of charge carriers in the transistor, causing it to conduct.
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The opto-isolator operation may be tested by driving the input LED using the Pulse Generator, and displaying the signature of the output transistor. Connect the output transistor collector to Channel A and emitter to COM. Connect the input LED anode to one of the Pulse outputs, and the cathode to COM. Select Logic range, Low frequency, Pulse1 Pos. Set Level to 0. The signature in the right quadrant is a horizontal line, indicating no conduction . As the Level is increased, the LED will be forward biased. Light emitting from the LED will stimulate conduction in the output transistor, producing a signature as shown below. Further increasing Level will saturate the output transistor, producing an almost vertical line in the right quadrant close to the Y-axis.
Opto isolator Logic Range Low Frequency DC Pos Output transistor collector-emitter
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Testing four-terminal devices Testing SCRs An SCR can be regarded as a diode with an additional control terminal (the "gate").
Connect the anode to Channel A, cathode to COM and the gate to one of the Pulse outputs. Select Low range, Low frequency, DC Pos. Set Level to 0. The signature produced is a horizontal line, indicating no conduction. As Level is increased, gate current flows. When this reaches a sufficient value, the SCR "triggers" i.e. conducts, producing a signature similar to that for a conventional diode Selecting the Pulse2 Pos pulse output enables both conducting and non-conducting operation to be displayed. Leaving Level unchanged from the previous step, rotate the Width control to vary the pulse period. When the pulse is high, the SCR conducts. When it is low, the SCR is switched off. The signature is shown below. The horizontal line corresponds to the time the pulse is low, and the vertical line to the time the pulse is high.
SCR Signature
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Testing Triacs A Triac is similar to an SCR, except that it conducts in both directions, and can be triggered by either positive or negative gate current.
Connect the MT2 terminal to Channel A, MT1 to COM and the gate to one of the Pulse outputs. Select Low range, Low frequency, DC Pos. Set Level to 0. The signature is a horizontal line, indicating no conduction. As the Level is increased, gate current flows. When this reaches a sufficient value the Triac "triggers" i.e. conducts, producing a signature similar to that for a conventional diode. Further increasing Level causes the Triac to conduct in both directions, producing the signature shown below. Triac Low Range Low Frequency DC Pos MT2 MT1
Return Level to zero, then select negative Pulse polarity. Repeat step 3 to produce similar signatures. Selecting the Pulse2 pulse output enables both the conducting and non-conducting operation to be displayed. Leaving Level unchanged from the previous step, rotate the Width control to vary the pulse period. When the pulse polarity is positive, the resultant signature is the same as for the SCR. When the polarity is negative, the display is a mirror image of that for an SCR.
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Selecting Pulse2 Bi-Dir results in conduction in both directions, and produces the signature shown below.
Triac Signature
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Testing integrated circuits using ASA
Integrated Circuits The Logic and Junction ranges and Low frequency are recommended for use when testing ICs. All integrated circuits can be tested by probing pairs of terminals. Most ICs tested in this way display signatures similar to diodes or Zener diodes. Note: ICs manufactured using different technologies can have distinctly different signatures. This must be considered before diagnosing a device as faulty. When testing an IC it is usually appropriate to connect COM to the ground pin of the IC. Alternatively COM can be connected to Vcc. IMPORTANT: In some circumstances unstable signatures can occur (especially in sensitive ranges like Junction). Connecting both ground and Vcc pins to COM can overcome this effect. TTL signatures The Signatures below show signatures for a 74LS00 IC.
74LS00 Logic Range Low Frequency Input to ground
The signature above is dominated by the input protection diode with its anode connected to the COM probe via circuit ground.
46 Testing integrated circuits using ASA
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74LS00 Logic Range Low Frequency Vcc to ground
The signature above shows the effect of a network of components within the IC.
74LS00 Logic Range Low Frequency Output to ground
The signature above is more complex as several output components within the IC influence the trace. The corresponding signatures for an HC gate (74HC02) are shown below.
74HC02 Logic Range Low Frequency Vcc to ground
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Testing integrated circuits using ASA 47
74HC02 Logic Range Low Frequency Input to ground
74HC02 Logic Range Low Frequency Output to ground
4000 series CMOS Devices The corresponding signatures for 4000 series CMOS (4017) are shown below In the lower diagram looping occurs due to capacitance within the IC. Using Med or High frequency will exaggerate this effect. In general Low frequency should be used when testing ICs.
4017 Logic Range Low Frequency Input to ground
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4017 Logic Range Low Frequency Output to ground
4017 Logic Range Low Frequency Vcc to ground
Testing Devices in Circuit When testing a component in circuit, the signature is a composite of that device and other components in parallel. This is most often the case when diagnosing faults in service. The characteristic signature at any probing point in a circuit is unique for that circuit. Using channels A and B to display the signatures of a suspect circuit and that of a good circuit is the best way to identify a fault. A faulty component may affect the signatures of several connected components. The operator can 'home-in' on a fault by probing at several points in the circuit.
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Testing integrated circuits using ASA 49
Bus-connected devices When a number of devices are connected together on a common bus, the signatures on the bus lines may be compared to look for differences. Lines on the same bus will usually have similar signatures (e.g. all data lines will be similar to each other). If one line has a different signature from other lines on the same bus, this suggests that a device on that bus is faulty. Testing bus-connected devices
To isolate the fault to a specific device there are a number of methods: If any devices are socketed, remove them one by one until the defective line's signature matches the other lines. Each device will have one or more pins that are not connected to a bus, e.g. /CE (Chip Enable) or /OE (Output Enable). This provides a method for looking at the ICs individually. Instead of connecting the PFL's COM input to Vcc or ground, connect it to the defective bus line. Probe each of the devices' /OE or /CE pins, looking for a device whose signature differs from other similar devices. If neither of the above methods locate the fault, it may be necessary to unsolder devices until the fault is cleared. The diagram below shows the signature of a data bus line of a microprocessor in circuit.
Microprocessor data bus in circuit
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ICT device testing
PFL780 In Circuit Functional Test

The In Circuit Functional Test (ICT) facility of the PFL780 is highly effective in locating faulty digital integrated circuits. The technique may also be used to examine the signatures and verify the logical functions of digital integrated circuits. The PFL780 incorporates a database consisting of a wide range of digital device models against which suspect devices may be compared. The PFL780 allows users to perform both single and repetitive ICT tests on all devices modelled in the PFL780 database. When a device type is not known the PFL780 can test the device for a match within its database and print a list of all equivalent device numbers. The PFL780 integrated programming environment allows the operator to create test programs with both fault finding techniques, ASA and ICT, combined into a single test program.
Device testing with ICT

The ICT technique of device checking is a popular and widely established method of testing and repairing printed circuit boards containing digital integrated circuits. ICT is a method of device testing which carries out a functional test of the logic device. ICT verifies that digital integrated circuits perform their associated logical functions in accordance with their design parameters. During an ICT test the PFL780 drives the inputs of a digital device and monitors the device outputs for correct response. A wide range of logic elements can be tested using ICT (for example, using ICT the PFL780 can easily check that a logic gate operates in accordance with its truth table or that a counter or shift register correctly responds to a known number of clocks).
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ICT device testing 51
ICT allows even very complex devices to be tested the PFL780 can, for instance, test a large memory device such as a VLSI RAM (by writing to each location and checking that the correct word is read back). ICT can also be used to check that programmable devices such as ROMs or EPROMs have been properly programmed or that programmable interface devices respond correctly to control words Using ICT the PFL780 stores the response of a device in a good circuit and uses the stored response to test the corresponding device in a suspect board. Test results may be shown as a simple PASS/FAIL result or displayed as pin connection and logic diagrams, allowing the more obscure faults to be quickly pinpointed. In many cases the operator simply needs to locate the device test clip over the digital device to be tested and specify the device type (if known) to perform a test. In an ICT test the PFL780 automatically applies power to the device for the duration of the test and compares the logical function of the device under test with the corresponding ideal device in the PFL780 Device Library. Each device program in the library includes a sequence of test patterns that will initialise the device, drive the input pins of the device and check for appropriate responses on the device output pins. During testing the logical operation of the device (i.e. the relationship between inputs, clocks, control signals and outputs) can be viewed in diagrammatic form and compared with the ideal device in the database. Differences between the device under test and the component in the database are shown in red for easy identification. Testing devices in circuit In some cases, when testing devices soldered into a circuit the device will behave as the free air model and the operator simply locates the test clip over the device and specifies the device type. Generally, however, the operator first uses the PFL780 to acquire signatures for the device in a good circuit. During the reference acquisition process the behaviour patterns of the device in a good circuit are compared with the standard device responses and the differences recorded. The acquired signatures are then used as a reference when testing suspect boards. Device responses on the board under test are thus compared to the reference signatures. To accommodate variations in the signature shapes of devices from different vendors the PFL allows the user to
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store sets of signatures under vendor names. Device signatures are then compared with several reference signature sets. Backdriving To fully verify a digital device, a test program must check the responses of the device under all possible input conditions. The PFL780 test system therefore incorporates circuitry which is able to source and sink sufficient current to override the logic level of any pin on a device in circuit and force the pin into a known state, regardless of the logical state of preceding gates this requires a technique often referred to as backdriving. Backdriving is the primary technique behind digital in-circuit testing. In order to perform a full logical test on a digital integrated circuit, it is necessary to drive the inputs of the device to all possible states. Driving the inputs of a device frequently means backdriving the outputs (sourcing or sinking the output currents) of other devices connected to the device under test. The circuit below illustrates a typical circuit configuration the PFL780 drives the inputs of U1 and tests the output for the correct response (as shown in the accompanying truth table). The PFL780 must source or sink sufficient current to override the logic levels on U2s outputs and drive the inputs of U1 with every possible input combination.
Drive these lines
Test this one

Backdriving gates preceding the device under test
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The PFL780 is able to source or sink currents up to 500mA through the test clip in order to force the input of an integrated circuit into a defined state. The backdriving current forces the outputs of preceding gates into a logic high or low, regardless of their quiescent state. In order to limit the power applied to the gates preceding the device under test the PFL780 completes the entire device test within 16mS. This conforms to all internationally recognised backdriving specifications.
The PFL780 Device Library

The PFL780 software includes a comprehensive database of integrated circuits in general use throughout the electronics industry. The library consists of functional and pin assignments for most digital devices in common use:
TTL devices 74 and 75 series 4000 series CMOS devices microprocessors and microcontrollers microprocessor interfacing devices memory devices programmable logic devices
ICT testing of digital ICs

Caution: During ICT testing it is essential that the instrument is not connected to any nodes that are outside the range 0 to +5V, other-wise damage is likely to occur to the ICT driver/sensor networks. Before testing devices, check for good connection between the test clips and the device under test if necessary clean the device of dirt, flux residue, corrosion, etc. Connect the test clip over the device to be tested ensure that the brown connection of the ribbon cable is connected to pin 1 of the device. Alternatively, for out of circuit testing use the ZIF test fixture ACC145.
The Power On ICT test

In-circuit device signature acquisition and testing are performed with power applied to the circuit and comprise two test components the Links Test and the Logical Function Test.
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The PFL780 first performs a Links Test, checking the status of device pins, i.e. testing for pins which are stuck high or low and checking for links between pins. The PFL780 then stimulates the inputs of the device and monitors the device outputs to verify the logical functions of the device. Links Test During the Links Test the PFL780 checks the status of device pins. The PFL780 notes the pins that are permanently at logical high or low (e.g. power supply lines and grounds and pins which are stuck high or low). The PFL780 also records interconnecting lines between pins. The results of the Links Test are displayed in the Links Window. The diagram displays the number and status of each pin with its associated signal function, stuck pins (Vcc and ground pins are normally shown as stuck high and low respectively) and connections between pins. Functional Test The second test consists of the device Functional Test. During the Functional Test the PFL780 checks that the device correctly performs its logical functions. The PFL780 recalls the test program for the device from the device library, drives all device inputs and monitors the response on the device outputs. The results of the Functional Test are displayed in the ICT window as a logic diagram. Controlling test conditions When digital integrated circuits are to be tested in circuit it will be necessary to ensure that device operating conditions are predictable and repeatable: Devices under test must be capable of being initialised, i.e. placed in a known state It must be possible to prevent other circuit components from affecting the result of the test, i.e. the device must be effectively isolated Other signals (e.g. clock signals) must be prevented from affecting the result of the test Note: When using ICT to test a device in circuit, the length of cable should be kept to a minimum, and adapters that allow multiple test leads to be connected in parallel (e.g. ACC137) should not be used. See the Applications Hints.
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The Logic Diagram The logic diagram graphically displays the logic level of every device pin at each "tested" step in the device's test program. The stimulating signals on the device inputs and the resulting logic levels on the device outputs are shown for every step in the device test program. Levels are shown as High, Low, Tristate (a dotted line midway between High and Low levels) or Don't Care (the cross-hatched areas). The reference (learnt) waveforms are shown as greencoloured lines on the PFL780 display. Pins behaving correctly are displayed in green pins displaying errors are shown in red for easy identification. Device pin numbers are shown on the left of the Logic Diagram. Device tests are shown along the top of the diagram if the device test incorporates a large number of test points use the left and right cursor keys to scroll through program tests. Press <Esc> to return to the Main screen. Use the mouse to scroll down the ICT window to view the test waveforms on other pins of the device. Logic levels in the Logic Diagram Logic levels in the Logic Diagram are shown as LOW (0V) and HIGH (+5V). The cross-hatched area represents the Dont care state; the horizontal dotted lines shown at the 2.5V level indicate the tristate (open circuit) output level. Note: The 2.5V mid-level can appear on both inputs and outputs. A mid-level on a device output may be correct if the output is meant to be open circuit (tristate). A mid-level input probably indicates a problem with the device or with testing.
Acquiring device signatures

When testing devices under free air conditions, the PFL780 recalls the device program from the PFL780 Device Library and compares the behaviour of the device with the expected behaviour pattern in the Library. With devices soldered into a circuit the operator first uses the PFL780 to acquire reference signatures for the device when driven and loaded in a good circuit.
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During the reference acquisition process the behaviour patterns of the device on the board under test are compared with the standard device responses and the differences stored. In this way devices can still be successfully tested, even with unconnected pins, pins wired to adjoining pins or adjacent devices, pins grounded or tied high, etc. The stored signatures are then used during device testing for reference when testing suspect boards. Device responses on suspect boards are compared to the stored device behaviour pattern a successful match results in a PASS. The PFL780 thus makes it possible to learn and test even programmable devices such as EPROMs and PALs in their final configuration. Devices are learnt as part of the Program process. Preventing instability problems Use the supplied cables to supply power from the PFL780 to the board under test using thin cables to supply power may result in voltage drop along the cable (particularly if heavy currents are drawn) and may cause instability or unreliable results. Keeping cable runs as short as possible will also help prevent instability. On some circuit boards, narrow power supply tracks may cause stability problems. If device stability proves difficult, try injecting supply voltages close to the device under test. See Applications Hints at the end of this section. Once the device has acquired reference signatures its number and reference are shown in bold in the device list.
Testing the device

As the device is tested the PFL780 displays the outcome of the test as a PASS/FAIL result, along with a pin assignment diagram showing all stuck pins and expected and unexpected links and a logic state diagram indicating the device pin states at each test point in the program. The PFL780 recalls the learnt test program and runs the test. The results of the test, PASS or FAIL, are displayed along with the ICT Test Results, i.e. the results of the Connectivity Test and the number of pins which passed or failed the Functional tests. Links diagram The Links diagram displays the number of each pin with its associated signal function label (e.g. CLK, VCC, GND, etc.) stuck pins and connected pins.
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Three types of links are detected and displayed in the ICT window: Confirmed links Confirmed links refer to pins which are connected on both the reference board and the board under test (the Reference device and the Acquired device) and are shown in green. Missing links Missing links refer to pins which were connected on the reference board but are not connected on the board under test. Missing links are shown as gaps on the Acquired device. Unexpected links Unexpected links refer to pins that are connected on the board under test which were not connected on the reference board. Unexpected links are shown in red. Stuck pins Signal lines that remained at a fixed logic level during the test are shown as stuck pins as described below: Confirmed stuck pins Confirmed stuck pins refer to pins which are stuck high or low on both the reference board and the board under test and are shown on both Reference and Acquired devices in green connected to Vcc or ground. Missing stuck pins Missing stuck pins refer to pins which were stuck high or low on the reference board but are not stuck high or low on the board under test. Missing stuck pins are shown on the Reference device but are omitted from the Acquired device. Unexpected stuck pins Unexpected stuck pins refer to pins that are stuck high or low on the board under test which were not stuck high or low on the reference board.
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Application hints
If an obscure fault shows up on one IC, check other ICs as well the fault may be easier to find on another chip. Using Loop until Pass when ICT results are unstable In some circuit configurations it may not be possible to fully guard a device from the effects of its connection to the other devices on the board. In this situation the use of Loop until Pass is recommended. Initialising devices In order to perform a reliable test on a device the system must be able to initialise the device, i.e. put the device into a known state. If a device cannot be initialised test results may be unpredictable: If, for example, the RESET lines of a counter have been hard wired the PFL780 will be unable to correctly initialise the counter. Some microprocessors contain internal free-running clocks which cannot be inhibited
Isolating devices in circuit

Bus-connected (tristate) devices In many circuits (e.g. microprocessor-based systems) devices transfer data or control signals over common buses (groups of address, data or control lines). Usually, the microprocessor determines which devices are sending and which devices are receiving by driving the address and control lines. In a bus system, the set of connecting lines is accessible to all devices on the bus. Bus circuits are therefore designed so that, at any time, only one device is allowed to place data on the bus. All devices on a bus system which are able to place data on to the bus therefore require the ability to assume an "open" state in addition to the normal high and low logic levels. So devices on a bus system incorporate the facility to set their outputs into an open circuit state as well as the normal high and low logic states. These tristate devices utilise an enable input which controls whether the device behaves as a normal logic device or appears as an open circuit to the bus.
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The enable input is often connected (sometimes indirectly) to one of the control lines of the microprocessor. The enabling signal is usually active low, i.e. a logic low level on the enable input enables the device outputs to assume a logic high or low state. Hint: Removing the CPU from a processor system may allow device enable pins to float to logical high, effectively isolating those devices from each other and preventing bus conflicts. When a bus connected device is disabled, the device outputs present an open circuit to the bus so the device is effectively disconnected from the bus selective device disabling will allow only the device under test to drive the bus. Disabling bus buffers In a typical microprocessor-based system the bus output connections of the microprocessor are only capable of supplying small amounts of current. This means that the processor can only directly drive a small number of devices before its outputs become too heavily loaded. Designers therefore normally isolate the processor from the rest of the system with buffers. Buffers accept input from the processor and can supply the high currents necessary to drive the capacitance associated with circuit board wiring and large numbers of devices. Hint: Disabling the buffer devices can often prove an effective means of isolating devices on the bus. Applying Guard voltages It will, however, in many situations be impossible to remove or disable devices. The PFL780 therefore makes logical high and low guard voltages (+5V and 0V) available at its front panel to enable users to disable components in the vicinity of the device under test. The device may then be tested in isolation without removal from circuit. If it is not practicable, for example, to remove the CPU or disable the bus buffers it may be possible to disable busconnected devices by applying guard voltages to the RESET, HOLD, or DMA Request (or equivalent) lines on the CPU. Many device types employ an active low CHIP ENABLE or OUTPUT ENABLE lines applying a logical high to this line places the outputs into a high impedance condition, effectively rendering the outputs open circuit.
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If many devices share the bus it may be necessary to apply guard voltages to several devices to ensure effective isolation of the device under test. When testing a bus-connected device, therefore, effective device isolation may be achieved by applying guard voltages to the enable inputs of all other connected devices on the bus (forcing the outputs into their open circuit state). When applying guard voltages to devices on undocumented boards some experimentation may be necessary before stable results are achieved. Note that the guard voltage outputs are able to backdrive and remain at logical high or low for the duration of the test. In the diagram below the device under test is U2, the guard voltage is applied to the CHIP ENABLE input of U1. The outputs of U1 are effectively open circuit.
Isolating a device using guard voltages
Disabling memory devices Memory devices (RAM or ROM) can be disabled by applying guard voltages to the Chip Enable signal lines in address decoding circuits (sometimes whole blocks can be disabled via a single line). The PFL780 applies guard voltages to selected devices during testing to disable the device outputs and prevent bus contention. Bus contention occurs when more than one device attempts to place data on the bus at a given time. When applying guard voltages to a circuit ensure that guard voltages are not connected (even indirectly) to the pin connections of the device under test.
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Disabling clocks Clocks and oscillators producing signals which could appear at the inputs of a device under test must be stopped or disabled during the test. A changing signal on an input pin of a device under test may interfere with the results of a test. Clock signals are often passed through flip-flops, which serve either as clock frequency dividers or provide signal shaping or buffering. It will often be possible to prevent the clock signal passing through the flip-flop by applying a high or low guard voltage as appropriate to the gating (clock enable) inputs or SET or RESET lines. If possible, disable all clocks and oscillators on the board. Hint: In a processor system removing the CPU will disable many clocking signals as well as disabling devices. A common use of guard voltages is shown in Figure 5-13. The circuit in Figure 5-13 is typical of many microprocessor clock generating circuits. Applying LOW guard voltages across the crystal will disable the oscillator circuit, and therefore the microprocessor.
Using guard voltages to disable a typical microprocessor clock circuit
Note: Use the supplied cables to supply power from the PFL780 to the board under test using thin cables to supply power may result in voltage drop along the cable (particularly if heavy currents are drawn) and may cause instability or unreliable results. Keeping cable runs as short as possible will also help prevent instability. On some circuit boards, narrow power supply tracks may cause stability problems. If device stability proves difficult, try injecting supply voltages close to the device under test.
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Pre-Charge function The Pre-Charge function controls the delay prior to each tested step during the ICT test. The default setting is 0S and will be found suitable for most applications. Hint: The delay can be altered, if necessary, to allow for propagation delay, and to improve stability in some high speed circuits. Some experimentation may be necessary before the optimum value is found. Note that ICT test time is guaranteed to be less than 16mS only when the Pre Charge is set to 0S.
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Writing test programs
The Program window

When the PFL program is started the PFL displays the Quickstart dialog box from which the user can choose to learn a new board, test an existing board (from the displayed list) or select Live Instrument or Quicktest. (The Quickstart dialog box may be disabled via the Config-Prompts screen in which case the PFL recalls the most recently used program or an empty program named Untitled if no programs have been created).
Copying existing test programs can prove an effective method of rapidly creating new programs which are based on, or similar to, existing test programs.
The PFL program window provides a graphical environment in which to create new programs, or modify and delete existing programs to test a wide variety of circuit components. The Board Layout view is provided to allow the programer to associate devices in the test list with a physical location on a bitmapped image of the board under test. In most cases the programmer simply needs to select devices from a comprehensive database of components the PFL however allows the programmer a high degree of control over test types and parameters. Good device signatures may be stored for reference and viewed and the signatures of devices under test may be sorted and viewed in device pin order or in descending order of error. In addition, sets of signatures for devices from different vendors can be stored as reference under the vendor name. This will eliminate spurious device failures caused by slight variations in signatures in good devices from different manufacturers.
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Writing test programs 65
Backing up test programs Test programs are stored as .PFL files in the Program Files\Polar\Pfl folder. Users can create additional sub folders in which to group related programs. Programmers are strongly recommended to back up test programs to tape or diskette on a regular basis. Working with Test Programs A test program consists of a list of devices and associated test conditions, each program usually consisting of the devices located on one circuit module (e.g., circuit board, sub-assembly, etc.). Programmers will often find it convenient to limit the number of devices in a test program to keep it to a manageable size. Loading a test program To load an existing program, From the File menu choose Open or click the Open button the Open dialog box opens at the current list of programs in the program folder. Highlight the program name or type the name in the File name box and press the Open button or press <Enter>.
Creating a new test program

From the File menu select New the PFL opens a new Test List window. The device list screen is comprised of two sections: The Test List The Results Window with ASA, ICT, ASALinks or ICTLinks tabs (not all devices have all three tabs shown; some devices, for example are tested using ASA only). Adding a board layout bitmap The PFL allows the programmer to include a bitmapped image of the board under test in the program test file. The image is stored as part of the test file and provides a graphical means of selecting devices for testing. The PFL requires that the graphic must be in bitmap (.bmp) format; the color depth of the image must be 8-bit (256 colors) or greater. (The color depth of an image, sometimes known as the pixel depth, defines the amount of color information available to each pixel in the image. As the color depth increases, more colors are available. An image with a color depth of 8-bits can display 256 colors, 16-bit depth allows 64K colors and so on.)
66 Writing test programs
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If a suitable image of the board is available: From the View menu select Board Layout View. Choose Set Board Image from the Board menu. Navigate to the folder containing the board graphic Choose the graphic file and press Open. The graphic is displayed in the Board Layout window. Adding devices to the test list Devices can be added at any point in the list Insert adds a device before the highlighted device. Inserting a device From the Device menu choose Insert (or use the <Insert> key) the Insert Device dialog box is displayed:
Enter the device type in the Type field if the device is not recognized by the system the user will be prompted to enter its details; the PFL displays the Enter Device Info dialog box.
If the Quad Flat Pack (QFP) package type is selected specify the device pinning via the Width, Height and Pin One fields
Enter the device description package type and pin count and press OK. If the device is likely to be used more than once use DevLib to add it to the device library. Type the circuit reference (if required) in the Ref: field.
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If the PFL identifies more than one possibility for the entered type it displays a list of alternatives to select from. In the Using: field specify how the device is to be tested in most cases the DIP test clips will be used so the default value of Library will be the correct setting. In some situations the device will be inaccessible or in a nonstandard package and it will be necessary to use a different probe type click the List Box arrow and choose the probe type from the list as appropriate. Click the Notes button to add instructions or explanatory notes for the user the Notes will be displayed whenever device signatures are acquired. Press OK the device will be added to the test list. The test types ASA, ICT and ASA or ICT Links are shown against each device in the device list. A small warning triangle is displayed against new devices to indicate that no reference signatures have yet been acquired for the device. Associating a device with the board image Once the device has been included in the test list, it can be linked to its corresponding location on the board image. Choose the device in the test list, then switch to Board Layout view.
Beginning at one corner of the device, drag the mouse to trace a rectangle over the associated device. For a new program, a bold white rectangle appears round the device. (Note: If you are adding a board image to an existing program, the rectangle colors will reflect the test results for each device green for a PASS result, red for a device FAIL.) Repeat the process until all the devices in the test list have been associated with their locations on the board image. Use the up and down arrow keys to step through the test list in Board Layout view.
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Acquiring reference signatures Use the Test function to acquire reference signatures for all pins of the device. The sequence for acquiring the signatures for a device is as follows: To learn a device, connect the test leads between the PFL and the device to be learnt (ensure the COM lead is connected to the board), highlight the device in the device list and press the Test button or the Foot Pedal. The PFL acquires the device signatures. Testing the board via the board image To acquire signatures or to test a device using the board image, double click the rectangle round the device. When the device is tested the rectangle changes from white to green to indicate a PASS or red to indicate a FAIL.
Hint: If there are no reference signatures stored for a device, pressing Loop will acquire and verify in one operation
Use Loop to verify that signatures are stable (indicated by a consistent Pass). View the signatures to check they appear to be correct. To view the signatures click the View ASA, View ICT or View Links buttons to display the windows containing the device signatures. See Viewing ASA signatures, Viewing ICT data and Viewing Links data. If the signatures are correct use the Device Save function to store the good signatures to hard disk.
Press the Save button on the Tool Bar to save signatures
At this point the PFL will check if any of the ASA signatures are open-circuit and indicate any open pins. The user should verify that this correct (i.e. not due to poor contact on the test chips, etc.) before saving the data as a reference. Saving data for alternative vendors To acquire reference signatures for the same device from another vendor, connect the test clips to the device and press the Test button. Press the Save button to store the signatures as reference and enter the new vendor name.
Note: When the PFL 780 executes a test it always tests against all vendors until a match is found.
The vendor name is shown in the list box on the Tool Bar the results of an acquisition can be viewed against any vendor by selecting the vendor from the list.
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Rearranging the test list The buttons in the Test List window enable programmers to change the order of the components in the test list. Pressing a button (e.g. Reference, Type, etc.) toggles the order of the device list between ascending and descending. This allows the test list to be sorted, for example, by circuit reference or by devices with the same number of pins (i.e. using the same test clip or Polar SMD probe). Removing a device from the test list Use the Delete command from the Device menu to remove a component from a program. Highlight the device to be removed and select Delete (or press the <Delete> key) If the device has reference signatures the system issues a warning prompt; press Yes to confirm the Delete operation. If the device was associated with a location in Board Layout view the device location is removed from the board image. Editing the test list The test list can be edited (i.e. device entries moved or copied) with the Cut, Copy and Paste commands from the Device menu. Use the Cut and Paste commands to move a device within the test list. To copy a device, i.e. to make multiple entries for similar devices, use the Copy and Paste commands it will be necessary to learn signatures for each device inserted in this way. Cut The Cut command removes the device's entry from the test list; its data and signatures are kept in the PFL's scratch-pad memory. Paste The Paste command inserts the contents of the PFL scratchpad memory into the test list before the highlighted device Copy The Copy command copies the highlighted device's data only to the PFL scratch-pad (signatures are not copied). Printing a test program Select the Print command from the File menu to obtain a hard copy of the Test Program the list of devices with their associated test parameters for the selected test program. Select Print Preview from the File menu to view the test program before printing. Use the Print Preview Toolbar to move through and change the view of the document.
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Board Notes
If the system is Unlocked the Board Notes file can be edited during device testing to add fault-finding hints "on-line".
Each test program includes an associated Board Notes text file which may contain information relating to the board or module (e.g. connection details, list of clips required, the date the program was written) or expanded instructions for a specific test if there is insufficient space in the device Notes field. Choose Notes from the Board menu add notes, instructions, etc. as required. When editing is complete, press OK. Deleting a device location To remove the association between a device location on the board image and the device in the test list, right click the mouse over the device location and choose Delete Location.
Saving the test program To save a test program choose the Save As command from the File menu the Save As dialog box is displayed. Enter a name for the program in the File name box (it is not necessary to supply the .pfl extension it will be supplied automatically) and press Save. Naming test programs Program names must be unique to make it easier to locate test programs, use descriptive filenames (e.g. Main Controller Board). The complete path to the file, including drive letter, server name, folder path, and filename, can contain up to 255 characters. Test program names cannot include any of the following characters: forward slash (/), backslash (\), greater-than sign (>), less-than sign (<), asterisk (*), question mark (?), quotation mark ("), pipe symbol (|), colon (:), or semicolon (;).
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Viewing ASA signatures

Each screen is able to display up to ten signatures from a device. When viewing a multi-pin device, use the mouse or cursor keys to keys to scroll through the pin signatures: <Home> moves the first signature to the top left of the screen <End> moves the last signature to the bottom right of the screen <PgUp> moves to previous page of ten signatures <PgDn> moves to next page of ten signatures The scroll arrows shift the display one signature up or down. Controlling ASA signature display order
Right click the mouse in the ASA view window to alter the voltage range in View by Pin
By default the stored signatures are displayed in descending order of deviation from the reference signatures (View by Error). Select the View by Pin from the View menu to view signatures by each voltage range for which signatures are available. Producing hard copies of signatures Select Print from the File menu to produce a hard copy of the stored signatures for the selected device. Select Print Preview to view the hard copy before actually printing the signatures.
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Viewing ICT data

The ICT View screen displays a pin connection diagram of the selected integrated circuit type along with a timing diagram portraying the pins' status during test. Logic Diagram The Logic Diagram shows the status of each pin at each "tested" step in the selected device's test program (test step numbers are shown above the diagram). Note: There may be transitions that occur between these steps (e.g. a series of clock pulses when testing a counter). These transitions are not shown in the diagram. The reference data is shown in green. Levels are shown as High, Low, Tristate (shown as a dashed line between the High and Low levels) or Don't Care (shown as a hashed area). Use the up and down cursor keys to view the test waveforms on other pins of the device.
Viewing Links data

Selecting the ASA Links or ICT Links functions will display the Links data for the device. The Links diagram The Links (i.e. pin connection) window shows the signal lines and associated pin numbers of the reference device. Lines that are at detected as being at a fixed potential are shown as Stuck pins: Stuck pins Pins that are stuck high are shown connected to a positive supply rail. Pins that are stuck low are shown connected to ground. Confirmed links Confirmed links refer to pins which are connected on the reference board. Link lines matching the reference device are displayed in green. Unexpected links are shown in red.
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Board testing
Testing a board To test a board follow the procedure below: Creating a new program
From the File menu select New the PFL opens a new Test List window. Optionally, switch to Board Layout view and from the Board menu choose Set Board Bitmap and import a bitmap into the program. Select Insert to add a device to the list. Associate each device in the test list with the device location on the board image. Use the Test function to acquire and verify reference signatures for the devices View the device signatures via the ASA, ICT and Links windows Insert the other devices into the program Add Notes to the board or devices as necessary Save the program
Testing the board

From the File menu use the Open command to choose and load the program for the board. Highlight the device to be tested from the Test List or click on the device on the board image. Click the Test button or press the Foot Switch to run the test on the device (follow the instructions, if any, in the Notes box). (Optionally) view the results screens if the test produced a Pass result or continue through the program testing the other devices.
Excluding test types

Where a device would normally use ASA, ICT and Links tests the user can if required disable either of the test types. From the Board menu choose Disable test type and remove the tick mark from the test type to be excluded the device will be tested with only the remaining test type. If a test type is disabled there will be no tick or cross in the corresponding tab on the Test List view.
Performing tests continuously with the Loop command

Selecting the Loop command from the Device menu performs the test continuously. The Loop test is useful for detecting intermittent logic problems or faulty
Polar Fault Locator
connections. The PFL provides three Loop operations Loop until pass, Loop until fail and Loop forever. Press <Esc> to terminate the Loop command.
Advanced Editing
The test parameters used by default will be found satisfactory for most device tests. The Advanced Edit command in the Device menu allows the programmer to modify test parameters (e.g. to exclude test types, specify different voltage or frequency ranges, etc.) for each device in the test program. The Advanced Edit function includes tab settings:
General ASA ICT Pulser Notes Pin Names Disable Result
Using the Advanced Edit dialog box General settings The General settings tab includes details of the device type, circuit reference, number of pins and device function. Click into the device Ref: or Description: fields to modify the circuit reference or device descriptions for the selected device. The Test Types box indicates which test types are included for the device test types may be included or excluded from the current test by clicking the associated check boxes. The ASA Links and ICT Links are mutually exclusive. The graphic displayed in the test window can be selected to match the outline of the device under test. Choose the DIP option to display the dual-in-line package graphic or the SOIC to display the Small-Outline IC device style. Where the displayed device graphic does not match the actual outline of the device under test the graphic can be turned off with the Disable Graphic option. Pin numbering is not affected. Specifying the ASA settings ASA test conditions for the device under test (voltage ranges, frequency, etc.) are specified via the ASA tab.
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Specifying voltage ranges Select the Range field the currently selected voltage ranges will be shown ticked. Each range can be toggled on and off with the mouse or by its associated selection key. Note that test time and storage requirements will increase with the number of ranges selected. Setting the comparison threshold Selecting the Tolerance field allows the user to specify the sensitivity of the signature comparison as a percentage value.
The most effective values will be found by experiment; start with a value of 5% and adjust for a sensitivity which will allow normal component tolerances but capture faulty devices.
Percentage values from 1 99% may be specified. Lower values represent a more exacting comparison, higher values will allow greater differences in signatures.
Frequency Setting the test frequency Highlight the Frequency field and select Low or Medium or High frequency as applicable the active frequency range will be highlighted. The time taken to conduct a device test will depend on the test frequency testing at the higher frequencies will be performed more quickly than at lower frequencies but will exhibit greater variation due to stray capacitance. Pre Charge Controlling the range and pin switching rate In some circuit configurations, signatures may vary with time during the acquisition (highly capacitive circuits may exhibit charging times which are much greater than the signature acquisition time). The Pre Charge function allows the program to vary the rate at which signatures are acquired. Highlight the Pre Charge function and specify a value from 1 9999mS. The optimum value will be found by experiment. The default setting is 0mS (i.e. fastest acquisition). Pin by Pin If a standard test clip cannot be used for a device (if, for example, a DIP case style device proves inaccessible) the user can specify Pin by Pin and use a single pin test probe to test the device one pin at a time. Whenever signatures are acquired for the Pin by Pin box is displayed with a prompt to probe the first pin:
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Using the Foot Switch to step through the device pins will help probe devices in inaccessible locations
Probe the pin and press OK the PFL will increment to the next pin number until the device is fully tested.
Specifying the ICT settings (PFL780 only) Selecting the Ict option activates the ICT Settings box and enables the user to specify the ICT parameters for the device (logic levels and step rate). Levels specifying the logic voltage thresholds The Levels field allows the user to select the logic voltage thresholds to be used during an ICT test. The High field specifies the minimum voltage which will be recognised as a logical high; the Low field specifies the maximum voltage recognised as a logical low. The Ttl and Cmos options provide predefined values for the High and Low fields. Select Ttl or Cmos as appropriate. The default values will be found satisfactory for most testing applications. The logic levels can be altered from the default values if the User option is selected. Select User the High and Low logic level fields will be enabled. Move to the field to be set; use the left and right cursor keys to alter the logic levels (in 0.1V increments) to the desired value. The High level will always be greater than the Low level. Pre Charge The Pre Charge function controls the delay prior to each "tested" step during the ICT test. The default setting is 0S (i.e. fastest acquisition); this rate will be found suitable for most applications The time can be altered, if necessary, to allow for propagation delay, etc. Highlight the Pre Charge function and specify a value from 1 999S. The optimum value will be found by experiment. Note: The ICT test time is guaranteed to be less than 16ms only when the Pre Charge is set to 0.
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Using the Pulse Generator Note: If the Pulser is being used it is recommended that Junction Range is disabled in the ASA settings. The Pulse Generator incorporated with the PFL will be found useful for testing many types of 3-terminal devices (e.g. SCRs, triacs, opto-isolators). Setting the Pulse Generator See ASA Device Testing for a discussion of Pulser applications. To incorporate the Pulse Generator in a test, Press the Pulser tab and select the Pulse type P1, P2 or DC as required. Select the Width field to specify the width of the applied pulse type a number between 1 and 100 in the Width field. The amplitude of the pulse is similarly set via the Level field; activate the field and specify a value between 1 and 100%. The default values are 50%. Pin Names To change the name assigned to a device pin (IRQ, CLK, etc.) click the Pin Names tab, scroll down and highlight the pin, then edit the name in the editing box. Disabling test results for device pins There may be occasions when it proves difficult to achieve repeatable results for a pin on a device (e.g. if the pin is subject to charging effects). In this case it the test could record a FAIL even though the device itself was working satifactorily. Failure in any one of the test types, ASA, ICT, ASA Links or ICT Links will result in a FAIL result. The Disable Results tab allows the programmer to disable the results of any (or all) of the four test types for a pin which is proving unstable. Scroll to the pin number and click the check box in the associated test type the test type will displayed as OFF in the pin list.
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Datalogging
The PFL Datalog function Selecting the PFL Datalog function enables datalogging for the board type under test. Using Datalogging the user can compile statistics of board or component failure rates (for quality or process control, etc.). Datalogging results To enable Datalogging select the Datalog command (in the Board menu) and choose Enable (a tick will appear next to Enable to indicate Datalogging is enabled). Enabling Datalogging adds a %Fail column to the Test List window. Test each device on the board. When the board is completed the data for the board can be logged with the Log results command (in the Board menu) the result log for the most recent series of device tests is displayed. To avoid logging incorrect data, the user can edit the result for a device prior to logging by clicking on the device circuit reference (toggling the result between a Pass or a Fail) or pressing Clear (which sets all tested devices to Pass). Press OK to log the results. As each set of data is logged the %Fail column is updated to display the accumulated failure rate for each component.
The Board Notes screen can be accessed by clicking the Notes button the operator can then record fault descriptions to the Board Notes text file.
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Rearranging the test list The buttons in the Test List window enable programmers to change the order of the components in the test list. Pressing a button (e.g. Reference, Type, etc.) toggles the order of the device list between ascending and descending. This allows the test list to be sorted, for example, by failure rate or by devices with the same number of pins (i.e. using the same test clip or Polar SMD probe). Initialising the data for a board From the Board menu select Datalog then Initialise to set the values in the %Fail column to zero. (Initialise is only active if the system security status is Unlocked. Disabling Datalogging From the Board menu select Datalog and click Enable to toggle datalogging off. The current contents of the datalog are not affected. Printing the datalog From the File menu select Print to print the Test List which includes the datalog.
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Adding devices to the Library with DevLib
The PFL User Library

The Polar Fault Locator system stores device parameters in device libraries. The instrument ships with two libraries of pre-defined device parameters Library1 and Library2. (These libraries are stored as folders Library1 and Library2 within the Program Files\Polar\Pfl folder on the installation drive). The PFL software provides a third library, User, to which users may add new or special devices, (such as PAL devices). Using DevLib users may add new devices or create aliases for devices currently in the library. To start DevLib click the Start button, choose Programs then the Polar Fault Locator program group then choose the Device Library command. DevLib opens displaying the list of devices in the User Library. Adding a new device to the Library
You can also press the New Device button on the Tool Bar
To add a new device select New from the Device menu the New Device dialog box is displayed:
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Adding devices to the Library with DevLib 81
Specifying the device details

Type the name of the new device in the Name field (e.g. 74999). Enter a brief description of the device (e.g. PAL) in the Description field. Enter the number of pins on the device in the Pin Count field. Specify which pins are used for Vcc and ground. Choose the package type (e.g. DIP). Specify the logic levels TTL or CMOS (only used if the device is a digital device). Specify the test type ASA, ICT Links or both. Note: if an ICT Links test is included the PFL780 applies +5V to the device.
Editing the pin names

To assign names to the device pins choose Pin Names from the Device menu or click the Pin Names button the Pin Name Editor is displayed.
The Pin Names button
Edit the pin name for each pin (it is recommended that names are kept to a maximum of four characters) press Close. From the File menu choose Save.
Creating device aliases Users have the option of supplying a device name as an alias an alternate name for a device in the database. Where a new device is identical functionally to one already present it enables the same ICT functional test driver to be used. Creating an alias for an existing device
To create an alias for a device currently in the library choose Add Alias from the Device menu the Add Alias dialog box is displayed. Supply the name of the device you wish to alias (e.g. 74LS244) and press OK the New Device dialog box is displayed with the parameters of the existing device type. Add the alias name in the Name field and press OK. From the File menu choose Save.
82 Adding devices to the Library with DevLib
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Maintenance and cleaning
Servicing the PFL

WARNING This instrument should only be serviced by a qualified electronics technician.
Refer all servicing to qualified service personnel. Polar Instruments publishes a PFL Service Manual to assist the service technician. Calibration requirements To maintain the calibration of the instrument it is recommended that its Calibration/Adjustment Procedure is carried out at intervals not exceeding 12 months. Input Protection Fuses Channels A and B are protected by fast blow fuses. If the probes are connected to a powered board, or to a large, charged capacitor, these fuses open to minimise damage to the instrument. To replace the channel protection fuses: Disconnect the power cord. Locate the channel protection fuses for Channel A and Channel B on the rear panel of the instrument. Test each fuse for continuity. Replace if necessary. Fuses must only be replaced by fuses of the value and type shown on the label adjacent to the fuse-holder. Reconnect the power cord. Troubleshooting The problem most likely to be encountered is a blown Channel Protection Fuse. When a channel is unconnected, its normal signature is a horizontal line. If its protection fuse has blown, then a vertical (short-circuit) signature will be displayed. Refer to Input Protection Fuses when replacing the fuse. The following symptoms may be investigated by the user. Refer all servicing to qualified service personnel.
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Maintenance and cleaning 83
Symptom
Foot pedal does not operate
Test
Check that the communication cable being used is the cable that was supplied with the instrument. Ensure the board under test is disconnected from any power supply or external ground connection. Check power is switched on. Suspect the line fuse or a power failure. Check that the COM lead is connected. If ASA testing ICs, connect the Vcc and ground pins together. Check the IC Test Clip by swapping the A and B clips. Check that the Com port has been set up correctly. Check that the PC is connected to the PFL. Check that the communication cable being used is the cable that was supplied with the instrument.
PFL reports protection fuse failure, but fuse is OK. No LEDs lit.
Trace unstable
Scanner always indicates a fault on the same pin Communication Error reported by the host computer
Cleaning Clean the instrument with a cloth lightly moistened with water with a small amount of mild detergent. Alternatively, a cloth lightly moistened with alcohol (ethanol or methylated spirit) or isopropyl alcohol (IPA) may be used. Do not spray cleaners directly onto the instrument. Technical Support For technical support contact your local Polar Instruments distributor or Polar Instruments.
84 Maintenance and cleaning
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APPENDIX B ASA Comparison Algorithm
For comparison, the signatures are sampled over n points. In the PFL n is fixed at 100. The Deviation D is defined as:
n
D = 1/n
| Van Vbn | x k%
where Va1, Va2.....Van represent the amplitude of channel A, i.e. the reference signature at comparison points 1, 2.......n and Vb1, Vb2.....Vbn represent the amplitude of channel B, i.e. the signature of the device under test at comparison points 1, 2.......n and k is a scaling factor.
Polar Fault Locator
APPENDIX B ASA Comparison Algorithm 1
APPENDIX C PFL Pin numbering formats
The format of the pin numbering of the PFL inputs depends on the package type selected and the number of pins on the device under test. All illustrations show the instrument viewed from the front. The position of pin #1 is always the same (in the upper right corner when the instrument is viewed from the front).
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APPENDIX C PFL Pin numbering formats 1
2 APPENDIX C PFL Pin numbering formats
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APPENDIX C PFL Pin numbering formats 3
This page is intentionally blank.
4 APPENDIX C PFL Pin numbering formats
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APPENDIX D Test Clips and Probes
SMD Probes
SMD probes may be used in situations where a suitable integrated circuit test clip is unavailable, or where it is physically impossible to attach a test clip to the device under test. An SMD Probe consists of a row of pins (typically 10 or 11 depending on the specific probe) enabling PLCC packages etc., to be tested by probing each side of the device separately. Select SIP mode when using SMD probes. Pin numbering Pin #1 on the SMD Probe is indicated by a dot on the probe head and the red stripe on the cable. Remember when using the probe that the pin number reported by the PFL refers to the probe. If pin #1 of the probe is not connected to pin #1 of the device under test, the user must add an appropriate offset to the number displayed to obtain the correct IC number. Using the probe Warning: The probe pins are sharp. Take care when handling. Push the probe against the device under test so that its pins are perpendicular to the leads of the device. Avoid sliding the probe horizontally as this may damage the probe pins. For convenience it is recommended that the PFL is operated using a foot pedal, leaving the operators hands free to hold the probe and the board under test. Replacing pins The probes pins may be damaged if they are bent or if excessive force is applied to them. Replacement pins are available from your Polar distributor. When ordering pins always quote the probe type (e.g. T131). Replacing a damaged pin
Carefully remove the comb, by pulling away from the probe head as shown below. The comb has two spring-pins,
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APPENDIX D Test Clips and Probes 1
which will usually stay attached to the comb. However, it is not a problem if either stays attached to the probe head. Note: the T132 does not have a comb The spring-pin is mounted in a fixed receptacle. Grip the pin close to where it exits the receptacle, using a pair of pliers. If this point is not easily identified (e.g. the pin may have an additional shoulder) it can be determined by noting that the pin is movable, the receptacle is fixed. Carefully pull the pin away from its receptacle. Gently push the new pin fully into the receptacle until it is retained. Carefully replace the comb, ensuring that its spring-pins engage in the two receptacles in the probe head, and that the pins in the probe head locate through the holes in the comb.
2 APPENDIX D Test Clips and Probes
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Connecting to DIL ICs
IC Test Clips, complete with lead, are available individually or in Test Packs. Each clip is fitted with a lead terminated for a T Series or PFL instrument. Note that ASY106 and ASY107 are usually supplied with the instrument.
No of pins
IC width
Part Number
ACC139 Pack
ACC140 Pack
8 14 16 18 20 22 22 24 24 28 28 40
0.3 0.3 0.3 0.3 0.3 0.3 0.6 0.3 0.6 0.3 0.6 0.6
ASY116 ASY115 ASY107 ASY117 ASY110 ASY118 ASY120 ASY112 ASY114 ASY119 ASY113 ASY106
supplied with product
supplied with product
T132 IC Probe suitable for all 0.1 pitch ICs, consists of 10 pins on a 0.1 pitch. Also available with flux piercing needle pins as part T132/N.
Dual in line IC probe suitable for connecting to DIL ICs with standard 0.3 spacing and 0.1 pitch. T203, 16 pins, DIL outline, 0.3 IC width T204, 20 pins, DIL outline, 0.3 IC width
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Connecting to DIL ICs 3
Connecting to SOICs
IC Test Clips complete with lead are available individually or in a Test Pack. Each clip is fitted with a lead terminated for a T Series or PFL instrument. All clips are suitable for SO and SO(W) outlines.
No of pins
IC width
Part Number
ACC160 Pack
8 14 16 20 24 28
0.1 to 0.2 0.1 to 0.2 0.1 to 0.2 0.1 to 0.2 0.1 to 0.2 0.1 to 0.2
ASY123 ASY124 ASY125 ASY126 ASY127 ASY128
T131 IC Probe suitable for all 0.05 pitch small outline (SO) ICs, consists of 11 pins on a 0.05 pitch.The probe pins are protected by a unique sliding comb assembly which also prevents the probe from slipping off the IC when in use.
Dual in line IC probes suitable for connecting to small outline ICs with 0.05 pitch and width as below: T201, 16 pins, SO-16 outline, 0.1 IC width T202, 20 pins, SO-20W outline, 0.2 IC width The probe pins are protected by a unique sliding comb assembly which also prevents the probe from slipping off the IC when in use.
4 Connecting to SOICs
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Connecting to PLCCs, QFPs, etc.
IC Test Clips, complete with lead, are available individually or in a Test Pack. Each clip is fitted with a lead terminated for a T Series or PFL instrument.
No of pins
Part Number
ACC161 Pack
20 28 32 44 52 68 84
ASY129 ASY130 ASY131 ASY132* ASY133* ASY134* ASY135*
*These clips require interface ACC169 when used with T4000, TD8000 and PFL. Test Pack ACC161 includes ACC169. A range of SMD IC Probes for use on devices with lead pitches as shown in the table below. The pins are arranged so that they can used on any device shape. The probe pins are protected by a unique comb assembly which guides them on to the IC leg and prevents the probe from slipping off the IC when in use.
IC Pitch Part Number No of pins
0.4mm 0.5mm 0.65mm 0.8mm 1.0mm 0.025
T141 T140 T137 T139 T136 T138
32 32 32 16 14 32
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Connecting to PLCCs, QFPs, etc. 5

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Polar Fault Locator

PFL Operator Manual

Polar Instruments Ltd

PFL FAULT LOCATOR OPERATOR MANUAL

European Community Directive Conformance Statement

Polar Fault Locator

Polar Fault Locator

Polar Fault Locator

ASA Test Facilities

ICT Facilities (PFL780 only)

ICT Links User Power Supply

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Environmental operating conditions

Altitude Temperature Relative humidity Mains borne transients

Channel A and B Protection Fuses

Physical characteristics (excluding accessories)

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ACCESSORIES Standard Accessories

Optional Accessories (PFL760, PFL780)

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Polar Fault Locator

Polar Fault Locator

Polar Fault Locator

Polar Fault Locator

Introducing the PFL Fault Locator

Introduction to the PFL Fault Locator

About this manual

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Introducing the PFL Fault Locator 1

Analog Signature Analysis

The PFL component library

2 Introducing the PFL Fault Locator

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goods inwards testing/troubleshooting. rapid diagnostics.

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Introducing the PFL Fault Locator 3

Installing the Fault Locator

Connecting the PFL to a power supply

4 Installing the Fault Locator

Polar Fault Locator

Installing the PFL software

Installing the program

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Installing the Fault Locator 5

Computer control of the PFL

6 Installing the Fault Locator

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Running the program

PFL main window The main window comprises:

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Installing the Fault Locator 7

Setting up the PFL control program environment

8 Installing the Fault Locator

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Reduce Acquisition Priority

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Installing the Fault Locator 9

Changing the system colors

Changing the language option

Upgrading an -EX version instrument

Exiting the PFL program

10 Installing the Fault Locator

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