Beruflich Dokumente
Kultur Dokumente
R
L+X/
RFC
Cd
C
V
DD
V
s
()
I
s
()
useful functions and identities
Units
Constants
_______________________________________
Table of Contents
I. Introduction
II. Process Parameters
III. Inputs
IV. Standard Class E Design Procedure
V. Alinikula Class E Design Procedure
VI. Choi's Class E Design Procedure
VII. References
VIII. Copyright and Trademark Notice
_______________________________________
Introduction
This file is a modification of the routine class-e1.mcd. The modifications include:
1. The addition of finite Q component losses in the overall efficiency of the amplifier.
2. The effects of a finite device output capacitance. Later the effects of the nonlinearity of this capacitance is also
added. This derivation is from reference [1].
3. Units are added.
4. The overall format of the routine is modified for easier use.
A problem with this analysis is that it doesn't take into account overall transmitter chain efficiency due to finite gain loss
of the power amplifier. This may set an upper limit on the device size, which will in turn make the drain capacitance
part linear capacitance and part nonlinear capacitance. The design also does not take into account the input power
back-off required to meet ACPR (adjacent channel power ratio) requirements. This will also degrade efficiency.
1
Q 7 : Q of Matching Network (Optimum Value can be
found: Higher value leads to narrower band and
more dependence on process variations and
finite Q elements. Lower value degrades
efficiency directly)
f 0.9 GHz : Center Frequency
t
r
0.1 nS : Rise Time
_______________________________________
Standard Class-E Synthesis Procedure
2 f : 5.655
Grad
sec
Center Frequency
R
s
0.577 V
dd
V
sat
( )
2
P
a
: R
s
1.496ohm Device Load Resistance
L
s
Q R
s
: L
s
1.851nH Matching Inductance
C
p
1
R
s
5.447
: C
p
21.707pF Matching Capacitances
C
s
C
p
5.447
Q
,
1
1.42
Q 2.08
+
,
: C
s
21.767pF
V
p
3.562 V
dd
2.562 V
sat
: V
p
6.612V Peak Output Voltage
A 1
0.82
+
_
f t
r
: A 0.101
_______________________________________
Process Parameters
C
j0
0.4
fF
m
2
: Bottom Plate Capacitance for Zero-Biased Reverse Biased Diode
C
jsw
0.4
fF
m
: Sidewall Capacitance for Zero-Biased Reverse Biased Diode
m
j
0.77 : Exponent for Reverse Biased Diode Capacitance
V
bi
1V : Fermi Potential for Reverse Biased Diode
N
300
cm
2
Vsec
: Device Effective Mobility
C
OX
2
fF
m
2
: Device Gate Capacitance per Unit Area
mA_m 0.5
mA
m
: Electromigration Limition on Line Width
L
min
0.5m : Minimum Line Width
V
TN
0.7V : Threshold Voltage
_______________________________________
Inputs
V
dd
2V : Supply Voltage
V
sat
0.2V : Minimum Device Drain to Source Voltage
P
a
1.25watt : Power Available at Drain
2
Device Output Capacitance
R
8
2
4 +
V
dd
2
P
a
: R 1.846 Load Resistance
X
2
4
( )
2
2
4 +
( )
V
dd
2
P
a
: X 2.127 Load Reactance
v
Dmax
2 atan
2
,
V
dd
: v
Dmax
7.124V Maximum Drain Voltage
R
R 1.365
V
sat
I
dc
+
: 0.831 Drain Efficiency
Solution Assuming a Nonlinear Capacitor
v
D
( ) V
bi
1
C
j0
V
bi
n 1 + ( )
I
DC
v
out
R
cos + ( ) + cos ( )
,
1 +
1
1
]
n 1 +
1
1
1
1
]
=
v
D
( ) V
bi
z
n 1 + ( )
v
out
R I
DC
cos + ( ) cos ( ) ( ) +
1
1
]
1 +
1
1
]
n 1 +
1
1
1
1
]
=
v
D
z , ( ) V
bi
z
n 1 +
2
cos ( ) + sin ( ) +
2
,
1 +
1
1
]
n 1 +
1
1
1
]
: Drain Voltage
Using Root Finder to solve for z
40
60
1
( )
A 1
0.82
Q
+
,
f t
r
: A 0.101
I
dc
P
a
V
dd
1
2 A ( )
2
12
1
2 A ( )
2
6
V
sat
V
dd
,
1 A +
2 A ( )
2
6
1
1
]
: I
dc
727.896mA DC Current
I
p
I
dc
1 1.862 1
0.5
Q
,
+
1
1
]
: I
p
1.986amp Peak Current
P
dc
V
dd
I
dc
: P
dc
1.456 watt DC Power
P
a
P
dc
100 : 85.864 Efficiency
_______________________________________
Alinikula's Class E Design Analyis and Synthesis
Solution Assuming a Linear Capacitor
n
m
j
1 m
j
: C
D
17.59pF
3
I
DC
z C
j
V
bi
: I
DC
624.998mA DC Current
L
X
: L
res
2.285nH Resonant Inductance
v
Dmax
V
bi
z
n 1 +
2 atan
2
,
1 +
1
1
]
n 1 +
1
1
1
]
: v
Dmax
8.764V Maximum Drain Voltage
N
I
DC 1
:
10 5 0 5 10
20
0
20
1
2
0
v
D
z
guess
, ( )
d
V
dd
z
guess
z I
DCguess
V
dd
R
z
guess
I
DCguess
C
D
V
bi
root V
dd
1
2
0
v
D
z
guess
, ( )
d z
guess
,
,
: z 2.642 Variable used for more efficient
calculation.
1
atan
0
v
D
z , ( ) cos ( )
d
0
v
D
z , ( ) sin ( )
,
:
1
18.922deg Fundamental Frequency Phase
Angle at node A
a
1
1
v
D
z , ( ) cos ( )
,
2
0
v
D
z , ( ) sin ( )
,
2
+ : a
1
3.443V Fundamental Frequency
Amplitude at node A
R
8
2
4 +
V
dd
2
P
a
: R 1.846ohm Load Resistance
X R tan
1
atan
2
,
: X 2.312 Load Reactance
C
j
3.562 V
dd
z 2 atan
2
,
V
bi
C
D
:
C
j
41.837pF Drain Capacitance
4
Drain Efficiency
_______________________________________
Choi's Class E Design Procedure
Notes about this design procedure:
1. It does not include the effects of inductive source degeneration, but instead models it as a resistive source
degeneration. The paper does not say what the degeneration is, but it implies it is the same as the gate impedance
2. It does not calculate the input impedance, which is necessary for matching to the driver amplifier. This impedance
changes during the cycle, so what value do you use for the input matching network? The average value?
3. It does not calculate the required input signal swing, Vs, to generate the required output power. It is possible to use
the equations in reverse to find the required Vs, but will surely be non-linear, so iterative technques must be used.
Since iterative techniques must be used it might be more appropriate not to solve the equations in reverse, but instead
use constraint-based optimization to meet the two conditions of output power and maximize PAE.
4. It does not include parasitic losses of the output matching network. This should be a simple addition.
2
900MHz Center frequency of oscillator
R 50ohm :
P
out
P
a
: P
a
1.25 watt Designed output power at the drain.
P
out
1watt :
C
d
P
out
V
dd
2
: C
d
14.072pF Drain capacitance
N
546
cm
2
Vsec
: Device mobility
sq 1 :
K
n
200
A
V
2
: Instrinsic transconductance
gatefinger 1 :
r
m
0.07
: Metal resistance
N
I
DC
mA_m
1
3 L
min
:
N 833.331 Number of Devices in Parallel
The following equation for the drain capacitance is based on a layout, where the drain is layed out
C
j
N
C
j0
3 L
min
W
0
C
jsw
2 W
0
3 L
min
+ ( ) +
2
=
W
0
C
j
2
N
3 L
min
C
jsw
2
C
j0
3 L
min
C
jsw
2 +
:
W
0
70.863m Width of Each Segment
W W
0
N : W 59.053mm Width of Overall Device
Length L
min
3 L
min
N + : Length 1.25mm Length of N Devices
Area W
0
4 L
min
N : Area 0.118mm
2
Overall Area of Device
R
on
1
N
C
OX
V
dd
V
TN
( )
W
L
min
: R
on
0.109 On Resistance of Device
R
R 1.365R
on
+
: 92.569%
5
C
gs
n ( ) n c
gs
: Gate to source capacitance
c
gd0
C
GD0
W :
c
gd0
0.038pF C
gdo
n ( ) n c
gd0
: Gate to drain capacitance
C
gd
n ( ) C
gdo
n ( )
C
gs
n ( )
2
+ :
I
d
( )
K
n
W
2 L
2 V
gs
( ) V
ds
( ) V
ds
( )
2
_
,
= 2 I
DC
=
V
sm
4.3V :
V
gsmag
n V
sm
, ( )
V
sm
1 R
g
n ( ) R
s
n ( ) + ( ) C
gs
n ( ) C
gd
n ( ) + ( )
1
]
2
+
:
V
gsmag
n V
sm
, ( ) 4.059V
n ( ) atan R
g
n ( ) R
s
n ( ) + ( ) C
gs
n ( ) C
gd
n ( ) + ( )
1
]
: n ( ) 0.337
V
gs
( ) V
gsmag
n ( ) sin n ( ) + ( ) I
d
( ) R
s
n ( ) : I
d
V
gs
n , V
sm
, ( ) V
gsmag
n V
sm
, ( ) sin n ( ) + ( ) : V
gs
n , V
sm
, ( ) 1.34V
100 200
0
1
2
V
gs
nval , 0V , ( )
V
gs
nval , 2V , ( )
V
gs
nval , 5V , ( )
nval
2 R
s
n ( ) C
d
V
dd
V
gs
n , V
sm
, ( ) ( ) 2 C
d
L
K
n
W
V
gs
n , V
sm
, ( ) 11.14 kg m
2
s
-3
A
-1
a n ( ) 1 2 C
d
R
s
n ( ) : a n ( ) 0.696
r
m
0.07
sq
: Metal resistance
r
c
1.8
gatefinger
: Metal-poly contact resistance
R
s
n ( ) r
m
r
c
n
+ : Resistance in the source R
s
n ( ) 0.608
gate
1.9
sq
: Polysilicon sheet resistance
C
GD0
3 10
10
farad
m
: Gate to drain overlapp capacitance
W 125m : Width of one finger
L 0.5m : Length of one finger
r
g
gate
3
W
L
r
c
+
,
:
r
g
160.133 R
g
n ( ) r
m
r
g
n
+ : Gate resistance
c
gs
K
n
W L
N
:
c
gs
0.229pF
6
1
P
DC
n V
sm
, ( ) 0.748 watt P
DC
n V
sm
, ( )
C
d
V
dd
V
dmin
n V
sm
, ( ) ( )
1 2 R
s
n ( ) C
d
+
V
dd
: P
DC
I
DC
V
DD
=
I
DC
n V
sm
, ( ) 0.374amp I
DC
n V
sm
, ( )
C
d
V
dd
V
dmin
n V
sm
, ( ) ( )
1 2 R
s
n ( ) C
d
+
:
V
dmin
n V
sm
, ( ) 0.05V :
0 2 4
0
20
40
V
dmin
n V
smval
, ( )
V
smval
0 50 100 150 200
0
10
20
30
V
dmin
nval V
sm
, ( )
nval
V
dmin
n V
sm
, ( ) 30.094V
V
dmin
n V
sm
, ( )
b n V
sm
, ( ) b n V
sm
, ( )
2
4 a n ( ) c n ( ) +
2 a n ( )
:
c n ( ) 40V
2
c n ( )
4 C
d
K
n
W
L
V
dd
:
c n ( ) 40V
2
c n ( ) 4 C
d
L
K
n
W
V
dd
:
b n V
sm
, ( ) 22.279 kg m
2
s
-3
A
-1
b n V
sm
, ( ) 2 V
gsmag
n V
sm
, ( ) sin n ( ) + ( ) 1 2 R
s
n ( ) C
d
+ ( ) 4 C
d
V
dd
R
s
n ( ) +
4
K
n
W
L
C
d
:
b n V
sm
, ( ) 22.279 V
b n V
sm
, ( ) 2 2 R
s
n ( ) C
d
V
dd
V
gs
n , V
sm
, ( ) ( ) 2 C
d
L
K
n
W
V
gs
n , V
sm
, ( )
1
1
]
:
a n ( ) 0.696
a n ( ) 1 2 R
s
n ( ) C
d
:
1 2 R
s
n ( ) C
d
+ 1.304
a n ( ) 0.696 a n ( ) 1 2 C
d
R
s
n ( ) :
7
0 50 100 150 200
0
0.5
1
P
DC
nval V
sm
, ( )
nval
V
d
( ) if < I
DC
n V
sm
, ( ) R
s
n ( ) 1
2
sin ( ) + cos ( )
V
dmin
n V
sm
, ( ) +
... ,
I
DC
n V
sm
, ( )
C
d
3
2
2
cos ( ) sin ( )
V
dmin
n V
sm
, ( ) 2 I
DC
n V
sm
, ( ) R
s
n ( ) + +
... ,
1
1
1
]
:
I
d
( ) if < I
DC
n V
sm
, ( ) 1
2
sin ( ) + cos ( )
,
, 0V ,
1
1
]
:
0 2 4 6
0
5
10
V
d
( )
V
dmin
n V
sm
, ( )
0 2 4 6
1
0
1
I
d
( )
V
dmax
n V
sm
, ( ) 1.13
I
DC
n V
sm
, ( )
C
d
V
dmin
n V
sm
, ( ) + 2 I
DC
n V
sm
, ( ) R
s
n ( ) + :
0 50 100 150 200
0
5
10
V
dmax
nval V
sm
, ( )
nval
P n V , ( )
2
V
sm
r
g
c
gs
c
gd0
+ ( )
2 V c c + ( ) V n V , ( ) c +
1
:
8
P
in
n V
sm
, ( )
V
sm
4
r
g
c
gs
c
gd0
+ ( )
1 r
g
c
gs
c
gd0
+ ( )
1
]
2
+
2 V
sm
c
gs
c
gd0
+ ( ) V
dmax
n V
sm
, ( ) c
gd0
+
1
]
:
P
in
n V
sm
, ( )
2
V
sm
4
n n r
m
r
g
+ ( ) c
gs
c
gd0
+ ( )
1
2
n r
m
r
g
+ ( )
2
c
gs
c
gd0
+ ( )
2
+
2 V
sm
c
gs
c
gd0
+ ( ) V
dmax
n V
sm
, ( ) c
gd0
+
1
]
:
0 50 100 150 200
0
0.5
1
P
in
nval V
sm
, ( )
nval
P
out
n V
sm
, ( )
2
4 +
8
I
DC
n V
sm
, ( )
2
R 1
R
s
n ( ) C
d
,
2
+
1
1
1
]
:
0 50 100 150 200
0
10
20
P
out
nval V
sm
, ( )
nval
Efficiency n V
sm
, ( )
I
DC
n V
sm
, ( ) R
2
4 +
( )
1
R
s
n ( ) C
d
,
2
+
1
1
1
]
8 V
dd
:
0 50 100 150 200
0
50
100
Efficiency nval V
sm
, ( )
nval
Gain
P
out
P
in
= Gain nval V
sm
, ( )
I
DC
n V
sm
, ( )
2
R
2
4 +
( )
1
R
s
n ( ) C
d
,
2
+
1
1
1
]
1 R
g
n ( ) C
gs
n ( ) C
gdo
n ( ) + ( )
1
]
+
2 V
sm
2
R
g
n ( ) C
gs
n ( ) C
gdo
n ( ) + ( ) 2 V
sm
C
gs
n ( ) C
gdo
n ( ) + ( ) V
dmax
n V
sm
, ( ) C
gdo
+
:
1042
9
0 50 100 150 200
1039
1040
1041
Gain nval V
sm
, ( )
nval
PAE n V
sm
, ( ) Efficiency
P
in
P
DC
:
_______________________________________
References
[1] "Design of a Class E Power Amplifier with a Nonlinear Parasitic Output Capacitance," by Petteri Alinikula et. al.,
IEEE Transactions on Circuits and Systems II, vol. 46, no.2, February 1999.
[2] "Class E CMOS Power Amplifier," by Martin Tsai.
[3] "The use of parasitic nonlinear capacitors in class E amplifiers," by M. J. Chudobiak, IEEE Transactions on
Circuits and Systems, vol. 34, pp. 941-944. December 1994.
[Sokal] N.O. Sokal and A. D. Sokal, "Class E-A new class of high-efficiency tuned single-ended switching power
amplifiers," I.E.E.E. Journal of Solid State Circuits, vol. SC-10, pp. 168-176, June 1975.
[Li] C. Li and Y. Yam, "Analysis and design of the class E amplifier with non-zero ON resistance," Microwave Opt.
Technology Letters. vol. 7, pp. 337-341, May 1994.
[Choi] David K. Choi and Stephen Long, "A Physically Based Analytic Model of FET Class-E Power
Amplifiers--Designing for Maximum PAE."
_______________________________________
Copyright and Trademark Notice
All software and other materials included in this document are protected by copyright, and are owned or
controlled by Circuit Sage.
The routines are protected by copyright as a collective work and/or compilation, pursuant to federal copyright
laws, international conventions, and other copyright laws. Any reproduction, modification, publication, transmission,
transfer, sale, distribution, performance, display or exploitation of any of the routines, whether in whole or in part,
without the express written permission of Circuit Sage is prohibited.
10