Analog

BiCMOS DESIGN
Practices and Pitfalls

Analog

BiCMOS DESIGN
Practices and Pitfalls
James C. Daly
Department of Electrical and Computer Engineering University of Rhode Island

Denis P. Galipeau
Cherry Semiconductor Corp.

CRC Press Boca Raton London New York Washington, D.C.

Foreword
This book presents practical methods and pitfalls encountered in the design of biCMOS integrated circuits. It is intended as a reference for design engineers and as a text for an introductory course on analog integrated circuit design for engineering seniors and graduate students. A broad range of topics are covered with the intent of giving new designers the tools to complete a design project. Most of the topics have been simplied so they can be understood by students who have had a course in electronics. The material has been used in a course open to seniors and graduate students at the University of Rhode Island. In the course, students were required to design an analog integrated circuit that was fabricated by Cherry Semiconductor Corporation. In the process of assembling material for the book, we had discussions with many people who have been generous with information, ideas and criticism. We are grateful to James Alvernez, Mark Belch, Brad Benson, Mark Crowther, Vincenzo DiTommaso, Je Dumas, Paul Ferrara, Godi Fischer, Justin Fisher, Robert Fugere, Brian Harnedy, David Harrington, Ashish Kirtania, Seok-Bum Ko, Shawn LaLiberte, Andreas Ladas, Sangmok Lee, Eric Lindberg, Jien-Chung Lo, Robert Maigret, Nadia Matchey, Andrew McKinnon, Jay Moser, Ted Neira, Peter Rathfelder, Shelby Raymond, Jon Rhan, Paul Sisson, Michael Tedeschi, Claudio Tuozzolo, and Yingping Zheng. Finally, we owe our thanks to the management and engineering sta of Cherry Semiconductor Corporation. CSC has fabricated scores of analog IC designs generated by the URI students enrolled in the course that has been the basis for this book. James C. Daly Denis P. Galipeau

2000 by CRC Press LLC

Contents
1 Devices 1.1 Introduction 1.2 Silicon Conductivity 1.2.1 Drift Current 1.2.2 Energy Bands 1.2.3 Sheet Resistance 1.2.4 Diusion Current 1.3 Pn Junctions 1.3.1 Breakdown Voltage 1.3.2 Junction Capacitance 1.3.3 The Law of the Junction 1.3.4 Diusion Capacitance 1.4 Diode Current 1.5 Bipolar Transistors 1.5.1 Collector Current 1.5.2 Base Current 1.5.3 Ebers-Moll Model 1.5.4 Breakdown 1.6 MOS Transistors 1.6.1 Simple MOS Model 1.7 DMOS Transistors 1.8 Zener Diodes 1.9 EpiFETs 1.10 Chapter Exercises 2 Device Models 2.1 Introduction 2.2 Bipolar Transistors 2.2.1 Early Eect 2.2.2 High Level Injection 2.2.3 Gummel-Poon Model 2.3 MOS Transistors 2.3.1 Bipolar SPICE Implementation

2000 by CRC Press LLC

2.4

2.5

Simple Small Signal Models for Hand Calculations 2.4.1 Bipolar Small Signal Model 2.4.2 Output Impedance 2.4.3 Simple MOS Small Signal Model Chapter Exercises

3 Current Sources 3.1 Current Mirrors in Bipolar Technology 3.2 Current Mirrors in MOS Technology 3.3 Chapter Exercises 4 Voltage References 4.1 Simple Voltage References 4.2 Vbe Multiplier 4.3 Zener Voltage Reference 4.4 Temperature Characteristics of Ic and Vbe 4.5 Bandgap Voltage Reference 5 Ampliers 5.1 The Common-Emitter Amplier 5.2 The Common-Base Amplier 5.3 Common-Collector Ampliers (Emitter Followers) 5.4 Two-Transistor Ampliers 5.5 CC-CE and CC-CC Ampliers 5.6 The Darlington Conguration 5.7 The CE-CB Amplier, or Cascode 5.8 Emitter-Coupled Pairs 5.9 The MOS Case: The Common-Source Amplier 5.10 The CMOS Inverter 5.11 The Common-Source Amplier with Source Degeneration 5.12 The MOS Cascode Amplier 5.13 The Common-Drain (Source Follower) Amplier 5.14 Source-Coupled Pairs 5.15 Chapter Exercises 6 Comparators 6.1 Hysteresis 6.1.1 Hysteresis with a Resistor Divider 6.1.2 Hysteresis from Transistor Current Density 6.1.3 Comparator with Vbe -Dependent Hysteresis

2000 by CRC Press LLC

6.2 6.3 6.4 6.5 6.6 6.7 6.8

The Bandgap Reference Comparator Operational Ampliers A Programmable Current Reference A Triangle-Wave Oscillator A Four-Bit Current Summing DAC The MOS Case Chapter Exercises

7 Amplier Output Stages 7.1 The Emitter Follower: a Class A Output Stage 7.2 The Common-Emitter Class A Output Stage 7.3 The Class B (Push-Pull) Output 7.4 The Class AB Output Stage 7.5 CMOS Output Stages 7.6 Overcurrent Protection 7.7 Chapter Exercises 8 Pitfalls 8.1 IR Drops 8.1.1 The Eect of IR Drops on Current Mirrors 8.2 Lateral pnp 8.2.1 The Saturation of Lateral pnp Transistors 8.2.2 Low Beta in Large Area Lateral pnps 8.3 npn Transistors 8.3.1 Saturating npn Steals Base Current 8.3.2 Temperature Turns On Transistors 8.4 Comparators 8.4.1 Headroom Failure 8.4.2 Comparator Fails When Its Low Input Limit Is Exceeded 8.4.3 Premature Switching 8.5 Latchup 8.5.1 Resistor ISO EPI Latchup 8.6 Floating Tubs 8.7 Parasitic MOS Transistors 8.7.1 Examples of Parasitic MOSFETs 8.7.2 OSFETs 8.7.3 Examples of Parasitic OSFETs 8.8 Metal Over Implant Resistors 9 Design Practices 9.1 Matching 9.1.1 Component Size 9.1.2 Orientation

2000 by CRC Press LLC

9.2 9.3 9.4

9.1.3 Temperature 9.1.4 Stress 9.1.5 Contact Placement for Matching 9.1.6 Buried Layer Shift 9.1.7 Resistor Placement 9.1.8 Ion Implant Resistor Conductivity Modulation 9.1.9 Tub Bias Aects Resistor Match 9.1.10 Contact Resistance Upsets Matching 9.1.11 The Cross Coupled Quad Improves Matching 9.1.12 Matching Calculations Electrostatic Discharge Protection (ESD) ESD Protection Circuit Analysis Chapter Exercises

2000 by CRC Press LLC