Cadence Design Tools

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Getting Started with RTL Compiler

Use the following brief steps to perform synthesis of your functional Verilog code in the AMS 0.35u Hit-KIT. This process results in gate-level Verilog code based on the AMS digital libraries that can be used for automated place & route and can be imported into the DFII framework (schematic, functional, and/or symbol views) for mixed and analog simulation In this tutorial you will set up your directory, obtain and prepare the tcl script, launch the RC (RTL Compiler) program, source your script RTL Compiler: Bin to Therm Example Setting up the Directory: 1. Create a new directory called "synthesis" inside your current working directory (the directory you type "ams_cds ...." out of) 2. For each new verilog module you synthesize create a new directory inside of your "synthesis" directory 3. So for this example my directory structure looks like this: proj_5837/synthesis/bin_to_therm 4. Important Now inside this bin_to_therm directory (or whatever your directory is) create a VERILOG folder Preparing the files: In this section we will get the files and prepare them to work with a specific verilog file To move this file and edit it, I transferred the file to my windows desktop using 'SSH file transfer client' and edited it with a txt editor.You can move and edit the file any way you see fit 1. Obtain the rtl.tcl file from /usr/local/candence/cadence/tutorials/rtl.tcl this is a tcl script (you can either copy it to your "bin_to_therm" (or equivalent) folder or use SSH file transfer client to copy it to you desktop) 2. Now open this file so you can edit it it should look like the following:

3. Read over the file and familiarize your self on what it is doing. Then change the two lines it asks you to.Follow the instructions in the tcl scrit 4. Now that the tcl script has been changed correctly move the rtl.tcl file (if its not already there) to your equivalent "bin_to_them" directory 5. Put a copy of your verilog file in to your VERILOG folder, make sure it has the same name as you specified in the rtl.tcl file 6. So now my directory structure of bin_to_therm looks like this: "synthesis" contains VERILOG/ & rtl.tcl; the folder "VERILOG/" contains verilog.v Running RC and sourcing the script

1. From your equivalent "bin_to_therm" directory type rc -gui don't try to run it in the background you need to have access to its command line 2. The following gui window and command line should appear:

3. At the rc:/> prompt type source rtl.tcl, this will source the tcl script your created early 4. If every thing was done correctly and your verilog code is correct you should receive the following message and the gui widow should show the layout of your design

5. Read through this output to understand what it is doing: here are some links to the documentation of the RTL Compiler

This document is the RC command reference This document is the RC user guide