EE141

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!! Project

Phase 2 now on the web-site. !! Hw 6 due today. !! New homework to be posted in a week. !! Cory Hall closed on Monday (Power Outage)
"! Instructional computers in 353 Cory should come back on line on Tu. !! Enjoy

Spring Break!

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!! Last

lecture lecture (Ch 10)

"! Registers
!! Todays

"! Timing
!! Reading

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#! Latch: level-sensitive
clock is low - hold mode clock is high - transparent
D Q Clk Clk D Q
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#! Register: edge-triggered
stores data when clock rises
D Q Clk Clk D Q
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D Q Clk T Clk D tclk-q PWm thold tsetup td-q

Q Delays can be different for rising and falling data transitions

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D Q Clk T Clk D tsetup Q tclk-q Delays can be different for rising and falling data transitions
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thold

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tclk-q,min tsetup, thold

tclk-q

tlogic tlogic,min

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tclk-q tclk-q,min tsetup, thold

tlogic,min

tlogic

Cycle time (max): TClk > tclk-q + tlogic + tsetup Race margin (min): thold < tclk-q,min + tlogic,min
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!! Clock

skew jitter

"! Spatial variation in temporally equivalent clock edges; deterministic + random, tSK
!! Clock

"! Temporal variations in consecutive edges of the clock signal; modulation + random noise "! Cycle-to-cycle (short-term) tJS "! Long term tJL
!! Variation

of the pulse width

"! Important for level sensitive clocking

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Sources of clock uncertainty

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Clk
tSK

Clk

tJS

!! Both

skew and jitter affect the effective cycle time and the race margin

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# of registers Earliest occurrence Latest occurrence of Clk edge of Clk edge Nominal !/2 Nominal + ! /2

Insertion delay Max Clk skew

Clk delay

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Launching edge arrives before the receiving edge

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TCLK - ! CLK1 1 TCLK 3

CLK2

Receiving edge arrives before the launching edge

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tclk-q,min tsetup, thold

tclk-q

tlogic tlogic,min

Minimum cycle time: Tclk + ! = tclk-q + tsetup + tlogic

Worst case is when receiving edge arrives early (negative !)
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tclk-q tclk-q,min tsetup, thold

tlogic,min

tlogic

Hold time constraint: t(clk-q,min) + t(logic,min) > thold + !

Worst case is when receiving edge arrives late Race between data and clock
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tsetup Clk tclk-Q tlogic TCLK

tJS - !

"

Latest point of launching

Earliest arrival of next cycle

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If launching edge is late and receiving edge is early, the data will not be too late if:

tclk-q + tlogic + tsetup < TCLK tJS,1 tJS,2 + !"

Minimum cycle time is determined by the maximum delays through the logic

tclk-q + tlogic + tsetup - ! + 2tJS < TCLK

Skew can be either positive or negative
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Earliest point of launching

Clk tclk-q,min Clk

tlogic,min

thold
Data must not arrive before this time

Nominal clock edge

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If launching edge is early and receiving edge is late:

tclk-q,min + tlogic,min tJS,1 > thold + tJS,2 + !"

Minimum logic delay

tclk-q,min + tlogic,min > thold + 2tJS+ !"

(This assumes jitter at launching and receiving clocks are independent which usually is not true)
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Reference

Pipelined

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(Domino logic almost always uses latch-based clocking)

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!! In

a flip-flop based system:

! And must arrive before next rising edge

"! Data launches on one rising edge "! If data arrives late, system fails
! If it arrives early, wasting time

"! Flip-flops have hard edges

!! In

a latch-based system:
! As long as each loop finished in one cycle

"! Data can pass through latch while it is transparent "! Long cycle of logic can borrow time into next cycle

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!! Flip-flops

generally easier to use

"! Most digital ASICs designed with register-based timing

!! But,

latches (both pulsed and level-sensitive) allow more flexibility

"! And hence can potentially achieve higher performance "! Latches can also be made more tolerant of clock un-certainty "! More in EE241

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!! Make

things cheaper:

"! Want to sell more functions (transistors) per chip for the same money "! Or build same products cheaper "! Price of a transistor has to be reduced
!! But

also want to be faster, smaller, lower power

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!! Benefits

of 30% Dennard scaling (1974):

"! Double transistor density "! Reduce gate delay by 30% (increase operating frequency by 43%) "! Reduce energy per transition by 65% (50% power savings @ 43% increase in frequency)
!! Die

size used to increase by 14% per generation (not any more) !! Technology generation spans 2-3 years
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2X reduction every ~5 years

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tp decreases by 30%/year f increases by 43%

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From Kuroda
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Full Scaling (Constant Electrical Field)

ideal model dimensions and voltages scale together by the same factor S

Fixed Voltage Scaling

most common model until 1990s only dimensions scale, voltages remain constant

General Scaling
most realistic for todays situation voltages and dimensions scale with different factors

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!! W,

L, tox: 1/S !! VDD, VT: 1/S

!! Area:

WL !! Cox: 1/tox !! CL: CoxWL !! ID: Cox(W/L)(VDD-VT)2 !! Req: VDD/IDSAT

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!! W,

L, tox: 1/S !! VDD, VT: 1/S

!! tp:

ReqCL !! Pavg: CLVDD2/tp !! Pavg/A: CoxVDD2/tp

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!! W,

L, tox: 1/S !! VDD, VT: 1/S

!! Area:

WL !! Cox: 1/tox !! CL: CoxWL !! ID: WCoxvsat(VDD-VT-VVSAT/2) !! Req: VDD/IDSAT

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!! W,

L, tox: 1/S !! VDD, VT: 1/S

!! tp:

ReqCL !! Pavg: CLVDD2/tp !! Pavg/A: CoxVDD2/tp

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!! What

will did cause this model to break?

"! Leakage set by kT/q

! Temp. does not scale ! VT set to minimize power

"! Power actually increased

! Leakage increased drastically ! f increased faster than device speed ! Hit cooling limit

"! Process Variation

! Hard to build very small things accurately (less averaging)
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