SN54ABT16821, SN74ABT16821 20-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

SCBS216B JUNE 1992 REVISED JANUARY 1997

D D D D D D D D

Members of the Texas Instruments Widebus Family State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25C Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout High-Drive Outputs (32-mA IOH, 64-mA IOL ) Package Options Include Plastic Thin Shrink Small-Outline (DGG), 300-mil Shrink Small-Outline (DL) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

SN54ABT16821 . . . WD PACKAGE SN74ABT16821 . . . DGG OR DL PACKAGE (TOP VIEW)

description
These 20-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. The ABT16821 can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20 flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs.

1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 1Q7 GND 1Q8 1Q9 1Q10 2Q1 2Q2 2Q3 GND 2Q4 2Q5 2Q6 VCC 2Q7 2Q8 GND 2Q9 2Q10 2OE

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29

1CLK 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 1D7 GND 1D8 1D9 1D10 2D1 2D2 2D3 GND 2D4 2D5 2D6 VCC 2D7 2D8 GND 2D9 2D10 2CLK

A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16821 is characterized for operation over the full military temperature range of 55C to 125C. The SN74ABT16821 is characterized for operation from 40C to 85C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and EPIC-B are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303

Copyright 1997, Texas Instruments Incorporated

DALLAS, TEXAS 75265

SN54ABT16821, SN74ABT16821 20-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

SCBS216B JUNE 1992 REVISED JANUARY 1997

FUNCTION TABLE (each flip-flop) INPUTS OE L L L H CLK L X D H L X X OUTPUT Q H L Q0 Z

logic symbol
1OE 1CLK 2OE 2CLK 1 56 28 29 C3 55 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 30 3D 4 1D 2 2 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 27 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9 1Q10 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9 2Q10 EN2 C1 EN4

1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 1D10 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9 2D10

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SN54ABT16821, SN74ABT16821 20-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

SCBS216B JUNE 1992 REVISED JANUARY 1997

logic diagram (positive logic)

1OE 1

1CLK

56

One of Ten Channels 1D1 55

C1 1D

1Q1

To Nine Other Channels 28

2OE

2CLK

29

One of Ten Channels 42 2D1

C1 1D

15

2Q1

To Nine Other Channels

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . 0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT16821 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT16821 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SN54ABT16821, SN74ABT16821 20-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

SCBS216B JUNE 1992 REVISED JANUARY 1997

recommended operating conditions (see Note 3)

SN54ABT16821 MIN VCC VIH VIL VI IOH IOL t /v Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate Outputs enabled 55 0 4.5 2 0.8 VCC 24 48 10 125 40 0 MAX 5.5 SN74ABT16821 MIN 4.5 2 0.8 VCC 32 64 10 85 MAX 5.5 UNIT V V V V mA mA ns/ V C

TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VCC = 4.5 V, VCC = 4.5 V, VCC = 5 V, VCC = 4 4.5 5V VOL Vhys II IOZH IOZL Ioff ICEX IO ICC VCC = 4 4.5 5V TEST CONDITIONS II = 18 mA IOH = 3 mA IOH = 3 mA IOH = 24 mA IOH = 32 mA IOL = 48 mA IOL = 64 mA 100 VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 0, VCC = 5.5 V, VCC = 5.5 V, VI = VCC or GND VO = 2.7 V VO = 0.5 V VI or VO 4.5 V VO = 5.5 V VO = 2.5 V Outputs high 50 Outputs high 5 5 V, V IO = 0, 0 VCC = 5.5 VI = VCC or GND Outputs low Outputs disabled 100 1 50 50 100 50 200 500 89 500 1.5 3.5 7.5 50 50 200 500 89 500 1.5 50 1 50 50 1 50 50 100 50 200 500 89 500 1.5 MIN 2.5 3 2 2* 0.55 0.55* 0.55 0.55 TA = 25C TYP MAX 1.2 2.5 3 2 2 V mV A A A A A mA A mA A mA pF pF SN54ABT16821 MIN MAX 1.2 2.5 3 V SN74ABT16821 MIN MAX 1.2 UNIT V

VOH

ICC Ci Co

VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V

* On products compliant to MIL-PRF-38535, this parameter does not apply. All typical values are at VCC = 5 V. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SN54ABT16821, SN74ABT16821 20-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

SCBS216B JUNE 1992 REVISED JANUARY 1997

timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V, TA = 25C MIN fclock tw tsu th Clock frequency Pulse duration, CLK high or low Setup time, data before CLK Hold time, data after CLK 0 3.3 1.8 1.3 MAX 150 SN54ABT16821 MIN 0 3.3 1.8 1.3 MAX 150 SN74ABT16821 MIN 0 3.3 1.8 1.3 MAX 150 MHz ns ns ns UNIT

switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25C MIN 150 CLK Q Q Q 1.3 1.6 1.1 1.6 2 1.8 3.7 3.9 3.2 3.8 4.5 4.1 5.1 5.1 4.7 5 5.7 5.8 TYP MAX SN54ABT16821 MIN 150 1.3 1.6 1.1 1.6 2 1.8 6.7 5.8 5.8 5.7 6.6 8.4 MAX SN74ABT16821 MIN 150 1.3 1.6 1.1 1.6 2 1.8 6.1 5.4 5.7 5.6 6.5 7.1 MAX MHz ns ns ns UNIT

OE OE

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SN54ABT16821, SN74ABT16821 20-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

SCBS216B JUNE 1992 REVISED JANUARY 1997

PARAMETER MEASUREMENT INFORMATION

7V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 7V Open

LOAD CIRCUIT 3V Timing Input tw 3V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Data Input tsu 1.5 V th 3V 1.5 V 0V 1.5 V 0V

3V Input 1.5 V tPLH Output 1.5 V 1.5 V 0V tPHL VOH 1.5 V VOL tPHL Output 1.5 V tPLH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS

Output Control tPZL Output Waveform 1 S1 at 7 V (see Note B) Output Waveform 2 S1 at Open (see Note B) tPZH

3V 1.5 V 1.5 V 0V tPLZ 1.5 V tPHZ VOH 0.3 V VOH

3.5 V VOL + 0.3 V VOL

1.5 V

[0V

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TIs standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (CRITICAL APPLICATIONS). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMERS RISK. In order to minimize risks associated with the customers applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TIs publication of information regarding any third partys products or services does not constitute TIs approval, warranty or endorsement thereof.

Copyright 1998, Texas Instruments Incorporated