WIRELESS FLOOD LEVEL MONITOR AND CONTROL

In this project we show that how we monitor and contro the FLOOD LEVEL !sin" RF mod! e techno o"#$$ In this project we not monitor

the e%e o& & ood at the 'oth end '!t at the same time we pro%ide a contro a!tomation in 'oth side$ In this project we !se two circ!it to comp ete the a!tomation$ One circ!it is transmitter end which is &itted at the ri%er end and second is recei%er end which is &itted at the contro room$ In the transmitter and recei%er circ!it $ In the transmitter circ!it we !se One microcontro er with r& transmitter circ!it and at the recei%er end we !se Recei%er mod! e with cd disp a#$

COM(ONENTS )SED TRANSMITTER TRANSMITTER CIRC)IT* IC +,+.T /0 E ENCODER IC$ +11 Mht2 mod! e$ On3o&& switch $e$d 4 56 /,, 7 ohm resistor456$ +8, ohm496 /: 4+6 -%o t 'atter# S)((L; 3 STE( DOWN RECTIFIER (OWER S)((L; <-S50 CONTROLLER =)>>ER N(N TRANSISTOR 4 =C 5+<6 406 (N( TRANSISTOR 4 =C 55<6 406

RECEIVER
COM(ONENTS )SED * STE( DOWN TRANSFORMER 00,??? -?,?- AC DIODE IN +,,8 406 CA(ACITOR /,,, m&d 406 08 p& 406@ /, m&d 4/6 LCD DIS(LA; IC .T /0 D 4 DECODER IC 6 <-S50 MICROCONTROLLER RF RECEIVER +11 Mht2 4/6 CR;STAL /0 Mht2$4/6 L$E$D$ 496 IC 8<,5 REA)LATOR 4/6 SMALL DC ()M( ()S. TO ON SWITC.$ TRANSISTOR =C 55< 406@ =C 55<406 =)>>ER /,: 4/6 +8, O.M 456 /:4+6

CIRC)IT WOR:INA* In the transmitter circ!it we insert one p astic pro'e in the RIVER WATER$ On this p astic pro'e we connect &ew connectin" wires$ We connect &i%e wires$ O!t o& these &i%e wires &o!r wires are connected with the CONTROLLER CIRC)IT and one wire with the common positi%e %o ta"e$ As the water is to 'e raise in the RIVER$ (ositi%e %o ta"e on the 'ottom is a so to 'e trans&er &rom ower point to hi"her point$ Now positi%e %o ta"e &rom the 'ottom is to 'e connected to other point o& the pro'e$ Vo ta"e &rom the pro'e is connected to the ic +,+- heB in%erter ic$ .eB in%erter ic "ets the data &rom pro'e and connected to the and

MICROCONTROLLER direct #$Microcontro er "et the si"na

compare inside$ I& the water e%e is hi"h then p!mp is a!tomatic on$ Microcontro er a!tomatic pro%ide a si"na to the encoder chip direct #$ .ere we !se .T /0 E encoder ic to con%ert the para e data in seria $ O!tp!t o& the .T /0 E is connected to RF transmitter$ .ere we !se +11 Mht2 transmitter to transmit the data in air The TWS-434 and RWS-434 are extremely small, and are excellent for applications requiring short-range RF remote controls. The transmitter module is only !3 the si"e of a standard

postage stamp, and can easily #e placed inside a small plastic enclosure.

TWS-434$ The transmitter output is up to %mW at 433.&'()" *ith a range of approximately 4++ foot ,open area- outdoors. .ndoors, the range is approximately '++ foot, and *ill go through most *alls.....

TWS-434A

The TWS-434 transmitter accepts #oth linear and digital inputs, can operate from ./ to ' 0olts-12, and ma3es #uilding a miniature hand-held RF transmitter 4ery easy. The TWS-434 is approximately the si"e of a standard postage stamp.

TWS-434 Pin Diagram

Sample Transmitter Application Circuit

.n this pro5ect output of the ic 4+4& is connected to the pin no ,',3,4 of the controller.. (icrocontroller is further connected to the )t ' e encoder ic. 6utput from the controller is from , ', 3

'3,'4,'/,'7 to encoder pin no +,

. 8in no ,',3,4,/,7,9,% is the address pin of the encoder ic. .n this pro5ect *e pro4ide a + address to the encoder for transmitter. Same + address is employ in the recei4er circuit . . 8in no 3,/,9,& is the input of the internal in4erter if the ic 4+4& and 8in no ',4,7, + is the output of the internal 4+4& ic. 8in no of the ic 4+4& is connected to the positi4e line and pin no % of the 4+4& is connected to the ground pin. 8in no % of the encoder is connected to the positi4e line and pin no & is connected to the ground pin. 8in no 4 is Transmit ena#le pin and connected to the ground 4oltage.

.n the recei4e circuit first of all *e use one recei4er module to recei4e the data from transmitter. 1ata from the recei4e module is serially output. 6utput from the rf module is connect to the decoder ic. 6utput of the rf module is connected to the pin no 4 of the ic. 8in no pin. We set the to % is address line and connected to the ground same address line of the transmitter and

recei4er. 8in no / and 7 of the ic is connected to the external resistance to pro4ide a oscillation circuit. 6utput from the decoder is connected to the pin no ,',3,4 of the microcontroller directly. 8in no % and & is connected to the

external crystal oscillator o pro4ide a external cloc3 to the circuit.. 8in no 4+ of the controller is connected to the positi4e / 4olt supply. For this positi4e / 4olt supply *e use one step do*n transformer to step do*n the 4oltage from ''+ 4olt ac to & 4olt ac. This ac is further con4erted into dc *ith the help of the full *a4e rectifier circuit. 6utput of the rectifier is further con4erted in

smooth dc *ith the help of the filter capacitor. 6utput of rectifier is further con4erted into smooth dc *ith the help of the 9%+/

regulator. .2 9%+/ regulator pro4ide a regulated / 4olt dc to the circuit. This supply is connected to the pin no % of the decoder ic and pin no 4+ of the controller ic.

:21 1.S8:;< is connected to the pin no 3& to 3' of the controller to display the *ater le4el .

RWS-434$ The recei4er also operates at 433.&'()", and has a sensiti4ity of 3u0. The RWS-434 recei4er operates from 4./ to /./ 4olts-12, and has #oth linear and digital outputs. 2lic3 on picture for larger image

RWS-434 Receiver

RWS-434 Pin Diagram

Sample Receiver Application Circuit

PROGRAM CODE OF THE TRANSMITTER,

sbit l0=P1^0; sbit l1=P1^1; sbit l2=P1^2; sbit l3=P1^3;

sbit moto 1=P2^0; sbit moto 2=P2^1;

sbit !"t"1=P2^2; sbit !"t"2=P2^3; sbit !"t"3=P2^#; sbit !"t"#=P2^$;

%oi! m"i&'( )

*+il,'1( ) i-'l0==1..l1==1..l2==1..l3==1( ) !"t"1=l0; !"t"2=l1; !"t"3=l2; !"t"#=l3; moto 1=1; moto 2=1; / ,ls, i-'l0==1..l1==1..l2==1..l3==0( ) !"t"1=l0; !"t"2=l1; !"t"3=l2; !"t"#=l3; moto 1=1; moto 2=1;

/ ,ls, i-'l0==1..l1==1..l2==0..l3==0( ) !"t"1=l0; !"t"2=l1; !"t"3=l2; !"t"#=l3; moto 1=1; moto 2=1; / ,ls, i-'l0==1..l1==0..l2==0..l3==0( ) !"t"1=l0; !"t"2=l1; !"t"3=l2; !"t"#=l3; moto 1=0; moto 2=1; /

,ls, i-'l0==0..l1==0..l2==0..l3==0( ) !"t"1=l0; !"t"2=l1; !"t"3=l2; !"t"#=l3; moto 1=0; moto 2=0; /

PROGRAM CODE OF THE RECEI0ER1 2i&3l4!,5 ,6$11+7

2!,-i&, l3! P0

sbit s=P2^8; sbit ,&=P2^$; sbit ,=P2^9;

sbit b4::, =P2^0; sbit moto =P2^1;

sbit !"t"1=P1^3; sbit !"t"2=P1^2; sbit !"t"3=P1^1; sbit !"t"#=P1^0;

sbit *t 0=P1^8; sbit *t 1=P1^9; sbit *t 2=P1^$; sbit *t 3=P1^#;

%oi! !,l";'4&si6&,! lo&6 i&t 3o4&t( << F4&3tio& to = o%i!, tim, !,l"; i& ms,31 ) i&t i; -o 'i=0i53o4&t;i>>(; /

%oi! l3!?!"t"'3+" !"t,( ) l3!=!"t,; s=1; ,&=1; !,l";'#0(;

,&=0; !,l";'80(; / %oi! l3!?3m!'3+" 3m!!( ) l3!=3m!!; s=0; ,&=1; !,l";'#0(; ,&=0; !,l";'80(; / %oi! l3!?i&it'( ) l3!?3m!'0@3A(; l3!?3m!'0@01(; l3!?3m!'0@0,(; l3!?3m!'0@A0(; /

) 4&si6&,! 3+" +=0; *+il,'=B+CD=EF0E( ) l3!?!"t"'=B+C(; +>>; / /

%oi! m"i&'( ) ,=0; l3!?i&it'(;

l3!?3m!'0@01(; l3!?3m!'0@A0(; l3!?= i&t'G H"t, I,%,l G(;

*+il,'1( ) i-'*t 0==1..*t 1==1..*t 2==1..*t 3==1( ) l3!?3m!'0@C0(; l3!?= i&t'G Em=t; !"t"1=*t 0; !"t"2=*t 1; !"t"3=*t 2; !"t"#=*t 3; b4::, =1; moto =1; *+il,'*t 0==1..*t 1==1..*t 2==1..*t 3==1(; / ,ls, i-'*t 0==0..*t 1==1..*t 2==1..*t 3==1( ) l3!?3m!'0@C0(; l3!?= i&t'G Io* !"t"1=*t 0; G(; G(;

!"t"2=*t 1; !"t"3=*t 2; !"t"#=*t 3; b4::, =1; moto =1; *+il,'*t 0==0..*t 1==1..*t 2==1..*t 3==1(; / ,ls, i-'*t 0==0..*t 1==0..*t 2==1..*t 3==1( ) l3!?3m!'0@C0(; l3!?= i&t'G M,!i4m !"t"1=*t 0; !"t"2=*t 1; !"t"3=*t 2; !"t"#=*t 3; b4::, =1; moto =1; *+il,'*t 0==0..*t 1==0..*t 2==1..*t 3==1(; / G(;

,ls, i-'*t 0==0..*t 1==0..*t 2==0..*t 3==1( ) l3!?3m!'0@C0(; l3!?= i&t'G Hi6+ !"t"1=*t 0; !"t"2=*t 1; !"t"3=*t 2; !"t"#=*t 3; b4::, =0; moto =1; *+il,'*t 0==0..*t 1==0..*t 2==0..*t 3==1(; / ,ls, i-'*t 0==0..*t 1==0..*t 2==0..*t 3==0( ) l3!?3m!'0@C0(; l3!?= i&t'G Floo! Sit4"tio& !"t"1=*t 0; !"t"2=*t 1; !"t"3=*t 2; G(; G(;

!"t"#=*t 3; b4::, =0; moto =0; /

A 3+it,3t4 ,

Architect!re is m!st to earn 'eca!se 'e&ore earnin" new machine it is necessar# to earn the capa'i ities o& the machine$ This is some thin" i7e 'e&ore earnin" a'o!t the car #o! cannot 'ecome a "ood dri%er$ The architect!re o& the <,5/ is "i%en 'e ow$

The <,5/ doesnCt ha%e an# specia &eat!re than other microcontro er$ The on # &eat!re is that it is eas# to earn$ Architect!re ma7es !s to 7now a'o!t the hardware &eat!res o& the microcontro er$ The &eat!res o& the <,5/ are

+: =#tes o& F ash Memor#

 /0< B <?=it Interna RAM F! # Static Operation* / M.2 to 0+ M.2 10 (ro"ramma' e I3O Lines Two /9?=it Timer3Co!nters SiB Interr!pt So!rces 45 Vectored6 (ro"ramma' e Seria Channe Low (ower Id e and (ower Down Modes

The <,5/ has a <?=it C() that means it is a' e to process < 'it o& data at a time$ <,5/ has 015 instr!ctions$ Some o& the important re"isters and their &!nctions are

N"m, ACC)M)LATOR = (ro"ram Stat!s

F4&3tio& A o"ica D arithmetica

operations Main # !sed in M! tip ication D Di%ision Word :eeps c!rrent stat!s o& AL) (oints the Stac7 Location o& the neBt instr!ction

'PSH( Stac7 (ointer 'SP( (ro"ram Co!nter 4(C6

Data (ointer 'DPTR(

(oints the Location o& the Data

AS per the a#o!t and ' oc7 dia"ram in concern$ We app # a 5?%o t dc power s!pp # to pin no +, o& this ic$ For this 5 %o t re"! ated power s!pp # we !se 8<,5 re"! ate with &! wa%e recti&ier power s!pp # or with the -?%o t dc 'atter#$ I& we !se - %o t dc 'atter# then - %o t dc is &!rther con%erted into 5 %o t dc with the he p o& 8<,5 re"! ator ic$ As per the pin a#o!t and ' oc7 dia"ram in concern$

Reset Circ!itr#*

As soon as #o! "i%e the power s!pp # the <,5/ doesnCt start$ ;o! need to restart &or the microcontro er to start$ Restartin" the microcontro er is nothin" '!t "i%in" a Lo"ic / to the reset pin at east &or the 0 c oc7 p! ses$ So it is "ood to "o &or a sma circ!it which can pro%ide the 0 c oc7 p! ses as soon as the microcontro er is powered$

This is not a 'i" circ!it we are j!st !sin" a capacitor to char"e the microcontro er and a"ain dischar"in" %ia resistor$

Cr#sta s

Cr#sta s pro%ide the s#nchroni2ation o& the interna &!nction and to the periphera s$ Whene%er e%er we are !sin" cr#sta s we need to p!t the capacitor 'ehind it to ma7e it &ree &rom noises$ It is "ood to "o &or a 11p& capacitor$

We can a so resonators instead o& cost # cr#sta which are ow cost and eBterna capacitor can 'e a%oided$

=!t the &reE!enc# o& the resonators %aries a ot$ And it is strict # not ad%ised when !sed &or comm!nications projects$

We wrote a pro"ram in the assem' er so&tware in the comp!ter$$ (ro"ram is written in the assem' # an"!a"e$ A&ter assem' e the so&tware In assem' er &i e stored as a $asm &i e$ Assm' er a!tomatica #

con%ert this asm &i e into heB &i e $ Now this heB &i e is to 'e trans&erred &rom the so&tware to ' an7 ic with the he p o& pro"rammer 7it$ The <,5/ has on # /08 '#tes o& ram$ The enhanced %ersion <,50 e%en has on # 059 '#tes o& ram$ So whi e pro"rammin" microcontro er we sho! d ta7e care a ot in the !sa"e o& the %aria' es$

A %iew o& the C Compi ers a%ai a' e in the mar7et

SDCC F Sma De%ice C Compi er open so!rce Compi er started in India$

RIDE F #et another &amo!s C Compi er '!t ram h!n"r#

.itech F Famo!s in De%$ (IC Micro compi ers

Micro C F Rather new compi er

:ei F Ver# Nice Compi er

.OW TO (ROARAM =LAN: C.I($

<,5/ micro contro er
T+, A0$1 The <,5/ de%e oped and a!nched in the ear # <,Gs@ is one o& the most pop! ar micro contro er in !se toda#$ It has a reasona' # ar"e amo!nt o& '!i t in ROM and RAM$ In addition it has the a'i it# to access eBterna memor#$ The "eneric term G<B5/G is !sed to de&ine the de%ice$ The %a !e o& B de&inin" the 7ind o& ROM@ i$e$ BH,@ indicates none@ BH1@ indicates mas7 ROM@ BH8@ indicates E(ROM and BH- indicates EE(ROM or F ash$

Di--, ,&t mi3 o 3o&t oll, s i& m" J,t1

(IC One o& the &amo!s microcontro ers !sed in the ind!stries$ It is 'ased on RISC Architect!re which ma7es the microcontro er process &aster than other microcontro er$

INTEL These are the &irst to man!&act!re microcontro ers$ These are not as sophisticated other microcontro ers '!t sti the easiest one to earn$ ATMEL Atme Cs AVR microcontro ers are one o& the most power&! in the em'edded ind!str#$ This is the on # microcontro er ha%in" /7' o& ram e%en the entr# sta"e$ =!t it is !n&ort!nate that in India we are !na' e to &ind this 7ind o& microcontro er$

I&t,l A0$1 Inte <,5/ is CISC architect!re which is eas# to pro"ram in assem' # an"!a"e and a so has a "ood s!pport &or .i"h e%e an"!a"es$ The memor# o& the microcontro er can 'e eBtended !p to 9+7$ This microcontro er is one o& the easiest microcontro ers to earn$ The <,5/ microcontro er is in the &ie d &or more than 0, #ears$ There are ots o& 'oo7s and st!d# materia s are readi # a%ai a' e &or <,5/$

First of all we select and open the assembler and wrote a program code in the file. After wrote a software we assemble the software by using internal assembler of the 8051 editor. If there is no error then assembler assemble the software abd 0 error is show the output window.

now assem' er "enerate a ASM &i e and .EI &i e$ This heB &i e is !se&! &or !s to pro"ram the ' an7 chip$ Now we trans&er the heB code into the ' an7 chip with the he p o& seria pro"rammer 7it$ In the pro"rammer we insert a ' an7 chip ,& <-s5/ series $ these chips are m! ti Ftime pro"ramma' e chip$ This pro"rammin" 7it is seperata # a%ai a' e in the mar7et and we trans&er the heB code into ' an7 chip with the he p o& the seria pro"rammer 7it

SE E! SE"#E!$ %IS&'A(
A popular type consists of seven small, bar-shaped LED segment arranged so that depending on which combinations are energized, the numbers 0 to 9 light up All the LED cathodes !or sometimes anodes" are #oined to form a common connection $urrent limiting resistors are re%uired !e g &'0 ohms", preferably one per segment

Anode Conne ction

$ommon cathode method of connecting an array of display elements

Common Cathode

(he main re%uirements for a suitable LED material are)*" &" 0" +t must have on energy gap of appropriate width ,oth - and . types must e/ist, preferably with low resistivities Efficient radioactive pathways must be present

1enerally, energy gaps greater than or e%ual to about & are re%uired

$ommercial LED materials)) 1allium arsenide !1a As" doped with 2i 1allium -hosphide !1a-" doped with . 3 ,i 1allium arsenide -hosphide !1a As*-/ -/" 1allium aluminium arsenide !1a/ Al*-/ As"

IED CONSTRKCTIONSL M
(o reduce reflection losses in LEDs there are two obvious ways) -

a"

b"

(he first is to ensure that most rays stri4e the surface at less than the critical angle (his may be achieved by shaping the semiconductor 5air interface into a hemisphere (he second techni%ue is to encapsulate the #unction in a transparent medium of high refractive inde/ (his is usually a plastic material with refractive inde/ of about * 6 7oulding the plastic into an appro/imately hemispherical shape can minimize the losses at the plastic lair interface

RESISTANCE
8esistance is the opposition of a material to the current +t is measured in 9hms !" All conductors represent a certain amount of resistance, since no conductor is *00: efficient (o control the electron flow !current" in a predictable manner, we use resistors Electronic circuits use calibrated lumped resistance to control the flow of current ,roadly spea4ing, resistor can be divided into two groups viz fi/ed 3 ad#ustable !variable" resistors +n fi/ed resistors, the value is fi/ed 3 cannot be varied +n variable resistors, the resistance value can be varied by an ad#uster 4nob +t can be divided into !a" $arbon composition !b" ;ire wound !c" 2pecial type (he most common type of resistors used in our pro#ects is carbon type (he resistance value is normally indicated by colour bands Each resistance has four colours, one of the band on either side will be gold or silver, this is called fourth band and indicates the tolerance, others three band will give the value of resistance !see table" <or e/ample if a resistor has the following mar4ing on it say red, violet, gold $omparing these coloured rings with the colour code, its value is &'000 ohms or &' 4ilo ohms and its tolerance is =6: 8esistor comes in various sizes !-ower rating" (he bigger, the size, the more power rating of *5> watts (he four colour rings on its body tells us the value of resistor value as given below COLOURS CODE ,lac4--------------------------------------------0 ,rown-------------------------------------------* 8ed----------------------------------------------& 9range-----------------------------------------0 ?ellow------------------------------------------> 1reen-------------------------------------------6 ,lue---------------------------------------------@ Aiolet--------------------------------------------' 1rey---------------------------------------------B ;hite--------------------------------------------9

(he first rings give the first digit (he second ring gives the second digit (he third ring indicates the number of zeroes to be placed after the digits (he fourth ring gives tolerance !gold =6:, silver = *0:, .o colour = &0:" +n variable resistors, we have the dial type of resistance bo/es (here is a 4nob with a metal pointer (his presses over brass pieces placed along a circle with some space b5w each of them 8esistance coils of different values are connected b5w the gaps ;hen the 4nob is rotated, the pointer also moves over the brass pieces +f a gap is s4ipped over, its resistance is included in the circuit +f two gaps are s4ipped over, the resistances of both together are included in the circuit and so on A dial type of resistance bo/ contains many dials depending upon the range, which it has to cover +f a resistance bo/ has to read upto *0,000, it will have three dials each having ten gaps i e ten resistance coils each of resistance *0 (he third dial will have ten resistances each of *00 (he dial type of resistance bo/es is better because the contact resistance in this case is small 3 constant

LIGHT EMITTING DIODE

Light emitting diode !LED" is basically a --. #unction semiconductor diode particularly designed to emit visible light (here are infrared emitting LEDs which emit invisible light (he LEDs are now available in many colours red, green and yellow A normal LED emits at & >A and consumes 7A of current (he LEDs are made in the form of flat tiny --. #unction enclosed in a semispherical dome made up of clear coloured epo/y resin (he dome of a LED acts as a lens and diffuser of light (he diameter of the base is less than a %uarter of an inch (he actual diameter varies somewhat with different ma4es (he common circuit symbols for the LED are shown in <ig +t is similar to the conventional rectifier diode symbol with two arrows pointing out (here are two leadsone for anode and the other for cathode LEDs often have leads of dissimilar length and the shorter one is the cathode All manufacturers do not strictly adhere this to 2ometimes the cathode side has a flat base +f there is doubt, the polarity of the diode should be identified A simple bench method is to use the ohmmeter incorporating 0-volt cells for ohmmeter function ;hen connected with the ohmmeter) one way there will be no deflection and when connected the other way round there will be a large deflection of a pointer ;hen this occurs the anode lead is connected to the negative of test lead and cathode to the positive test lead of the ohmmeter

+f low range !8/l" of the ohmmeter is used the LED would light up in most cases because the low range of ohmmeter can pass sufficient current to light up the LED Another safe method is to connect the test circuit shown in <ig & Cse any two dry cells in series with a current limiting resistor of @B to *00 ohms (he resistor limits the forward diode current of the LED under test to a safe value ;hen the LED under test is connected to the test terminals in any way) if it does not light up, reverse the test leads (he LED will now light up (he anode of the LED is that which is connected to the DAE terminal !positive pole of the battery" (his method is safe, as reverse voltage can never e/ceed 0 volts in this test

EIECTRICAI CHARACTERISTICS OF IEDSL M

Electrically, a LED is similar to the conventional diode in that it has relatively low forward voltage threshold 9nce this is e/ceeded the #unction has a low slope resistance and conducts current readily An e/ternal resistor must limit this current <orward voltage drew across red LED is nominally * @ A but spread with commercial diodes, it may be as high as & volts or so, while the 1reen LED drops & >A (his difference accounts for use of lower limiting resistor used with the 1reen LED Another important parameter of the LED is its ma/imum reverse voltage rating <or typical 8ed device it is of the order of 0 volts ,ut for 1reen LED it is somewhat higher- 6 to *0 volts (he LED produces light only when a d c current is passed in the forward direction and the amount of light emitted by a LED is proportional to the forward current over a broad range +t means that light intensity increases in an appro/imately linear manner with increasing current

SE0EN SEGMENT DISPIAN DECIMAI DISPIANLM

A popular type consists of seven small, bar-shaped LED segment arranged so that depending on which combinations are energized, the numbers 0 to 9 light up All the LED cathodes !or

sometimes anodes" are #oined to form a common connection $urrent limiting resistors are re%uired !e g &'0 ohms", preferably one per segment $ommon cathode method of connecting an array of display elements

Anode Conne ction

Common Cathode (he main re%uirements for a suitable LED material are)-

*" &" 0"

+t must have on energy gap of appropriate width ,oth - and . types must e/ist, preferably with low resistivities Efficient radioactive pathways must be present

1enerally, energy gaps greater than or e%ual to about & are re%uired $ommercial LED materials)) 1allium arsenide !1a As" doped with 2i 1allium -hosphide !1a-" doped with . 3 ,i 1allium arsenide -hosphide !1a As*-/ -/" 1allium aluminium arsenide !1a/ Al*-/ As"

IED CONSTRKCTIONSL M

(o reduce reflection losses in LEDs there are two obvious ways) a" (he first is to ensure that most rays stri4e the surface at less than the critical angle (his may be achieved by shaping the semiconductor 5air interface into a hemisphere (he second techni%ue is to encapsulate the #unction in a transparent medium of high refractive inde/ (his is usually a plastic material with refractive inde/ of about * 6 7oulding the plastic into an appro/imately hemispherical shape can minimize the losses at the plastic lair interface

b"

POHER SKPPIN
.n alternating current the electron flo* is alternate, i.e. the electron flo* increases to maximum in one direction, decreases #ac3 to "ero. .t then increases in the other direction and then

decreases to "ero again. 1irect current flo*s in one direction only. Rectifier con4erts alternating current to flo* in one direction only. When the anode of the diode is positi4e *ith respect to its cathode, it is for*ard #iased, allo*ing current to flo*. =ut *hen its anode is negati4e *ith respect to the cathode, it is re4erse #iased and does not allo* current to flo*. This unidirectional property of the diode is useful for rectification. ; single diode arranged #ac3-to-#ac3 might allo* the electrons to flo* during positi4e half cycles only and suppress the negati4e half cycles. 1ou#le diodes arranged #ac3to-#ac3 might act as full *a4e rectifiers as they may allo* the electron flo* during #oth positi4e and negati4e half cycles. Four diodes can #e arranged to ma3e a full *a4e #ridge rectifier. 1ifferent types of filter circuits are used to smooth out the pulsations in amplitude of the output 4oltage from a rectifier. The property of capacitor to oppose any change in the 4oltage applied across them #y storing energy in the electric field of the capacitor and of inductors to oppose any change in the current flo*ing through them #y storing energy in the magnetic field of coil may #e utili"ed. To remo4e pulsation of the direct current o#tained from the rectifier, different types of com#ination of capacitor, inductors and resistors may #e also #e used to increase to action of filtering.

NEED OF POHER SKPPIN

8erhaps all of you are a*are that a >po*er supply? is a primary requirement for the >Test =ench? of a home experimenter?s mini la#. ; #attery eliminator can eliminate or replace the #atteries of solid-state electronic equipment and the equipment thus can #e operated #y '3+4 ;.2. mains instead of the #atteries or dry cells. @o*adays, the use of commercial #attery eliminator or po*er supply unit has #ecome increasingly popular as po*er source for household appliances li3e trans recei4ers, record player, cassette players, digital cloc3 etc.

THEORY

USE OF DIODES IN RECTIFIERS:

Alectric energy is a4aila#le in homes and industries in .ndia, in the form of alternating 4oltage. The supply has a 4oltage of ''+0 ,rms- at a frequency of /+ )". .n the BS;, it is +0 at 7+ )". For the operation of most of the de4ices in electronic equipment, a dc 4oltage is needed. For instance, a transistor radio requires a dc supply for its operation. Bsually, this supply is pro4ided #y dry cells. =ut sometime *e use a #attery eliminator in place of dry cells. The #attery eliminator con4erts the ac 4oltage into dc 4oltage and thus eliminates the need for dry cells. @o*adays, almost all-electronic equipment includes a circuit that con4erts ac 4oltage of mains supply into dc 4oltage. This part of the equipment is called 8o*er Supply. .n general, at the input of the po*er supply, there is a po*er transformer. .t is follo*ed #y a diode circuit called Rectifier. The output of the rectifier goes to a smoothing filter, and then to a 4oltage regulator circuit. The rectifier circuit is the heart of a po*er supply.

RECTIFICATION
Rectification is a process of rendering an alternating current or 4oltage into a unidirectional one. The component used for rectification is called >Rectifier?. ; rectifier permits current to flo* only during the positi4e half cycles of the applied ;2 4oltage #y eliminating the negati4e half cycles or alternations of the applied

;2 4oltage. Thus pulsating 12 is o#tained. To o#tain smooth 12 po*er, additional filter circuits are required. ; diode can #e used as rectifier. There are 4arious types of diodes. =ut, semiconductor diodes are 4ery popularly used as rectifiers. ; semiconductor diode is a solid-state de4ice consisting of t*o elements is #eing an electron emitter or cathode, the other an electron collector or anode. Since electrons in a semiconductor diode can flo* in one direction only-from emitter to collector- the diode pro4ides the unilateral conduction necessary for rectification. 6ut of the semiconductor diodes, copper oxide and selenium rectifier are also commonly used.
FULL WAVE RECTIFIER

.t is possi#le to rectify #oth alternations of the input 4oltage #y using t*o diodes in the circuit arrangement. ;ssume 7.3 0 rms , % 0 p-p- is applied to the circuit. ;ssume further that t*o equal4alued series-connected resistors R are placed in parallel *ith the ac source. The % 0 p-p appears across the t*o resistors connected #et*een points ;2 and 2=, and point 2 is the electrical midpoint #et*een ; and =. )ence & 0 p-p appears across each resistor. ;t any moment during a cycle of 4 in, if point ; is positi4e relati4e to 2, point = is negati4e relati4e to 2. When ; is negati4e to 2, point = is positi4e relati4e to 2. The effecti4e 4oltage in proper time phase *hich each diode CseesC is in Fig. The 4oltage applied to the anode of each diode is equal #ut opposite in polarity at any gi4en instant. When ; is positi4e relati4e to 2, the anode of 1 is positi4e *ith respect to its cathode. )ence 1 *ill conduct #ut 1' *ill not. 1uring the second alternation, = is positi4e relati4e to 2. The anode of 1' is therefore positi4e *ith respect to its cathode, and 1' conducts *hile 1 is cut off. There is conduction then #y either 1 or 1' during the entire input-4oltage cycle. Since the t*o diodes ha4e a common-cathode load resistor R:, the output 4oltage across R : *ill result from the alternate

conduction of 1 and 1'. The output *a4eform 4out across R:, therefore has no gaps as in the case of the half-*a4e rectifier. The output of a full-*a4e rectifier is also pulsating direct current. .n the diagram, the t*o equal resistors R across the input 4oltage are necessary to pro4ide a 4oltage midpoint 2 for circuit connection and "ero reference. @ote that the load resistor R : is connected from the cathodes to this center reference point 2. ;n interesting fact a#out the output *a4eform 4 out is that its pea3 amplitude is not & 0 as in the case of the half-*a4e rectifier using the same po*er source, #ut is less than 4D 0. The reason, of course, is that the pea3 positi4e 4oltage of ; relati4e to 2 is 4D 0, not & 0, and part of the 4D 0 is lost across R. Though the full *a4e rectifier fills in the conduction gaps, it deli4ers less than half the pea3 output 4oltage that results from half-*a4e rectification.
BRIDGE RECTIFIER

; more *idely used full-*a4e rectifier circuit is the #ridge rectifier. .t requires four diodes instead of t*o, #ut a4oids the need for a centre-tapped transformer. 1uring the positi4e half-cycle of the secondary 4oltage, diodes 1' and 14 are conducting and diodes 1 and 13 are non-conducting. Therefore, current flo*s through the secondary *inding, diode 1', load resistor R: and diode 14. 1uring negati4e half-cycles of the secondary 4oltage, diodes 1 and 13 conduct, and the diodes 1' and 14 do not conduct. The current therefore flo*s through the secondary *inding, diode 1 , load resistor R: and diode 13. .n #oth cases, the current passes through the load resistor in the same direction. Therefore, a fluctuating, unidirectional 4oltage is de4eloped across the load.

Filt "tio&
The rectifier circuits *e ha4e discussed a#o4e deli4er an output 4oltage that al*ays has the same polarity$ #ut ho*e4er, this output is not suita#le as 12 po*er supply for solid-state circuits. This is due to the pulsation or ripples of the output 4oltage. This

should #e remo4ed out #efore the output 4oltage can #e supplied to any circuit. This smoothing is done #y incorporating filter net*or3s. The filter net*or3 consists of inductors and capacitors. The inductors or cho3e coils are generally connected in series *ith the rectifier output and the load. The inductors oppose any change in the magnitude of a current flo*ing through them #y storing up energy in a magnetic field. ;n inductor offers 4ery lo* resistance for 12 *hereasE it offers 4ery high resistance to ;2. Thus, a series connected cho3e coil in a rectifier circuit helps to reduce the pulsations or ripples to a great extent in the output 4oltage. The fitter capacitors are usually connected in parallel *ith the rectifier output and the load. ;s, ;2 can pass through a capacitor #ut 12 cannot, the ripples are thus limited and the output #ecomes smoothed. When the 4oltage across its plates tends to rise, it stores up energy #ac3 into 4oltage and current. Thus, the fluctuations in the output 4oltage are reduced considera#le. Filter net*or3 circuits may #e of t*o types in general$

CHOKE INPUT FILTER

.f a cho3e coil or an inductor is used as the >firstcomponents? in the filter net*or3, the filter is called >cho3e input filter?. The 1.2. along *ith ;2 pulsation from the rectifier circuit at first passes through the cho3e ,:-. .t opposes the ;2 pulsations #ut allo*s the 12 to pass through it freely. Thus ;2 pulsations are largely reduced. The further ripples are #y passed through the parallel capacitor 2. =ut, ho*e4er, a little nipple remains unaffected, *hich are considered negligi#le. This little ripple may #e reduced #y incorporating a series a cho3e input filters.
CAPACITOR INPUT FILTER

.f a capacitor is placed #efore the inductors of a cho3e-input filter net*or3, the filter is called capacitor input filter. The 1.2. along *ith ;2 ripples from the rectifier circuit starts charging the capacitor 2. to a#out pea3 4alue. The ;2 ripples are then diminished slightly. @o* the capacitor 2, discharges through the inductor or cho3e coil, *hich opposes the ;2 ripples, except the 12. The second capacitor 2 #y passes the further ;2 ripples. ; small ripple is still present in the output of 12, *hich may #e reduced #y adding additional filter net*or3 in series.

TRANSFORMER
PRINCIPLE OF THE TRANSFORMER:T*o coils are *ound o4er a 2ore such that they are magnetically coupled. The t*o coils are 3no*n as the primary and secondary *indings. In a Transformer, an iron core is used. The coupling #et*een the coils is source of ma3ing a path for the magnetic flux to lin3 #oth the coils. ; core as in fig.' is used and the coils are *ound on the lim#s of the core. =ecause of high permea#ility of iron, the flux path for the flux is only in the iron and hence the flux lin3s #oth *indings. )ence there is 4ery little >lea3age flux?. This term lea3age flux denotes the part of the flux, *hich does not lin3 #oth the coils, i.e., *hen coupling is not perfect. .n the high frequency transformers, ferrite core is used. The transformers may #e step-up, step-do*n, frequency matching, sound output, amplifier dri4er etc. The #asic principles of all the transformers are same.

MINIATURE TRANSFORMER

CONVENTIONAL POWER TRANSFORMER

MICROCONTROIIER ATAOC$1
A 3+it,3t4 , o- A0$1 -"mil;LM

The &i"!re F / a'o%e shows the 'asic architect!re o& <,5/ &ami # o& microcontro er$
Fea !res
J Compati' e with MCS?5/K (rod!cts J +: =#tes o& In?S#stem Repro"ramma' e F ash Memor# F End!rance* /@,,, Write3Erase C#c es J F! # Static Operation* , .2 to 0+ M.2 J Three?Le%e (ro"ram Memor# Loc7 J /0< B <?=it Interna RAM J 10 (ro"ramma' e I3O Lines J Two /9?=it Timer3Co!nters J SiB Interr!pt So!rces J (ro"ramma' e Seria Channe J Low (ower Id e and (ower Down Modes

Des"r#$ #on
The AT<-C5/ is a ow?power@ hi"h?per&ormance CMOS <?'it microcomp!ter with +: '#tes o& F ash (ro"ramma' e and Erasa' e Read On # Memor# 4(EROM6$ The de%ice is man!&act!red !sin" Atme Cs hi"h densit# non%o ati e memor# techno o"# and is compati' e with the ind!str# standard MCS?5/K instr!ction set and pino!t$

The on?chip F ash a ows the pro"ram memor# to 'e repro"rammed in?s#stem or '# a con%entiona non%o ati e memor# pro"rammer$ =# com'inin" a %ersati e <?'it C() with F ash on a mono ithic chip@ the Atme AT<-C5/ is a power&! microcomp!ter which pro%ides a hi"h # & eBi' e and cost e&&ecti%e so !tion to man# em'edded contro app ications$ The AT<-C5/ pro%ides the &o owin" standard &eat!res* +: '#tes o& F ash@ /0< '#tes o& RAM@ 10 I3O ines@ two /9?'it timer3co!nters@ &i%e %ector two? e%e interr!pt architect!re@ a &! d!p eB seria port@ and on?chip osci ator and c oc7 circ!itr#$ In addition@ the AT<-C5/ is desi"ned with static o"ic &or operation down to 2ero &reE!enc# and s!pports two so&tware se ecta' e power sa%in" modes$ The Id e Mode stops the C() whi e a owin" the RAM@ timer3co!nters@ seria port and interr!pt s#stem to contin!e &!nctionin"$ The (ower down Mode sa%es the RAM contents '!t &ree2es the osci ator disa' in" a other chip &!nctions !nti the neBt hardware reset$ Pi& D,s3 i=tio& 0CC S!pp # %o ta"e$ GND Aro!nd$ Po t 0 (ort , is an <?'it open drain 'idirectiona I3O port$ As an o!tp!t port each pin can sin7 ei"ht TTL inp!ts$ When /s are written to port , pins@ the pins can 'e !sed as hi"h impedance inp!ts$ (ort , ma# a so 'e con&i"!red to 'e the m! tip eBed ow order address3data '!s d!rin" accesses to eBterna pro"ram and data memor#$ In this mode (, has interna p! ?!ps$ (ort , a so recei%es the code '#tes d!rin" F ash pro"rammin"@ and o!tp!ts the code '#tes d!rin" pro"ram %eri&ication$ EBterna p! ?!ps are reE!ired d!rin" pro"ram %eri&ication$ Po t 1 (ort / is an <?'it 'idirectiona I3O port with interna p! ?!ps$ The (ort / o!tp!t '!&&ers can sin73so!rce &o!r TTL inp!ts$ When /s are written to (ort / pins the# are p! ed hi"h '# the interna p! ?!ps and can 'e !sed as inp!ts$ As inp!ts@ (ort / pins that are eBterna # 'ein" p! ed ow wi so!rce c!rrent 4IIL6 'eca!se o& the interna p! ?!ps$ (ort / a so recei%es the ow?order address '#tes d!rin" F ash pro"rammin" and %eri&ication$

Po t 2 (ort 0 is an <?'it 'idirectiona I3O port with interna p! ?!ps$ The (ort 0 o!tp!t '!&&ers can sin73so!rce &o!r TTL inp!ts$ When /s are written to (ort 0 pins the# are p! ed hi"h '# the interna p! ?!ps and can 'e !sed as inp!ts$ As inp!ts@ (ort 0 pins that are eBterna # 'ein" p! ed ow wi so!rce c!rrent 4IIL6 'eca!se o& the interna p! ?!ps$ (ort 0 emits the hi"h?order address '#te d!rin" &etches &rom eBterna pro"ram memor# and d!rin" accesses to eBterna data memor# that !ses /9?'it addresses 4MOVI L D(TR6$ In this app ication it !ses stron" interna p! ?!ps when emittin" /s$ D!rin" accesses to eBterna data memor# that !ses <?'it addresses 4MOVI L RI6M (ort 0 emits the contents o& the (0 Specia F!nction Re"ister$ (ort 0 a so recei%es the hi"h?order address 'its and some contro si"na s d!rin" F ash pro"rammin" and %eri&ication$ Po t 3 (ort 1 is an <?'it 'idirectiona I3O port with interna p! ?!ps$ The (ort 1 o!tp!t '!&&ers can sin73so!rce &o!r TTL inp!ts$ When /s are written to (ort 1 pins the# are p! ed hi"h '# the interna p! ?!ps and can 'e !sed as inp!ts$ As inp!ts@ (ort 1 pins that are eBterna # 'ein" p! ed ow wi so!rce c!rrent 4IIL6 'eca!se o& the p! ?!ps$ (ort 1 a so ser%es the &!nctions o& %ario!s specia &eat!res o& the AT<-C5/ as isted 'e ow* (ort 1 a so recei%es some contro si"na s &or F ash pro"rammin" and %eri&ication$ RST Reset inp!t$ A hi"h on this pin &or two machine c#c es whi e the osci ator is r!nnin" resets the de%ice$ AIE<PROG Address Latch Ena' e o!tp!t p! se &or atchin" the ow '#te o& the address d!rin" accesses to eBterna memor#$ This pin is a so the pro"ram p! se inp!t 4(ROA6 d!rin" F ash pro"rammin"$ In norma operation ALE is emitted at a constant rate o& /39 the osci ator &reE!enc#@ and ma# 'e !sed &or eBterna timin" or c oc7in" p!rposes$ Note@ howe%er@ that one ALE p! se is s7ipped d!rin" each access to eBterna Data Memor#$ I& desired@ ALE operation can 'e disa' ed '# settin" 'it , o& SFR ocation <E.$ With

the 'it set@ ALE is acti%e on # d!rin" a MOVI or MOVC instr!ction$ Otherwise@ the pin is wea7 # p! ed hi"h$ Settin" the ALE?disa' e 'it has no e&&ect i& the microcontro er is in eBterna eBec!tion mode$ PSEN (ro"ram Store Ena' e is the read stro'e to eBterna pro"ram memor#$ Po t Pi& Alt, &"t, F4&3tio&s (1$, RID 4seria inp!t port6 (1$/ TID 4seria o!tp!t port6 (1$0 INT, 4eBterna interr!pt ,6 (1$1 INT/ 4eBterna interr!pt /6 (1$+ T, 4timer , eBterna inp!t6 (1$5 T/ 4timer / eBterna inp!t6 (1$9 WR 4eBterna data memor# write stro'e6 (1$8 RD 4eBterna data memor# read stro'e6 When the AT<-C5/ is eBec!tin" code &rom eBterna pro"ram memor#@ (SEN is acti%ated twice each machine c#c e@ eBcept that two (SEN acti%ations are s7ipped d!rin" each access to eBterna data memor#$ EA<0PP EBterna Access Ena' e$ EA m!st 'e strapped to AND in order to ena' e the de%ice to &etch code &rom eBterna pro"ram memor# ocations startin" at ,,,,. !p to FFFF.$ Note@ howe%er@ that i& oc7 'it / is pro"rammed@ EA wi 'e interna # atched on reset$ EA sho! d 'e strapped to VCC &or interna pro"ram eBec!tions$ This pin a so recei%es the /0?%o t pro"rammin" ena' e %o ta"e 4V((6 d!rin" F ash pro"rammin"@ &or parts that reE!ire /0?%o t V(($ PTAI1 Inp!t to the in%ertin" osci ator amp i&ier and inp!t to the interna c oc7 operatin" circ!it$ PTAI2

O!tp!t &rom the in%ertin" osci ator amp i&ier$ Os3ill"to C+" "3t, isti3s ITAL/ and ITAL0 are the inp!t and o!tp!t@ respecti%e #@ o& an in%ertin" amp i&ier which can 'e con&i"!red &or !se as an on?chip osci ator@ as shown in Fi"!re /$ Either a E!art2 cr#sta or ceramic resonator ma# 'e !sed$ To dri%e the de%ice &rom an eBterna c oc7 so!rce@ ITAL0 sho! d 'e e&t !nconnected whi e ITAL/ is dri%en as shown in Fi"!re 0$There are no reE!irements on the d!t# c#c e o& the eBterna c oc7 si"na @ since the inp!t to the interna c oc7in" circ!itr# is thro!"h a di%ide?'#?two & ip?& op@ '!t minim!m and maBim!m %o ta"e hi"h and ow time speci&ications m!st 'e o'ser%ed$ I!l, Mo!, In id e mode@ the C() p!ts itse & to s eep whi e a the on chip periphera s remain acti%e$ The mode is in%o7ed '# so&tware$ The content o& the on?chip RAM and a the specia &!nctions re"isters remain !nchan"ed d!rin" this mode$ The id e mode can 'e terminated '# an# ena' ed Interr!pt or '# hardware reset$ It sho! d 'e noted that when id e is terminated '# a hard .ardware reset@ the de%ice norma # res!mes pro"ram eBec!tion@ &rom where it e&t o&&@ !p to two machine c#c es 'e&ore the interna reset a "orithm ta7es contro $ On? chip hardware inhi'its access to interna RAM in this e%ent@ '!t access to the port pins is not inhi'ited$ To e iminate the possi'i it# o& an !neBpected write to a port pin when Id e is terminated '# reset@ the instr!ction &o owin" the one that in%o7es Id e sho! d not 'e one that writes to a port pin or to eBterna memor#$ St"t4s o- E@t, &"l Pi&s !4 i&6 I!l, "&! Po*, !o*& Mo!,s Mo!, P o6 "m M,mo ; AIE PSEN PORT0 PORT1 PORT2 PORT3 Id e Interna / Data Id e EBterna / F oat Data Address Data (ower down Interna , Data (ower down EBterna , F oat Data Po*, !o*& Mo!,

In the power down mode the osci ator is stopped@ and the instr!ction that in%o7es power down is the ast instr!ction eBec!ted$ The on?chip RAM and Specia F!nction Re"isters retain their %a !es !nti the power down mode is terminated$ The on # eBit &rom power down is a hardware reset$ Reset rede&ines the SFRs '!t does not chan"e the on?chip RAM$ The reset sho! d not 'e acti%ated 'e&ore VCC is restored to its norma operatin" e%e and m!st 'e he d acti%e on" eno!"h to a ow the osci ator to restart and sta'i i2e$ P o6 "m M,mo ; Io3J Qits On the chip are three oc7 'its which can 'e e&t !n?pro"rammed 4)6 or can 'e pro"rammed 4(6 to o'tain the additiona &eat!res isted in the ta' e 'e ow* When oc7 'it / is pro"rammed@ the o"ic e%e at the EA pin is samp ed and atched d!rin" reset$ I& the de%ice is powered !p witho!t a reset@ the atch initia i2es to a random %a !e@ and ho ds that %a !e !nti reset is acti%ated$ It is necessar# that the atched %a !e o& EA 'e in a"reement with The c!rrent o"ic e%e at that pin in order &or the de%ice to &!nction proper #$ Io3J Qit P ot,3tio& Mo!,s P o6 "m Io3J Qits P ot,3tio& T;=, IQ1 IQ2 IQ3 / ) No pro"ram oc7 &eat!res$ 0 ( ) MOVC instr!ctions eBec!ted &rom eBterna pro"ram memor# are disa' ed &rom &etchin" code =#tes &rom interna memor#@ EA is samp ed and atched on reset@ and &!rther pro"rammin" o& the F ash is disa' ed$ 1 ( ) Same as mode 0@ a so %eri&# is disa' ed$ + ( same as mode 1@ a so eBterna eBec!tion is disa' ed$ P o6 "mmi&6 t+, Fl"s+ The AT<-C5/ is norma # shipped with the on?chip F ash memor# arra# in the erased state 4that is@ contents H FF.6 and read# to 'e pro"rammed$ The pro"rammin" inter&ace accepts either a hi"h?%o ta"e 4/0?%o t6 or a ow?%o ta"e 4VCC6 pro"ram ena' e si"na $ The ow %o ta"e pro"rammin" mode pro%ides a con%enient wa# to

pro"ram the AT<-C5/ inside the !serCs s#stem@ whi e the hi"h?%o ta"e pro"rammin" mode is compati' e with con%entiona third part# F ash or E(ROM pro"rammers$ The AT<-C5/ is shipped with either the hi"h?%o ta"e or ow?%o ta"e pro"rammin" mode ena' ed$ The respecti%e top?side mar7in" and de%ice si"nat!re codes are isted in the &o owin" ta' e$ The AT<-C5/ code memor# arra# is pro"rammed '#te?'# '#te In either pro"rammin" mode$ To pro"ram an# non' an7 '#te in the on?chip F ash Memor#@ the entire memor# m!st 'e erased !sin" the Chip Erase Mode$ P o6 "mmi&6 Al6o it+mL =e&ore pro"rammin" the AT<-C5/@ the address@ data and contro si"na s sho! d 'e set !p accordin" to the F ash pro"rammin" mode ta' e and Fi"!res 1 and +$ To pro"ram the AT<-C5/@ ta7e the &o owin" steps$ /$ Inp!t the desired memor# ocation on the address ines$ 0$ Inp!t the appropriate data '#te on the data ines$ 1$ Acti%ate the correct com'ination o& contro si"na s$ +$ Raise EA3V(( to /0V &or the hi"h?%o ta"e pro"rammin" mode$ 5$ (! se ALE3(ROA once to pro"ram a '#te in the F ash arra# or the oc7 'its$ The '#te?write c#c e is se &?timed and t#pica # ta7es no more than /$5 ms$ Repeat steps / thro!"h 5@ chan"in" the address and data &or the entire arra# or !nti the end o& the o'ject &i e is reached$ D"t" Polli&6L The AT<-C5/ &eat!res Data (o in" to indicate the end o& a write c#c e$ D!rin" a write c#c e@ an attempted read o& the ast '#te written wi res! t in the comp ement o& the written dat!m on (O$8$ Once the write c#c e has 'een comp eted@ tr!e data are %a id on a o!tp!ts@ and the neBt c#c e ma# 'e"in$ Data (o in" ma# 'e"in an# time a&ter a write c#c e has 'een initiated$ R,"!;<Q4s;L The pro"ress o& '#te pro"rammin" can a so 'e monitored '# the RD;3=S; o!tp!t si"na $ (1$+ is p! ed ow a&ter ALE "oes hi"h d!rin" pro"rammin" to indicate =)S;$ (1$+ is p! ed hi"h a"ain when pro"rammin" is done to indicate READ;$ P o6 "m 0, i-;L

I& oc7 'its L=/ and L=0 ha%e not 'een pro"rammed@ the pro"rammed code data can 'e read 'ac7 %ia the address and data ines &or %eri&ication$ The oc7 'its cannot 'e %eri&ied direct #$ Veri&ication o& the oc7 'its is achie%ed '# o'ser%in" that their &eat!res are ena' ed$ C+i= E "s,L The entire F ash arra# is erased e ectrica # '# !sin" the proper com'ination o& contro si"na s and '# ho din" ALE3(ROA ow &or /, ms$ The code arra# is written with a N/Os$ The chip erase operation m!st 'e eBec!ted 'e&ore the code memor# can 'e re?pro"rammed$ R,"!i&6 t+, Si6&"t4 , Q;t,sL The si"nat!re '#tes are read '# the same proced!re as a norma %eri&ication o& ocations ,1,.@ ,1/.@ and ,10.@ eBcept that (1$9 and (1$8 m!st 'e p! ed to a o"ic ow$ The %a !es ret!rned are as &o ows$ 4,1,.6 H /E. indicates man!&act!red '# Atme 4,1/.6 H 5/. indicates <-C5/ 4,10.6 H FF. indicates /0V pro"rammin" 4,10.6 H ,5. indicates 5V pro"rammin" P o6 "mmi&6 I&t, -"3, E%er# code '#te in the F ash arra# can 'e written and the entire arra# can 'e erased '# !sin" the appropriate com'ination o& contro si"na s$ The write operation c#c e is se & timed and once initiated@ wi a!tomatica # time itse & to comp etion$ A major pro"rammin" %endors o&&er wor dwide s!pport &or the Atme microcontro er series$ ( ease contact #o!r oca pro"rammin" %endor &or the appropriate so&tware re%ision$ Fl"s+ P o6 "mmi&6 Mo!,s Note* /$ Chip Erase reE!ires a /,?ms (ROA p! se$

SPECIAI FKNCTION REGISTER 'SFR( ADDRESSESL ACC ACC)M)LATOR ,E,.

= (SW S( D(TR D(L D(. (, (/ (0 (1 TMOD TCON T., TLO T./ TL/ SCON S=)F (CON

= REAISTER (ROARAM STAT)S WORD STAC: (OINTER DATA (OINTER 0 =;TES LOW =;TE OF D(TR .IA. =;TE OF D(TR (ORT, (ORT/ (ORT0 (ORT1 TIMER3CO)NTER MODE CONTROL TIMER CO)NTER CONTROL TIMER , .IA. =;TE TIMER , LOW =;TE TIMER / .IA. =;TE TIMER / LOW =;TE SERIAL CONTROL SERIAL DATA =)FFER (OWER CONTROL

,F,. ,D,. </. <0. <1. <,. -,. ,A,. ,=,. <-. <<. <C. <A. <D. <=. -<. --. <8.

TMOD 4TIMER MODE6 REAISTER

=oth timers are the <-c5/ share the one re"ister TMOD$ + LS= 'it &or the timer , and + MS= &or the timer /$ In each case ower 0 'its set the mode o& the timer )pper two 'its set the operations$ AATE* Aatin" contro when set$ Timer3co!nter is ena' ed on # whi e the INTI pin is hi"h and the TRB contro pin is set$ When c eared@ the timer is ena' ed whene%er the TRB contro 'it is set

C3T*

Timer or co!nter se ected c eared &or timer operation 4inp!t &rom

interna s#stem c oc76 M/ M, M/ , , / / M, , / , / Mode 'it / Mode 'it , MODE , / 0 1 O(ERATINA MODE /1 =IT TIMER3MODE /9 =IT TIMER MODE < =IT A)TO RELOAD S(LIT TIMER MODE

(SW 4(ROARAM STAT)S WORD6

C; AC F, RS/ RS, ,V ?? (

(SW$8 (SW$9 (SW$5 (SW$+ (SW$1 (SW$0 (SW$/ (SW$,

CARR; FLAA A)IILIAR; CARR; AVAILA=LE FOR T.E )SER FRO AENERAL ()R(OSE REAISTER =AN: SELECTOR =IT / REAISTER =AN: SELECTOR =IT , OVERFLOW FLAA )SER DEFINA=LE =IT (ARIT; FLAA SET3CLEARED =; .ARDWARE

(CON REAISATER 4NON =IT ADDRESSA=LE6

I& the SMOD H , 4DEFA)LT ON RESET6 T./ H CR;STAL FREP)ENC; 059???? QQQQQQQQQQQQQQQQQQQQ

1<+ I =A)D RATE I& the SMOD IS H / CR;STAL FREP)ENC;

$)1 * +5,--------------------------------------

/-0 I =A)D RATE There are two wa#s to increase the 'a!d rate o& data trans&er in the <,5/ /$ 0$ To !se a hi"her &reE!enc# cr#sta To chan"e a 'it in the (CON re"ister

(CON re"ister is an < 'it re"ister$ O& the < 'its@ some are !n!sed@ and some are !sed &or the power contro capa'i it# o& the <,5/$ The 'it which is !sed &or the seria comm!nication is D8@ the SMOD 'it$ When the <,5/ is powered !p@ D8 4SMOD =IT6 OF (CON re"ister is 2ero$ We can set it to hi"h '# so&tware and there'# do!' e the 'a!d rate =A)D RATE COM(ARISION FOR SMOD H , AND SMOD H/ T./ 4DECIMAL6 ?1 ?9 ?/0 ?0+ ITAL H //$,5-0 M.> IE 4INTERR)(T ENA=LE REAISTOR6 .EI FD FA F+ E< SMOD H, -9,, +<,, 0+,, /0,, SMOD H/ /-0,, -9,, +<,, 0+,,

EA

IE$8

Disa' e a interr!pts i& EA H ,@ no interr!pts is ac7now ed"ed I& EA is /@ each interr!pt so!rce is indi%id!a # ena' ed or disa' ed =# sendin" or c earin" its ena' e 'it$

IE$9 ET0 ES ET/ EI/ ET, IE$5 IE$+ IE$1 IE$0 IE$/

NOT imp emented ena' es or disa' es timer 0 o%er& a" in <-c50 on # Ena' es or disa' es a seria interr!pt Ena' es or Disa' es timer / o%er& ow interr!pt Ena' es or disa' es eBterna interr!pt Ena' es or Disa' es timer , interr!pt$

EI,

IE$,

Ena' es or Disa' es eBterna interr!pt ,

INTERR)(T (RIORIT; REAISTER

I& the 'it is ,@ the correspondin" interr!pt has a ower priorit# and i& the 'it is / the correspondin" interr!pt has a hi"her priorit# I($8 I($9 (T0 (S (T/ (I/ (T, (I, I($5 I($+ I($1 I($0 I($/ I($, NOT IM(LEMENTED@ RESERVED FOR F)T)RE )SE$ NOT IM(LEMENTED@ RESERVED FOR F)T)RE )SE DEFINE T.E TIMER 0 INTERR)(T (RIORIT; LELVEL DEFINES T.E SERIAL (ORT INTERR)(T (RIORIT; LEVEL DEFINES T.E TIMER / INTERR)(T (RIORIT; LEVEL DEFINES EITERNAL INTERR)(T / (RIORIT; LEVEL DEFINES T.E TIMER , INTERR)(T (RIORIT; LEVEL DEFINES T.E EITERNAL INTERR)(T , (RIORIT; LEVEL

SCON* SERIAL (ORT CONTROL REAISTER@ =IT ADDRESSA=LE S26@

SM, SM/ SM0 REN T=<

* * * * *

SCON$8 Seria (ort mode speci&ied SCON$9 Seria (ort mode speci&ier SCON$5 SCON$+ Set3c eared '# the so&tware to Ena' e3disa' e reception SCON$1 the -th 'it that wi =# so&tware 'e transmitted in modes 0 and 1@

Set3c eared R=< * /@ I& SM0 H ,@ R=< is the stop 'it that was recei%ed$ In mode , R=< is not !sed SCON$0 In modes 0 D1@ is the - th data 'it that was recei%ed$ In mode

(<* (8* (<0 (80 +E +( +E0 +(0

T/ 'it

SCON$/ Transmit interr!pt & a"$ Set '# hardware at the end o& the < th Time in mode ,@ or at the 'e"innin" o& the stop 'it in the

other Modes$ M!st 'e c eared '# so&tware R/ other Modes$ M!st 'e c eared '# the so&tware$ TCON TIMER CO)NTER CONTROL REAISTER This is a 'it addressa' e TF/ TCON$8 Timer / o%er& ows & a"$ Set '# hardware when the O%er& ows$ C eared '# hardware as processor TR/ TF, TCON$9 TCON$5 Timer / r!n contro 'it$ Set3c eared '# so&tware to t!rn Timer Co!nter / On3o&& Timer , o%er& ows & a"$ Set '# hardware when the O%er& ows$ C eared '# hardware as processor TR, IE/ ITI IE, IT, TCON$+ TCON$1 TCON$0 TCON$/ TCON$, Timer , r!n contro 'it$ Set3c eared '# so&tware to t!rn timer Co!nter , on3o&&$ EBterna interr!pt / ed"e & a" Interr!pt / t#pe contro 'it EBterna interr!pt , ed"e Interr!pt , t#pe contro 'it$ timer3co!nter , Timer3Co!nter / SCON$, Recei%e interr!pt & a"$ Set '# hardware at the end o& the <th 'it Time in mode ,@ or ha &wa# thro!"h the stop 'it time in the

MCSM$1 FAMIIN INSTRKCTION SET

Not,s o& D"t" A!! ,ssi&6 Mo!,s Rn ? Wor7in" re"ister R,?R8 Direct ? /0< interna RAM ocations@ an# 3O port@ contro or stat!s re"ister LRi ? Indirect interna or eBterna RAM ocation addressed '# re"ister R, or R/ Rdata ? <?'it constant inc !ded in instr!ction Rdata /9 ? /9?'it constant inc !ded as '#tes 0 and 1 o& instr!ction =it ? /0< so&tware & a"s@ an# 'it addressa' e 3O pin@ contro or stat!s 'it A ? Acc!m! ator Not,s o& P o6 "m A!! ,ssi&6 Mo!,s addr/9 ? Destination address &or LCALL and LSM( ma# 'e an#where within the 9+? :'#te pro"ram memor# address space$ addr// ? Destination address &or ACALL and ASM( wi 'e within the same 0?:'#te pa"e o& pro"ram memor# as the &irst '#te o& the &o owin" instr!ction$ Re ? SSM( and a conditiona j!mps inc !de an < 'it o&&set '#te$ Ran"e is T /083F /0< '#tes re ati%e to the &irst '#te o& the &o owin" instr!ction$ ACAII "!! 11 F!nction* A'so !te ca Description* ACALL !nconditiona # ca s a s!'ro!tine ocated at the indicated address$ The instr!ction increments the (C twice to o'tain the address o& the &o owin" instr!ction@ then p!shes the /9?'it res! t onto the stac7 4 ow?order '#te &irst6 and increments the stac7 pointer twice$ The destination address is o'tained '# s!ccessi%e # concatenatin" the &i%e hi"h?order 'its o& the incremented (C@ op code 'its 8?5@ and the second '#te o& the instr!ction$ The s!'ro!tine ca ed m!st there&ore start within the same 0: ' oc7 o& pro"ram memor# as the &irst '#te o& the instr!ction &o owin" ACALL$ No & a"s are a&&ected$ EBamp e* Initia # S( eE!a s ,8.$ The a'e OS)=RTNO is at pro"ram memor# ocation ,1+5.$ A&ter eBec!tin" the instr!ction ACALL S)=RTN at ocation ,/01.@ S( wi contain ,-.@ interna RAM ocation ,<. and ,-. wi contain ,1+5.$ contain 05. and ,/.@ respecti%e #@ and the (C wi

Operation* ACALL 4(C6 U 4(C6 T 0 4S(6 U 4S(6 T / 44S(66 U 4(C8?,6 4S(6 U 4S(6 T / 44S(66 U 4(C/5?<6 4(C/,?,6 U (a"e address =#tes* 0 C#c es* 0 Encodin"* a/, a- a< / , , , / a8 a9 a5 a+ a1 a0 a/ a, ADD A, 5s 3Mb;t,7 F!nction* Add Description* ADD adds the '#te %aria' e indicated to the acc!m! ator@ ea%in" the res! t in the acc!m! ator$ The carr# and a!Bi iar# carr# & a"s are set@ respecti%e #@ i& there is a Carr# o!t o& 'it 8 or 'it 1@ and c eared otherwise$ When addin" !nsi"ned inte"ers@ the carr# & a" indicates an o%er& ow occ!rred$ OV is set i& there is a carr# o!t o& 'it 9 '!t not o!t o& 'it 8@ or a carr# o!t o& 'it 8 '!t not o!t o& 'it 9M otherwise OV is c eared$ When addin" si"ned inte"ers@ OV indicates a ne"ati%e n!m'er prod!ced as the s!m o& two positi%e operands@ or a positi%e s!m &rom two ne"ati%e operands$ Fo!r so!rce operand addressin" modes are a owed* re"ister@ direct@ re"ister indirect@ or immediate$ EBamp e* The acc!m! ator ho ds ,C1. 4//,,,,//=6 and re"ister , ho ds ,AA. 4/,/,/,/,=6$ The instr!ction ADD A@ R, wi ea%e 9D. 4,//,//,/=6 in the acc!m! ator with the AC & a" c eared and 'oth the carr# & a" and OV set to /$ ADD A,R& Operation* ADD 4A6 U 4A6 T 4Rn6 =#tes* / C#c es* /

ADD A, !i ,3t Operation* ADD 4A6 U 4A6 T 4direct6 =#tes* 0 C#c es* / Encodin"* , , / , / r r r Encodin"* , , / , , / , / direct address ADD A, RRi Operation* ADD 4A6 U 4A6 T 44Ri66 =#tes* / C#c es* / ADD A, 2!"t" Operation* ADD 4A6 U 4A6 T Rdata =#tes* 0 C#c es* / Encodin"* , , / , , / / i Encodin"* , , / , , / , , immediate data ADDC A, 5 s 3Mb;t,7 F!nction* Add with carr# Description* ADDC sim! taneo!s # adds the '#te %aria' e indicated@ the carr# & a" and the acc!m! ator contents@ ea%in" the res! t in the acc!m! ator$ The carr# and a!Bi iar# Carr# & a"s are set@ respecti%e #@ i& there is a carr# o!t o& 'it 8 or 'it 1@ and c eared otherwise$ When addin" !nsi"ned inte"ers@ the carr# & a" indicates an o%er& ow occ!rred$ OV is set i& there is a carr# o!t o& 'it 9 '!t not o!t o& 'it 8@ or a carr# o!t o& 'it 8 '!t not o!t o& 'it 9M otherwise OV is c eared$ When addin" si"ned inte"ers@ OV indicates a ne"ati%e n!m'er prod!ced as the s!m o& two positi%e operands or a positi%e s!m

&rom two ne"ati%e operands$ Fo!r so!rce operand addressin" modes are a owed* re"ister@ direct@ re"ister indirect@ or immediate$ EBamp e* The acc!m! ator ho ds ,C1. 4//,,,,//=6 and re"ister , ho ds ,AA. 4/,/,/,/,=6 with the carr# & a" set$ The instr!ction ADDC A@ R, wi to /$ ADDC A, R& Operation* ADDC 4A6 U 4A6 T 4C6 T 4Rn6 =#tes* / C#c es* / ADDC A, !i ,3t Operation* ADDC 4A6 U 4A6 T 4C6 T 4direct6 =#tes* 0 C#c es* / Encodin"* , , / / / r r r Encodin"* , , / / , / , / direct address ADDC A, RRi Operation* ADDC 4A6 U 4A6 T 4C6 T 44Ri66 =#tes* / C#c es* / ADDC A, 2!"t" Operation* ADDC 4A6 U 4A6 T 4C6 T Rdata =#tes* 0 C#c es* / Encodin"* , , / / , / / i Encodin"* , , / / , / , , immediate data ea%e 9E. 4,//,///,=6 in the acc!m! ator with AC c eared and 'oth the carr# & a" and OV set

ASMP "!! 11 F!nction* A'so !te j!mp Description* ASM( trans&ers pro"ram eBec!tion to the indicated address@ which is &ormed at r!ntime '# concatenatin" the hi"h?order &i%e 'its o& the (C 4a&ter incrementin" the (C twice6@ op code 'its 8?5@ and the second '#te o& the instr!ction$ The destination m!st there&ore 'e within the same 0: ' oc7 o& pro"ram memor# as the &irst '#te o& the instr!ction &o owin" ASM($ EBamp e* The instr!ction ASM( SM(ADR is at ocation ,1+5. and wi Operation* ASM ( 4(C6 U 4(C6 T 0 4(C/,?,6 U (a"e address =#tes* 0 C#c es* 0 Encodin"* a/, a- a< , , , , / a8 a9 a5 a+ a1 a0 a/ a, ANI 5!,stMb;t,7, 5s 3Mb;t,7 F!nction* Lo"ica AND &or '#te %aria' es Description* ANL per&orms the 'itwise o"ica AND operation 'etween the %aria' es indicated and stores the res! ts in the destination %aria' e$ No & a"s are a&&ected$ The two operands a ow siB addressin" mode com'inations$ When the destination is an acc!m! ator@ the so!rce can !se re"ister@ direct@ re"ister?indirect@ or immediate addressin"M when the destination is a direct address@ the so!rce can 'e the acc!m! ator or immediate data$ Not,L When this instr!ction is !sed to modi&# an o!tp!t port@ the %a !e !sed as the ori"ina (ort data wi 'e read &rom the o!tp!t data atch@ not the inp!t pins$ EBamp e* I& the acc!m! ator ho ds ,C1. 4//,,,,//=6 and re"ister , ho ds ,AA. 4/,/,/,/,=6 then the instr!ction ANL A@ R, Wi ea%e </. 4/,,,,,,/=6 in the acc!m! ator$ oad the (C with ,/01.$ a'e OSM(ADRO is at pro"ram memor# ocation ,/01.$ The

When the destination is a direct # addressed '#te@ this instr!ction wi

c ear

com'inations o& 'its in an# RAM ocation or hardware re"ister$ The mas7 '#te determinin" the pattern o& 'its to 'e c eared wo! d either 'e a constant contained in the instr!ction or a %a !e comp!ted in the acc!m! ator at r!n?time$ The instr!ction ANL (/@ R,///,,//= wi c ear 'its 8@ 1@ and 0 o& o!tp!t port /$ ANI A, R& Operation* ANL 4A6 U 4A6 V 4Rn6 =#tes* / C#c es* / Encodin"* , / , / / r r r ANI A, !i ,3t Operation* ANL 4A6 U 4A6 V 4direct6 =#tes* 0 C#c es* / ANI A, RRi Operation* ANL 4A6 U 4A6 V 44Ri66 =#tes* / C#c es* / ANI A, 2!"t" Operation* ANL 4A6 U 4A6 V Rdata =#tes* 0 C#c es* / ANI !i ,3t, A Operation* ANL 4direct6 U 4direct6 V 4A6

=#tes* 0 C#c es* / Encodin"* , / , / , / , / direct address Encodin"* , / , / , / / i Encodin"* , / , / , / , , immediate data Encodin"* , / , / , / , / direct address ANI !i ,3t, 2!"t" Operation* ANL 4direct6 U 4direct6 V Rdata =#tes* 1 C#c es* 0 Encodin"* , / , / , , / / direct address immediate data ANI C, 5s 3Mbit7 F!nction* Lo"ica AND &or 'it %aria' es Description* I& the =oo ean %a !e o& the so!rce 'it is o"ic , then c ear the carr# & a"M otherwise ea%e the carr# & a" in its c!rrent state$ A s ash 4O3O precedin" the operand in the assem' # an"!a"e indicates that the o"ica comp ement o& the addressed 'it is !sed as the so!rce %a !e@ '!t the so!rce 'it itse & is not a&&ected$ No other & a"s are a&&ected$ On # direct 'it addressin" is a owed &or the so!rce operand$ EBamp e* Set the carr# & a" i& and on # i&@ (/$, H /@ ACC$8 H / and OV H ,* MOV C@ (/$,M Load carr# with inp!t pin state ANL C@ ACC$8M AND carr# with acc!m! ator 'it 8 ANL C@ 3OVM AND with in%erse o& o%er& ow & a" ANI C, bit Operation* ANL 4C6 U 4C6 V 4'it6 =#tes* 0 C#c es* 0 ANI C, <bit

Operation* ANL 4C6 U 4C6 V W 4'it6 =#tes* 0 C#c es* 0 Encodin"* / , , , , , / , 'it address Encodin"* / , / / , , , , 'it address CSNE 5!,stMb;t, 7, 5 s 3Mb;t, 7, ,l F!nction* Compare and j!mp i& not eE!a Description* CSNE compares the ma"nit!des o& the &irst two operands@ and 'ranches i& their %a !es are not eE!a $ The 'ranch destination is comp!ted '# addin" the si"ned re ati%e disp acement in the ast instr!ction '#te to the (C@ a&ter incrementin" the (C to the start o& the neBt instr!ction$ The carr# & a" is set i& the !nsi"ned inte"er %a !e o& Xdest?'#teY is ess than the !nsi"ned inte"er %a !e o& Xsrc?'#teYM otherwise@ the carr# is c eared$ Neither operand is a&&ected$ The &irst two operands a ow &o!r addressin" mode com'inations* the acc!m! ator ma# 'e compared with an# direct # addressed '#te or immediate data@ and an# indirect RAM ocation or wor7in" re"ister can 'e compared with an immediate constant$ EBamp e* The acc!m! ator contains 1+.$ Re"ister 8 contains 59.$ The &irst instr!ction in the seE!ence CSNE R8@ R 9,.@ NOTQEPM $ $ $ $ $ $ $ $ M R8 H 9,. NOTQEP SC REPQLOWM I& R8 X 9,.M $ $ $ $ $ $ $ $ M R8 Y 9,. sets the carr# & a" and 'ranches to the instr!ction at a'e NOTQEP$ =# testin" the carr# & a"@ this instr!ction determines whether R8 is "reater or ess than 9,.$ I& the data 'ein" presented to port / is a so 1+.@ then the instr!ction WAIT* CSNE A@ (/@ WAIT c ears the carr# & a" and contin!es with the neBt instr!ction in seE!ence@ since the acc!m! ator does eE!a the data read &rom (/$ 4I& some other %a !e was inp!t on (/@ the pro"ram wi this point !nti the (/ data chan"es to 1+.6$ CSNE A, !i ,3t, ,l Operation* 4(C6 U 4(C6 T 1 i& 4A6 X Y 4direct6 then 4(C6 U 4(C6 T re ati%e o&&set i& 4A6 X 4direct6 then 4C6 U/ oop at

e se 4C6 U , =#tes* 1 C#c es* 0 CSNE A, 2!"t", ,l Operation* 4(C6 U 4(C6 T 1 i& 4A6 X Y data then 4(C6 U 4(C6 T re ati%e o&&set i& 4A6 U data then 4C6 U/ e se 4C6 U , =#tes* 1 C#c es* 0 CSNE RN, 2!"t", ,l Operation* 4(C6 U 4(C6 T 1 i& 4Rn6 X Y data then 4(C6 U 4(C6 T re ati%e o&&set i& 4Rn6 X data then 4C6 U / e se 4C6 U , =#tes* 1 C#c es* 0 Encodin"* / , / / , / , / direct address re $ address Encodin"* / , / / , / , , immediate data re $ address Encodin"* / , / / / r r r immediate data re $ address CSNE RRi, 2!"t", ,l Operation* 4(C6 U 4(C6 T 1 i& 44Ri66 X Y data then 4(C6 U 4(C6 T re ati%e o&&set i& 44Ri66 X data then 4C6 U / e se 4C6 U ,

=#tes* 1 C#c es* 0 Encodin"* / , / / , / / i immediate data re $ address CIR A F!nction* C ear acc!m! ator Description* The acc!m! ator is c eared 4a 'its set to 2ero6$ No & a"s are a&&ected$ EBamp e* The acc!m! ator contains 5C. 4,/,///,,=6$ The instr!ction CLR A wi ea%e the acc!m! ator set to ,,. 4,,,,,,,,=6$ Operation* CLR 4A6 U , =#tes* / C#c es* / Encodin"* / / / , , / , , CIR bit F!nction* C ear 'it Description* The indicated 'it is c eared 4reset to 2ero6$ No other & a"s are a&&ected$ CLR can operate on the carr# & a" or an# direct # addressa' e 'it$ EBamp e* (ort / has pre%io!s # 'een written with 5D. 4,/,///,/=6$ The instr!ction CLR (/$0 wi ea%e the port set to 5-. 4,/,//,,/=6$

CIR C Operation* CLR 4C6 U , =#tes* / C#c es* / CIR bit Operation* CLR 4'it6 U , =#tes* 0

C#c es* / Encodin"* / / , , , , / / Encodin"* / / , , , , / , 'it address CPI A F!nction* Comp ement acc!m! ator Description* Each 'it o& the acc!m! ator is %ersa$ No & a"s are a&&ected$ EBamp e* The acc!m! ator contains 5C. 4,/,///,,=6$ The instr!ction C(L A wi ea%e the acc!m! ator set to ,A1. 4/,/,,,// =6$ Operation* C(L 4A6 U W 4A6 =#tes* / C#c es* / Encodin"* / / / / , / , , CPI bit F!nction* Comp ement 'it Description* The 'it %aria' e speci&ied is comp emented$ A 'it which had 'een a one is chan"ed to 2ero and %ice %ersa$ No other & a"s are a&&ected$ C(L can operate on the carr# or an# direct # addressa' e 'it$ Not,L When this instr!ction is !sed to modi&# an o!tp!t pin@ the %a !e !sed as the ori"ina data wi 'e read &rom the o!tp!t data atch@ not the inp!t pin$ EBamp e* (ort / has pre%io!s # 'een written with 5D. 4,/,///,/=6$ The instr!ction seE!ence C(L (/$/ C(L (/$0 wi ea%e the port set to 5=. 4,/,//,//=6$ o"ica # comp emented 4oneCs comp ement6$ =its which pre%io!s # contained a one are chan"ed to 2ero and %ice

CPI C

Operation* C(L 4C6 U W 4C6 =#tes* / C#c es* / CPI bit Operation* C(L 4'it6 U W 4'it6 =#tes* 0 C#c es* / Encodin"* / , / / , , / / Encodin"* / , / / , , / , 'it address DA A F!nction* Decima adj!st acc!m! ator &or addition Description* DA A adj!sts the ei"ht?'it %a !e in the acc!m! ator res! tin" &rom the ear ier addition o& two %aria' es 4each in pac7ed =CD &ormat6@ prod!cin" two &o!r?'it di"its$ An# ADD or ADDC instr!ction ma# ha%e 'een !sed to per&orm the addition$ I& acc!m! ator 'its 1?, are "reater than nine 4BBBB/,/,?BBBB////6@ or i& the AC & a" is one@ siB is added to the acc!m! ator prod!cin" the proper =CD di"it in the ow order ni'' e$ This interna addition wo! d set the carr# & a" i& a carr#?o!t o& the ow order &o!r?'it &ie d propa"ated thro!"h a hi"h?order 'its@ '!t it wo! d not c ear the carr# & a" otherwise$ I& the carr# & a" is now set@ or i& the &o!r hi"h?order 'its now eBceed nine 4/,/,BBBB? ////BBBB6@ these hi"h?order 'its are incremented '# siB@ prod!cin" the proper =CD di"it in the hi"h?order ni'' e$ A"ain@ this wo! d set the carr# & a" i& there was a carr#o!t o& the hi"h?order 'its@ '!t wo! dnCt c ear the carr#$ The carr# & a" th!s indicates i& the s!m o& the ori"ina two =CD %aria' es is "reater than /,,@ a owin" m! tip e precision decima additions$ OV is not a&&ected$ A o& this occ!rs d!rin" the one instr!ction c#c e$ Essentia #M this instr!ction per&orms the decima con%ersion '# addin" ,,.@ ,9.@ 9,.@ or 99. to the acc!m! ator@ dependin" on initia acc!m! ator and (SW conditions$ Not,L

DA A cannot simp # con%ert a heBadecima n!m'er in the acc!m! ator to =CD notation@ nor does DA A app # to decima s!'traction$ EBamp e* The acc!m! ator ho ds the %a !e 59. 4,/,/,//,=6 representin" the pac7ed =CD di"its o& the decima n!m'er 59$ Re"ister 1 contains the %a !e 98. 4,//,,///=6 representin" the pac7ed =CD di"its o& the decima n!m'er 98$ The carr# & a" is set$ The instr!ction seE!ence ADDC A@ R1 DA A wi &irst per&orm a standard twoCs?comp ement 'inar# addition@ res! tin" in the %a !e ,=E. 4/,/////,=6 in the acc!m! ator$ The carr# and a!Bi iar# carr# & a"s wi 'e c eared$ The decima adj!st instr!ction wi order two di"its o& the decima s!m o& 59@ 98@ and the carr#?in$ The carr# & a" wi 'e set '# the decima adj!st instr!ction@ indicatin" that a decima o%er& ow occ!rred$ The tr!e s!m 59@ 98@ and / is /0+$ =CD %aria' es can 'e incremented or decremented '# addin" ,/. or --.$ I& the acc!m! ator initia # ho ds 1,. 4representin" the di"its o& 1, decima 6@ then the instr!ction seE!ence ADD A@ R--. DA A wi order '#te o& the s!m can 'e interpreted to mean 1, F / H 0-$ Operation* DA contents o& acc!m! ator are =CD i& ZZ4A1?,6 Y -[ \ Z4AC6 H /[[ then 4A1?,6 U 4A1?,6 T 9 and i& ZZ4A8?+6 Y -[ \ Z4C6 H /[[ then 4A8?+6 U 4A8?+6 T 9 ea%e the carr# set and 0-. in the acc!m! ator@ since 1, T -- H /0-$ The ow then a ter the acc!m! ator to the %a !e 0+. 4,,/,,/,,=6@ indicatin" the pac7ed =CD di"its o& the decima n!m'er 0+@ the ow

=#tes* / C#c es* / Encodin"* / / , / , / , , DEC b;t, F!nction* Decrement Description* The %aria' e indicated is decremented '# /$ An ori"ina %a !e o& ,,. wi s !nder& ow to ,FF.$ No & a"s are a&&ected$ Fo!r operand addressin" modes are a owed* acc!m! ator@ re"ister@ direct@ or re"ister?indirect$ Not,L When this instr!ction is !sed to modi&# an o!tp!t port@ the %a !e !sed as the ori"ina port data wi 'e read &rom the o!tp!t data atch@ not the inp!t pins$ EBamp e* Re"ister , contains 8F. 4,///////=6$ Interna RAM ocations 8E. and 8F. contain ,,. and +,.@ respecti%e #$ The instr!ction seE!ence DEC LR, DEC R, DEC LR, wi ea%e re"ister , set to 8E. and interna RAM ocations 8E. and 8F. set to ,FF. and 1F.$ DEC A Operation* DEC 4A6 U 4A6 F / =#tes* / C#c es* / DEC R& Operation* DEC 4Rn6 U 4Rn6 F / =#tes* / C#c es* / Encodin"* , , , / , / , , Encodin"* , , , / / r r r

DEC !i ,3t Operation* DEC 4direct6 U 4direct6 F / =#tes* 0 C#c es* / DEC RRi Operation* DEC 44Ri66 U 44Ri66 F / =#tes* / C#c es* / Encodin"* , , , / , / , / direct address Encodin"* , , , / , / / i DI0 AQ F!nction* Di%ide Description* DIV A= di%ides the !nsi"ned ei"ht?'it inte"er in the acc!m! ator '# the !nsi"ned ei"ht?'it inte"er in re"ister =$ The acc!m! ator recei%es the inte"er part o& the E!otientM re"ister = recei%es the inte"er remainder$ The carr# and OV & a"s wi 'e c eared$ EBception* I& = had ori"ina # contained ,,.@ the %a !es ret!rned in the acc!m! ator and = re"ister wi 'e !nde&ined and the o%er& ow & a" wi 'e set$ The carr# & a" is c eared in an# case$ EBamp e* The acc!m! ator contains 05/ 4,F=. or /////,//=6 and = contains /< 4/0. or ,,,/,,/,=6$ The instr!ction DIV A= wi ea%e /1 in the acc!m! ator 4,D. or ,,,,//,/ =6 and the %a !e /8 4//. or ,,,/,,,/=6 in =@ since 05/ H 4/1B/<6 T /8$ Carr# and OV wi 'oth 'e c eared$ Operation* DIV 4A/5?<6 4=8?,6

=#tes* / C#c es* + Encodin"* / , , , , / , , U 4A6 3 4=6 DSNT 5b;t,7, 5 ,lM"!! 7 F!nction* Decrement and j!mp i& not 2ero Description* DSN> decrements the ocation indicated '# /@ and 'ranches to the address indicated '# the second operand i& the res! tin" %a !e is not 2ero$ An ori"ina %a !e o& ,,. wi s !nder& ow to ,FF.$ No & a"s are a&&ected$ The 'ranch destination wo! d 'e comp!ted '# addin" the si"ned re ati%e?disp acement %a !e in the ast instr!ction '#te to the (C@ a&ter incrementin" the (C to the &irst '#te o& the &o owin" instr!ction$ The ocation decremented ma# 'e a re"ister or direct # addressed '#te$ Not,L When this instr!ction is !sed to modi&# an o!tp!t port@ the %a !e !sed as the ori"ina port data wi 'e read &rom the o!tp!t data atch@ not the inp!t pins$ EBamp e* Interna RAM ocations +,.@ 5,.@ and 9,. contain the %a !es@ ,/.@ 8,.@ and /5.@ respecti%e #$ The instr!ction seE!ence DSN> +,.@ LA=ELQ/ DSN> 5,.@ LA=ELQ0 DSN> 9,.@ LA=ELQ1 wi ca!se a j!mp to the instr!ction at a'e LA=ELQ0 with the %a !es ,,.@ 9F.@ and /5. in the three RAM ocations$ The &irst j!mp was not ta7en 'eca!se the res! t was 2ero$ This instr!ction pro%ides a simp e wa# o& eBec!tin" a pro"ram oop a "i%en n!m'er o& times@ or &or addin" a moderate time de a# 4&rom 0 to 5/0 machine c#c es6 with a sin" e instr!ction$ The instr!ction seE!ence MOV R0@ R< TOAALE* C(L (/$8 DSN> R0@ TOAALE wi to"" e (/$8 ei"ht times@ ca!sin" &o!r o!tp!t p! ses to appear at 'it 8 o& o!tp!t port /$ Each p! se wi pin$ ast three machine c#c esM two &or DSN> and one to a ter the

DSNT R&, ,l Operation* DSN> 4(C6 U 4(C6 T 0 4Rn6 U 4Rn6 F / i& 4Rn6 Y , or 4Rn6 X , then 4(C6 U 4(C6 T re =#tes* 0 C#c es* 0 DSNT !i ,3t, ,l Operation* DSN> 4(C6 U 4(C6 T 0 4direct6 U 4direct6 F / i& 4direct6 Y , or 4direct6 X , then 4(C6 U 4(C6 T re =#tes* 1 C#c es* 0 Encodin"* / / , / / r r r re $ address Encodin"* / / , / , / , / direct address re $ address INC 5b;t,7 F!nction* Increment Description* INC increments the indicated %aria' e '# /$ An ori"ina %a !e o& ,FF. wi o%er& ow to ,,.$ No & a"s are a&&ected$ Three addressin" modes are a owed* re"ister@ direct@ or re"ister?indirect$ Not,L When this instr!ction is !sed to modi&# an o!tp!t port@ the %a !e !sed as the ori"ina port data wi 'e read &rom the o!tp!t data atch@ not the inp!t pins$ EBamp e* Re"ister , contains 8E. 4,//////,=6$ Interna RAM ocations 8E. and 8F. contain ,FF. and +,.@ respecti%e #$ The instr!ction seE!ence INC LR, INC R,

INC LR, wi ea%e re"ister , set to 8F. and interna RAM ocations 8E. and 8F. ho din" 4respecti%e #6 ,,. and +/.$ INC A Operation* INC 4A6 U 4A6 T / =#tes* / C#c es* / INC R& Operation* INC 4Rn6 U 4Rn6 T / =#tes* / C#c es* / Encodin"* , , , , , / , , Encodin"* , , , , / r r r INC !i ,3t Operation* INC 4direct6 U 4direct6 T / =#tes* 0 C#c es* / INC RRi Operation* INC 44Ri66 U 44Ri66 T / =#tes* / C#c es* / Encodin"* , , , , , / , / direct address Encodin"* , , , , , / / i INC DPTR F!nction* Increment data pointer

Description* Increment the /9?'it data pointer '# /$ A /9?'it increment 4mod! o 0/96 is per&ormedM an o%er& ow o& the ow?order '#te o& the data pointer 4D(L6 &rom ,FF. to ,,. wi increment the hi"h?order '#te 4D(.6$ No & a"s are a&&ected$ This is the on # /9?'it re"ister which can 'e incremented$ EBamp e* Re"isters D(. and D(L contain /0. and ,FE.@ respecti%e #$ The instr!ction seE!ence INC D(TR INC D(TR INC D(TR wi chan"e D(. and D(L to /1. and ,/.$ Operation* INC 4D(TR6 U 4D(TR6 T / =#tes* / C#c es* 0 Encodin"* / , / , , , / / SQ bit, ,l F!nction* S!mp i& 'it is set Description* I& the indicated 'it is a one@ j!mp to the address indicatedM otherwise proceed with the neBt instr!ction$ The 'ranch destination is comp!ted '# addin" the si"ned re ati%e?disp acement in the third instr!ction '#te to the (C@ a&ter incrementin" the (C to the &irst '#te o& the neBt instr!ction$ The 'it tested is not modi&ied$ No & a"s are a&&ected$ EBamp e* The data present at inp!t port / is //,,/,/,=$ The acc!m! ator ho ds 59 4,/,/,//,=6$ The instr!ction seE!ence S= (/$0@ LA=EL/ S= ACC$0@ LA=EL0 wi ca!se pro"ram eBec!tion to 'ranch to the instr!ction at a'e LA=EL0$ Operation* S= 4(C6 U 4(C6 T 1 i& 4'it6 H / then 4(C6 U 4(C6 T re =#tes* 1

C#c es* 0 Encodin"* , , / , , , , , 'it address re $ address SQC bit, ,l F!nction* S!mp i& 'it is set and c ear 'it Description* I& the indicated 'it is one@ 'ranch to the address indicatedM otherwise proceed with the neBt instr!ction$ In either case@ c ear the desi"nated 'it$ The 'ranch destination is comp!ted '# addin" the si"ned re ati%e disp acement in the third instr!ction '#te to the (C@ a&ter incrementin" the (C to the &irst '#te o& the neBt instr!ction$ No & a"s are a&&ected$ Not,L When this instr!ction is !sed to test an o!tp!t pin@ the %a !e !sed as the ori"ina data wi 'e read &rom the o!tp!t data atch@ not the inp!t pin$ EBamp e* The acc!m! ator ho ds 59. 4,/,/,//,=6$ The instr!ction seE!ence S=C ACC$1@ LA=EL/ S=C ACC$0@ LA=EL0 wi ca!se pro"ram eBec!tion to contin!e at the instr!ction identi&ied '# the a'e LA=EL0@ with the acc!m! ator modi&ied to 50. 4,/,/,,/,=6$ Operation* S=C 4(C6 U 4(C6 T 1 i& 4'it6 H / then 4'it6 U , 4(C6 U 4(C6 T re =#tes* 1 C#c es* 0 Encodin"* , , , / , , , , 'it address re $ address SC ,l F!nction* S!mp i& carr# is set Description* I& the carr# & a" is set@ 'ranch to the address indicatedM otherwise proceed with the neBt instr!ction$ The 'ranch destination is comp!ted '# addin" the si"ned re ati%e disp acement in the second instr!ction '#te to the (C@ a&ter incrementin" the (C twice$ No & a"s are a&&ected$

EBamp e* The carr# & a" is c eared$ The instr!ction seE!ence SC LA=EL/ C(L C SC LA=EL0 wi set the carr# and ca!se pro"ram eBec!tion to contin!e at the instr!ction identi&ied '# the a'e LA=EL0$ Operation* SC 4(C6 U 4(C6 T 0 i& 4C6 H / then 4(C6 U 4(C6 T re =#tes* 0 C#c es* 0 Encodin"* , / , , , , , , re $ address SMP RA > DPTR F!nction* S!mp indirect Description* Add the ei"ht?'it !nsi"ned contents o& the acc!m! ator with the siBteen? 'it data pointer@ and oad the res! tin" s!m to the pro"ram co!nter$ This wi 'e the address &or s!'seE!ent instr!ction &etches$ SiBteen?'it addition is per&ormed 4mod! o 0/96* a carr#?o!t &rom the ow?order ei"ht 'its propa"ates thro!"h the hi"her?order 'its$ Neither the acc!m! ator nor the data pointer is a tered$ No & a"s are a&&ected$ EBamp e* An e%en n!m'er &rom , to 9 is in the acc!m! ator$ The &o owin" seE!ence o& instr!ctions wi 'ranch to one o& &o!r ASM( instr!ctions in a j!mp ta' e startin" at SM(QT=L* MOV D(TR@ RSM(QT=L SM( LA T D(TR SM(QT=L* ASM( LA=EL, ASM( LA=EL/ ASM( LA=EL0 ASM( LA=EL1

I& the acc!m! ator eE!a s ,+. when startin" this seE!ence@ eBec!tion wi j!mp to a'e LA=EL0$ Remem'er that ASM( is a two?'#te instr!ction@ so the j!mp instr!ctions start at e%er# other address$ Operation* SM( 4(C6 U 4A6 T 4D(TR6 =#tes* / C#c es* 0 Encodin"* , / / / , , / / SNQ bit, ,l F!nction* S!mp i& 'it is not set Description* I& the indicated 'it is a 2ero@ 'ranch to the indicated addressM otherwise proceed with the neBt instr!ction$ The 'ranch destination is comp!ted '# addin" the si"ned re ati%e?disp acement in the third instr!ction '#te to the (C@ a&ter incrementin" the (C to the &irst '#te o& the neBt instr!ction$ The 'it tested is not modi&ied$ No & a"s are a&&ected$ EBamp e* The data present at inp!t port / is //,,/,/,=$ The acc!m! ator ho ds 59. 4,/,/,//,=6$ The instr!ction seE!ence SN= (/$1@ LA=EL/ SN= ACC$1@ LA=EL0 wi ca!se pro"ram eBec!tion to contin!e at the instr!ction at a'e LA=EL0$ Operation* SN= 4(C6 U 4(C6 T 1 i& 4'it6 H , then 4(C6 U 4(C6 T re $ =#tes* 1 C#c es* 0 Encodin"* , , / / , , , , 'it address re $ address SNC ,l F!nction* S!mp i& carr# is not set Description* I& the carr# & a" is a 2ero@ 'ranch to the address indicatedM otherwise proceed with the neBt instr!ction$ The 'ranch destination is comp!ted '# addin" the

si"ned re ati%e?disp acement in the second instr!ction '#te to the (C@ a&ter incrementin" the (C twice to point to the neBt instr!ction$ The carr# & a" is not modi&ied$ EBamp e* The carr# & a" is set$ The instr!ction seE!ence SNC LA=EL/ C(L C SNC LA=EL0 wi c ear the carr# and ca!se pro"ram eBec!tion to contin!e at the instr!ction identi&ied '# the a'e LA=EL0$ Operation* SNC 4(C6 U 4(C6 T 0 i& 4C6 H , then 4(C6 U 4(C6 T re =#tes* 0 C#c es* 0 Encodin"* , / , / , , , , re $ address SNT ,l F!nction* S!mp i& acc!m! ator is not 2ero Description* I& an# 'it o& the acc!m! ator is a one@ 'ranch to the indicated addressM otherwise proceed with the neBt instr!ction$ The 'ranch destination is comp!ted '# addin" the si"ned re ati%e?disp acement in the second instr!ction '#te to the (C@ a&ter incrementin" the (C twice$ The acc!m! ator is not modi&ied$ No & a"s are a&&ected$ EBamp e* The acc!m! ator ori"ina # ho ds ,,.$ The instr!ction seE!ence SN> LA=EL/ INC A SN> LA=EL0 wi set the acc!m! ator to ,/. and contin!e at a'e LA=EL0$ Operation* SN> 4(C6 U 4(C6 T 0 i& 4A6 ] , then 4(C6 U 4(C6 T re $ =#tes* 0 C#c es* 0

Encodin"* , / / / , , , , re $ address ST ,l F!nction* S!mp i& acc!m! ator is 2ero Description* I& a 'its o& the acc!m! ator are 2ero@ 'ranch to the address indicatedM otherwise proceed with the neBt instr!ction$ The 'ranch destination is comp!ted '# addin" the si"ned re ati%e?disp acement in the second instr!ction '#te to the (C@ a&ter incrementin" the (C twice$ The acc!m! ator is not modi&ied$ No & a"s are a&&ected$ EBamp e* The acc!m! ator ori"ina # contains ,/.$ The instr!ction seE!ence S> LA=EL/ DEC A S> LA=EL0 wi chan"e the acc!m! ator to ,,. and ca!se pro"ram eBec!tion to contin!e at the instr!ction identi&ied '# the a'e LA=EL0$ Operation* S> 4(C6 U 4(C6 T 0 i& 4A6 H , then 4(C6 U 4(C6 T re =#tes* 0 C#c es* 0 Encodin"* , / / , , , , , re $ address ICAII "!! 19 F!nction* Lon" ca Description* LCALL ca s a s!'ro!tine ocated at the indicated address$ The instr!ction adds three to the pro"ram co!nter to "enerate the address o& the neBt instr!ction and then p!shes the /9?'it res! t onto the stac7 4 ow '#te &irst6@ incrementin" the stac7 pointer '# two$ The hi"h?order and ow?order '#tes o& the (C are then oaded@ respecti%e #@ with the second and third '#tes o& the LCALL instr!ction$ (ro"ram eBec!tion contin!es with the instr!ction at this address$ The s!'ro!tine ma# there&ore 'e"in an#where in the &! address space$ No & a"s are a&&ected$ EBamp e* Initia # the stac7 pointer eE!a s ,8.$ The a'e OS)=RTNO is assi"ned to pro"ram memor# ocation /01+.$ A&ter eBec!tin" the instr!ction 9+ :'#tes pro"ram memor#

LCALL S)=RTN at ocation ,/01.@ the stac7 pointer wi contain ,-.@ interna RAM ocations ,<. and ,-. wi contain 09. and ,/.@ and the (C wi contain /01+.$ Operation* LCALL 4(C6 U 4(C6 T 1 4S(6 U 4S(6 T / 44S(66 U 4(C8?,6 4S(6 U 4S(6 T / 44S(66 U 4(C/5?<6 4(C6 U addr/5?, =#tes* 1 C#c es* 0 Encodin"* , , , / , , / , addr/5$ $ addr< addr8$ $ addr, ISMP "!! 19 F!nction* Lon" j!mp Description* LSM( ca!ses an !nconditiona 'ranch to the indicated address@ '# oadin" the hi"h order and ow?order '#tes o& the (C 4respecti%e #6 with the second and third instr!ction '#tes$ The destination ma# there&ore 'e an#where in the &! 9+: pro"ram memor# address space$ No & a"s are a&&ected$ EBamp e* The a'e OSM(ADRO is assi"ned to the instr!ction at pro"ram memor# ocation /01+.$ The instr!ction LSM( SM(ADR at ocation ,/01. wi Operation* LSM( 4(C6 U addr/5?, =#tes* 1 C#c es* 0 Encodin"* , , , , , , / , addr/5 $ $ $ addr< addr8 $ $ $ addr, MO0 5!,stMb;t,7, 5s 3Mb;t,7 F!nction* Mo%e '#te %aria' e Description* The '#te %aria' e indicated '# the second operand is copied into the ocation oad the pro"ram co!nter with /01+.$

speci&ied '# the &irst operand$ The so!rce '#te is not a&&ected$ No other re"ister or & a" is a&&ected$ This is '# &ar the most & eBi' e operation$ Fi&teen com'inations o& so!rce and destination addressin" modes are a owed$ EBamp e* Interna RAM ocation 1,. ho ds +,.$ The %a !e o& RAM ocation +,. is /,.$ The data present at inp!t port / is //,,/,/,= 4,CA.6$ MOV R,@ R1,.M R, X H 1,. MOV A@ LR,M A X H +,. MOV R/@ AM R/ X H +,. MOV =@ LR/M = X H /,. MOV LR/@ (/M RAM 4+,.6 X H ,CA. MOV (0@ (/M (0 X H ,CA. ea%es the %a !e 1,. in re"ister ,@ +,. in 'oth the acc!m! ator and re"ister /@ /,. in re"ister =@ and ,CA. 4//,,/,/,=6 'oth in RAM ocation +,. and o!tp!t on port 0$ MO0 A, R& Operation* MOV 4A6 U 4Rn6 =#tes* / C#c es* / MO0 A, !i ,3t U( Operation* MOV 4A6 U 4direct6 =#tes* 0 C#c es* / ^6 MOV A@ ACC is not a %a id instr!ction$ Encodin"* / / / , / r r r Encodin"* / / / , , / , / direct address MO0 A,RRi Operation* MOV 4A6 U 44Ri66 =#tes* /

C#c es* / MO0 A, 2!"t" Operation* MOV 4A6 U Rdata =#tes* 0 C#c es* / MO0 R&, A Operation* MOV 4Rn6 U 4A6 =#tes* / C#c es* / MO0 R&, !i ,3t Operation* MOV 4Rn6 U 4direct6 =#tes* 0 C#c es* 0 Encodin"* / / / , , / / i Encodin"* , / / / , / , , immediate data Encodin"* / / / / / r r r Encodin"* / , / , / r r r direct address MO0 R&, 2!"t" Operation* MOV 4Rn6 U Rdata =#tes* 0 C#c es* / MO0 !i ,3t, A Operation* MOV 4direct6 U 4A6 =#tes* 0

C#c es* / MO0 !i ,3t, R& Operation* MOV 4direct6 U 4Rn6 =#tes* 0 C#c es* 0 MO0 !i ,3t, !i ,3t Operation* MOV 4direct6 U 4direct6 =#tes* 1 C#c es* 0 Encodin"* , / / / / r r r immediate data Encodin"* / / / / , / , / direct address Encodin"* / , , , / r r r direct address Encodin"* / , , , , / , / dir$addr$ 4src6 dir$addr$ 4dest6 MO0 !i ,3t, R Ri Operation* MOV 4direct6 U 44Ri66 =#tes* 0 C#c es* 0 MO0 !i ,3t, 2!"t" Operation* MOV 4direct6 U Rdata =#tes* 1 C#c es* 0 MO0 R Ri, A Operation* MOV 44Ri66 U 4A6 =#tes* /

C#c es* / MO0 R Ri, !i ,3t Operation* MOV 44Ri66 U 4direct6 =#tes* 0 C#c es* 0 Encodin"* / , , , , / / i direct address Encodin"* , / / / , / , / direct address immediate data Encodin"* / / / / , / / i Encodin"* / , / , , / / i direct address MO0 R Ri, 2!"t" Operation* MOV 44Ri66 U Rdata =#tes* 0 C#c es* / Encodin"* , / / / , / / i immediate data MO0 5!,stMbit7, 5s 3Mbit7 F!nction* Mo%e 'it data Description* The =oo ean %aria' e indicated '# the second operand is copied into the ocation speci&ied '# the &irst operand$ One o& the operands m!st 'e the carr# & a"M the other ma# 'e an# direct # addressa' e 'it$ No other re"ister or & a" is a&&ected$ EBamp e* The carr# & a" is ori"ina # set$ The data present at inp!t port 1 is //,,,/,/=$ The data pre%io!s # written to o!tp!t port / is 15. 4,,//,/,/=6$ MOV (/$1@ C MOV C@ (1$1 MOV (/$0@ C wi ea%e the carr# c eared and chan"e port / to 1-. 4,,///,,/ =6$

MO0 C, bit Operation* MOV 4C6 U 4'it6

=#tes* 0 C#c es* / MO0 bit, C Operation* MOV 4'it6 U 4C6 =#tes* 0 C#c es* 0 Encodin"* / , / , , , / , 'it address Encodin"* / , , / , , / , 'it address MO0 DPTR, 2!"t"19 F!nction* Load data pointer with a /9?'it constant Description* The data pointer is oaded with the /9?'it constant indicated$ The /9 'it constant is oaded into the second and third '#tes o& the instr!ction$ The second '#te 4D(.6 is the hi"h?order '#te@ whi e the third '#te 4D(L6 ho ds the ow?order '#te$ No & a"s are a&&ected$ This is the on # instr!ction which mo%es /9 'its o& data at once$ EBamp e* The instr!ction MOV D(TR@ R/01+. wi oad the %a !e /01+. into the data pointer* D(. wi ho d /0. and D(L wi ho d 1+.$ Operation* MOV 4D(TR6 U Rdata/5?, D(. D(L U Rdata/5?< Rdata8?, =#tes* 1 C#c es* 0 Encodin"* / , , / , , , , immed$ data /5 $ $ $ < immed$ data 8 $ $ $ , MO0C A, RA > 5b"s,M ,67 F!nction* Mo%e code '#te Description* The MOVC instr!ctions oad the acc!m! ator with a code '#te@ or constant &rom pro"ram memor#$ The address o& the '#te &etched is the s!m o& the ori"ina !nsi"ned ei"ht?'it acc!m! ator contents and the contents o& a siBteen?'it 'ase re"ister@ which ma# 'e either the data pointer or the (C$ In the atter case@ the (C is

incremented to the address o& the &o owin" instr!ction 'e&ore 'ein" added to the acc!m! atorM otherwise the 'ase re"ister is not a tered$ SiBteen?'it addition is per&ormed so a carr#?o!t &rom the ow?order ei"ht 'its ma# propa"ate thro!"h hi"her? order 'its$ No & a"s are a&&ected$ EBamp e* A %a !e 'etween , and 1 is in the acc!m! ator$ The &o owin" instr!ctions wi trans ate the %a !e in the acc!m! ator to one o& &o!r %a !es de&ined '# the D= 4de&ine '#te6 directi%e$ RELQ(C* INC A MOVC A@ LA T (C RET D= 99. D= 88. D= <<. D= --. I& the s!'ro!tine is ca ed with the acc!m! ator eE!a to ,/.@ it wi ret!rn with 88. in the acc!m! ator$ The INC A 'e&ore the MOVC instr!ction is needed toO"et aro!ndO the RET instr!ction a'o%e the ta' e$ I& se%era '#tes o& code separated the MOVC &rom the ta' e@ the correspondin" n!m'er wo! d 'e added to the acc!m! ator instead$ MO0C A, RA > DPTR Operation* MOVC 4A6 U 44A6 T 4D(TR66 =#tes* / C#c es* 0 Encodin"* / , , / , , / / MO0C A, RA > PC Operation* MOVC 4(C6 U 4(C6 T / 4A6 U 44A6 T 4(C66 =#tes* / C#c es* 0

Encodin"* / , , , , , / / MO0P 5!,stMb;t,7, 5s 3Mb;t,7 F!nction* Mo%e eBterna Description* The MOVI instr!ctions trans&er data 'etween the acc!m! ator and a '#te o& eBterna data memor#@ hence theOIO appended to MOV$ There are two t#pes o& instr!ctions@ di&&erin" in whether the# pro%ide an ei"ht 'it or siBteen?'it indirect address to the eBterna data RAM$ In the &irst t#pe@ the contents o& R, or R/ in the c!rrent re"ister 'an7 pro%ide an ei"ht?'it address m! tip eBed with data on (,$ Ei"ht 'its are s!&&icient &or eBterna 3O eBpansion decodin" or a re ati%e # sma order address 'its$ These pins wo! d 'e contro ed '# an o!tp!t instr!ction precedin" the MOVI$ In the second t#pe o& MOVI instr!ctions@ the data pointer "enerates a siBteen?'it address$ (0 o!tp!ts the hi"h?order ei"ht address 'its 4the contents o& D(.6 whi e (, m! tip eBes the ow?order ei"ht 'its 4D(L6 with data$ The (0 specia &!nction re"ister retains its pre%io!s contents whi e the (0 o!tp!t '!&&ers are emittin" the contents o& D(.$ This &orm is &aster and more e&&icient when accessin" %er# ar"e data arra#s 4!p to 9+ :'#tes6@ since no additiona instr!ctions are needed to set !p the o!tp!t ports$ It is possi' e in some sit!ations to miB the two MOVI t#pes$ A ar"e RAM arra# with its hi"h?order address ines dri%en '# (0 can 'e addressed %ia the data pointer@ or with code to o!tp!t hi"h?order address 'its to (0 &o owed '# a MOVI instr!ction !sin" R, or R/$ EBamp e* An eBterna 059 '#te RAM !sin" m! tip eBed address3data ines 4e$"$ an SA= </55 RAM3I3O3timer6 is connected to the SA= <,4c6 5II port ,$ (ort 1 pro%ides contro ines &or the eBterna RAM$ (orts / and 0 are !sed &or norma 3O$ Re"isters , and / contain /0. and 1+.$ Location 1+. o& the eBterna RAM ho ds the %a !e 59.$ The instr!ction seE!ence MOVI A@ LR/ MOVI LR,@ A copies the %a !e 59. into 'oth the acc!m! ator and eBterna RAM ocation /0.$ RAM arra#$ For somewhat ar"er arra#s@ an# o!tp!t port pins can 'e !sed to o!tp!t hi"her?

MO0P A,RRi Operation* MOVI 4A6 U 44Ri66 =#tes* / C#c es* 0 MO0P A,RDPTR Operation* MOVI 4A6 U 44D(TR66 =#tes* / C#c es* 0 MO0P RRi, A Operation* MOVI 44Ri66 U 4A6 =#tes* / C#c es* 0 MO0P RDPTR, A Operation* MOVI 44D(TR66 U 4A6 =#tes* / C#c es* 0 Encodin"* / / / , , , / i Encodin"* / / / , , , , , Encodin"* / / / / , , / i Encodin"* / / / / , , , , MKI AQ F!nction* M! tip # Description* M)L A= m! tip ies the !nsi"ned ei"ht?'it inte"ers in the acc!m! ator and re"ister =$ The ow?order '#te o& the siBteen?'it prod!ct is e&t in the acc!m! ator@ and the hi"h?order '#te in =$ I& the prod!ct is "reater than 055 4,FF.6 the o%er& ow & a" is setM otherwise it is c eared$ The carr# & a" is a wa#s c eared$ EBamp e*

Ori"ina # the acc!m! ator ho ds the %a !e <, 45,.6$ Re"ister = ho ds the %a !e /9, 4,A,.6$ The instr!ction M)L A= wi "i%e the prod!ct /0@<,, 410,,.6@ so = is chan"ed to 10. 4,,//,,/,=6 and the acc!m! ator is c eared$ The o%er& ow & a" is set@ carr# is c eared$ Operation* M)L 4A8?,6 4=/5?<6 =#tes* / C#c es* + Encodin"* / , / , , / , , U 4A6 B 4=6 NOP F!nction* No operation Description* EBec!tion contin!es at the &o owin" instr!ction$ Other than the (C@ no re"isters or & a"s are a&&ected$ EBamp e* It is desired to prod!ce a ow?"oin" o!tp!t p! se on 'it 8 o& port 0 astin" eBact # 5 c#c es$ A simp e SET=3CLR seE!ence wo! d "enerate a one?c#c e p! se@ so &o!r additiona c#c es m!st 'e inserted$ This ma# 'e done 4ass!min" no interr!pts are ena' ed6 with the instr!ction seE!ence CLR (0$8 NO( NO( NO( NO( SET= (0$8 Operation* NO( =#tes* / C#c es* / Encodin"* , , , , , , , , ORI 5!,stMb;t,7 5s 3Mb;t,7 F!nction* Lo"ica OR &or '#te %aria' es

Description* ORL per&orms the 'itwise o"ica OR operation 'etween the indicated %aria' es@ storin" the res! ts in the destination '#te$ No & a"s are a&&ected$ The two operands a ow siB addressin" mode com'inations$ When the destination is the acc!m! ator@ the so!rce can !se re"ister@ direct@ re"ister?indirect@ or immediate addressin"M when the destination is a direct address@ the so!rce can 'e the acc!m! ator or immediate data$ Not,L When this instr!ction is !sed to modi&# an o!tp!t port@ the %a !e !sed as the ori"ina port data wi 'e read &rom the o!tp!t data atch@ not the inp!t pins$ EBamp e* I& the acc!m! ator ho ds ,C1. 4//,,,,//=6 and R, ho ds 55. 4,/,/,/,/=6 then the instr!ction ORL A@ R, wi ea%e the acc!m! ator ho din" the %a !e ,D8. 4//,/,///=6$ When the destination is a direct # addressed '#te@ the instr!ction can set com'inations o& 'its in an# RAM ocation or hardware re"ister$ The pattern o& 'its to 'e set is determined '# a mas7 '#te@ which ma# 'e either a constant data %a !e in the instr!ction or a %aria' e comp!ted in the acc!m! ator at r!n?time$ The instr!ction ORL (/@ R,,//,,/,= wi set 'its 5@ +@ and / o& o!tp!t port /$ ORI A, R& Operation* ORL 4A6 U 4A6 \ 4Rn6 =#tes* / C#c es* / Encodin"* , / , , / r r r ORI A, !i ,3t Operation* ORL 4A6 U 4A6 \ 4direct6 =#tes* 0 C#c es* / ORI A,RRi

Operation* ORL 4A6 U 4A6 \ 44Ri66 =#tes* / C#c es* / ORI A, !"t" Operation* ORL 4A6 U 4A6 \ Rdata =#tes* 0 C#c es* / ORI !i ,3t, A Operation* ORL 4direct6 U 4direct6 \ 4A6 =#tes* 0 C#c es* / Encodin"* , / , , , / , / direct address Encodin"* , / , , , / / i Encodin"* , / , , , / , , immediate data Encodin"* , / , , , , / , direct address ORI !i ,3t, 2!"t" Operation* ORL 4direct6 U 4direct6 \ Rdata =#tes* 1 C#c es* 0 Encodin"* , / , , , , / / direct address immediate data ORI C, 5s 3Mbit7 F!nction* Lo"ica OR &or 'it %aria' es Description* Set the carr# & a" i& the =oo ean %a !e is o"ic /M ea%e the carr# in its c!rrent state otherwise$ A s ash 4O3O6 precedin" the operand in the assem' # an"!a"e indicates that the o"ica comp ement o& the addressed 'it is !sed as the so!rce %a !e@ '!t

the so!rce 'it itse & is not a&&ected$ No other & a"s are a&&ected$ EBamp e* Set the carr# & a" i& and on # i&@ (/$, H /@ ACC$8 H / or OV H ,* MOV C@ (/$,M Load carr# with inp!t pin (/$, ORL C@ ACC$8M OR carr# with the acc!m! ator 'it 8 ORL C@ 3OVM OR carr# with the in%erse o& OV ORI C, bit Operation* ORL 4C6 U 4C6 \ 4'it6 =#tes* 0 C#c es* 0 ORI C, <bit Operation* ORL 4C6 U 4C6 \ W 4'it6 =#tes* 0 C#c es* 0 Encodin"* , / / / , , / , 'it address Encodin"* / , / , , , , , 'it address POP !i ,3t F!nction* (op &rom stac7 Description* The contents o& the interna RAM ocation addressed '# the stac7 pointer are read@ and the stac7 pointer is decremented '# one$ The %a !e read is the trans&er to the direct # addressed '#te indicated$ No & a"s are a&&ected$ EBamp e* The stac7 pointer ori"ina # contains the %a !e 10.@ and interna RAM ocations 1,. thro!"h 10. contain the %a !es 0,.@ 01.@ and ,/.@ respecti%e #$ The instr!ction seE!ence (O( D(. (O( D(L wi ea%e the stac7 pointer eE!a to the %a !e 1,. and the data pointer set to ,/01.$ At this point the instr!ction

(O( S( wi ea%e the stac7 pointer set to 0,.$ Note that in this specia case the stac7 pointer was decremented to 0F. 'e&ore 'ein" oaded with the %a !e popped 40,.6$ Operation* (O( 4direct6 U 44S(66 4S(6 U 4S(6 F / =#tes* 0 C#c es* 0 Encodin"* / / , / , , , , direct address PKSH !i ,3t F!nction* (!sh onto stac7 Description* The stac7 pointer is incremented '# one$ The contents o& the indicated %aria' e is then copied into the interna RAM ocation addressed '# the stac7 pointer$ Otherwise no & a"s are a&&ected$ EBamp e* On enterin" an interr!pt ro!tine the stac7 pointer contains ,-.$ The data pointer ho ds the %a !e ,/01.$ The instr!ction seE!ence ()S. D(L ()S. D(. wi ea%e the stac7 pointer set to ,=. and store 01. and ,/. in interna RAM ocations ,A. and ,=.@ respecti%e #$ Operation* ()S. 4S(6 U 4S(6 T / 44S(66 U 4direct6 =#tes* 0 C#c es* 0 Encodin"* / / , , , , , , direct address RET F!nction* Ret!rn &rom s!'ro!tine Description* RET pops the hi"h and ow?order '#tes o& the (C s!ccessi%e # &rom the stac7@ decrementin" the stac7 pointer '# two$ (ro"ram eBec!tion contin!es at the res! tin" address@ "enera # the instr!ction immediate # &o owin" an ACALL or LCALL$ No & a"s are a&&ected$

EBamp e* The stac7 pointer ori"ina # contains the %a !e ,=.$ Interna RAM ocations ,A. and ,=. contain the %a !es 01. and ,/.@ respecti%e #$ The instr!ction RET wi Operation* RET 4(C/5?<6 U 44S(66 4S(6 U 4S(6 F / 4(C8?,6 U 44S(66 4S(6 U 4S(6 F / =#tes* / C#c es* 0 Encodin"* , , / , , , / , RETI F!nction* Ret!rn &rom interr!pt Description* RETI pops the hi"h and ow?order '#tes o& the (C s!ccessi%e # &rom the stac7@ and restores the interr!pt o"ic to accept additiona interr!pts at the same priorit# e%e as the one j!st processed$ The stac7 pointer is e&t decremented '# two$ No other re"isters are a&&ectedM the (SW is not a!tomatica # restored to its pre? interr!pt stat!s$ (ro"ram eBec!tion contin!es at the res! tin" address@ which is "enera # the instr!ction immediate # a&ter the point at which the interr!pt reE!est was detected$ I& a ower or same? e%e interr!pt is pendin" when the RETI instr!ction is eBec!ted@ that one instr!ction wi processed$ EBamp e* The stac7 pointer ori"ina # contains the %a !e ,=.$ An interr!pt was detected d!rin" the instr!ction endin" at ocation ,/00.$ Interna RAM ocations ,A. and ,=. contain the %a !es 01. and ,/.@ respecti%e #$ The instr!ction RETI wi ea%e the stac7 pointer eE!a to ,-. and ret!rn pro"ram eBec!tion to ocation ,/01.$ Operation* RETI 4(C/5?<6 U 44S(66 4S(6 U 4S(6 F / 'e eBec!ted 'e&ore the pendin" interr!pt is ea%e the stac7 pointer eE!a to the %a !e ,-.$ (ro"ram eBec!tion wi contin!e at ocation ,/01.$

4(C8?,6 U 44S(66 4S(6 U 4S(6 F / =#tes* / C#c es* 0 Encodin"* , , / / , , / , RI A F!nction* Rotate acc!m! ator e&t Description* The ei"ht 'its in the acc!m! ator are rotated one 'it to the e&t$ =it 8 is rotated into the 'it , position$ No & a"s are a&&ected$ EBamp e* The acc!m! ator ho ds the %a !e ,C5. 4//,,,/,/=6$ The instr!ction RL A ea%es the acc!m! ator ho din" the %a !e <=. 4/,,,/,//=6 with the carr# !na&&ected$ Operation* RL 4An T /6 U 4An6 n H ,?9 4A,6 U 4A86 =#tes* / C#c es* / Encodin"* , , / , , , / / RIC A F!nction* Rotate acc!m! ator e&t thro!"h carr# & a" Description* The ei"ht 'its in the acc!m! ator and the carr# & a" are to"ether rotated one 'it to the e&t$ =it 8 mo%es into the carr# & a"M the ori"ina state o& the carr# & a" mo%es into the 'it , position$ No other & a"s are a&&ected$ EBamp e* The acc!m! ator ho ds the %a !e ,C5. 4//,,,/,/=6@ and the carr# is 2ero$ The instr!ction RLC A ea%es the acc!m! ator ho din" the %a !e <A. 4/,,,/,/,=6 with the carr# set$ Operation* RLC 4An T /6 U 4An6 n H ,?9 4A,6 U 4C6 4C6 U 4A86 =#tes* / C#c es* /

Encodin"* , , / / , , / / RR A F!nction* Rotate acc!m! ator ri"ht Description* The ei"ht 'its in the acc!m! ator are rotated one 'it to the ri"ht$ =it , is rotated into the 'it 8 positions$ No & a"s are a&&ected$ EBamp e* The acc!m! ator ho ds the %a !e ,C5. 4//,,,/,/=6$ The instr!ction RR A ea%es the acc!m! ator ho din" the %a !e ,E0. 4///,,,/,=6 with the carr# !na&&ected$ Operation* RR 4An6 U 4An T /6 n H ,?9 4A86 U 4A,6 =#tes* / C#c es* / Encodin"* , , , , , , / / RRC A F!nction* Rotate acc!m! ator ri"ht thro!"h carr# & a" Description* The ei"ht 'its in the acc!m! ator and the carr# & a" are to"ether rotated one 'it to the ri"ht$ =it , mo%es into the carr# & a"M the ori"ina %a !e o& the carr# & a" mo%es into the 'it 8 position$ No other & a"s are a&&ected$ EBamp e* The acc!m! ator ho ds the %a !e ,C5. 4//,,,/,/=6@ the carr# is 2ero$ The instr!ction RRC A ea%es the acc!m! ator ho din" the %a !e 90. 4,//,,,/,=6 with the carr# set$ Operation* RRC 4An6 U 4An T /6 nH,?9 4A86 U 4C6 4C6 U 4A,6 =#tes* / C#c es* / Encodin"* , , , / , , / /

SETQ 5bit7 F!nction* Set 'it Description* SET= sets the indicated 'it to one$ SET= can operate on the carr# & a" or an# direct # addressa' e 'it$ No other & a"s are a&&ected$ EBamp e* The carr# & a" is c eared$ O!tp!t port / has 'een written with the %a !e 1+. 4,,//,/,,=6$ The instr!ctions SET= C SET= (/$, wi ea%e the carr# & a" set to / and chan"e the data o!tp!t on port / to 15. 4,,//,/,/=6$ SETQ C Operation* SET= 4C6 U / =#tes* / C#c es* / SETQ bit Operation* SET= 4'it6 U / =#tes* 0 C#c es* / Encodin"* / / , / , , / / Encodin"* / / , / , , / , 'it address SSMP ,l F!nction* Short j!mp Description* (ro"ram contro 'ranches !nconditiona # to the address indicated$ The 'ranch destination is comp!ted '# addin" the si"ned disp acement in the second instr!ction '#te to the (C@ a&ter incrementin" the (C twice$ There&ore@ the ran"e o& destinations a owed is &rom /0< '#tes precedin" this instr!ction to /08 '#tes &o owin" it$ EBamp e* The a'e ORELADRO is assi"ned to an instr!ction at pro"ram memor# ocation

,/01.$ The instr!ction SSM( RELADR wi assem' e into ocation ,/,,.$ A&ter the instr!ction is eBec!ted@ the (C wi contain the %a !e ,/01.$ Not,L )nder the a'o%e conditions the instr!ction &o owin" SSM( wi 'e at /,0.$ There&ore@ the disp acement '#te o& the instr!ction wi 'e the re ati%e o&&set 4,/01.? ,/,0.6 H 0/.$ In other words@ an SSM( with a disp acement o& ,FE. wo! d 'e a one?instr!ction in&inite oop$ Operation* SSM( 4(C6 U 4(C6 T 0 4(C6 U 4(C6 T re =#tes* 0 C#c es* 0 Encodin"* / , , , , , , , re $ address SKQQ A, 5s 3Mb;t,7 F!nction* S!'tract with 'orrow Description* S)== s!'tracts the indicated %aria' e and the carr# & a" to"ether &rom the acc!m! ator@ ea%in" the res! t in the acc!m! ator$ S)== sets the carr# 4'orrow6 & a" i& a 'orrow is needed &or 'it 8@ and c ears C otherwise$ 4I& C was set 'e&ore eBec!tin" a S)== instr!ction@ this indicates that a 'orrow was needed &or the pre%io!s step in a m! tip e precision s!'traction@ so the carr# is s!'tracted &rom the acc!m! ator a on" with the so!rce operand6$ AC is set i& a 'orrow is needed &or 'it 1@ and c eared otherwise$ OV is set i& a 'orrow is needed into 'it 9 '!t not into 'it 8@ or into 'it 8 '!t not 'it 9$ When s!'tractin" si"ned inte"ers OV indicates a ne"ati%e n!m'er prod!ced when a ne"ati%e %a !e is s!'tracted &rom a positi%e %a !e or a positi%e res! t when a positi%e n!m'er is s!'tracted &rom a ne"ati%e n!m'er$ The so!rce operand a ows &o!r addressin" modes* re"ister@ direct@ re"ister indirect@ or immediate$ EBamp e* The acc!m! ator ho ds ,C-. 4//,,/,,/=6@ re"ister 0 ho ds 5+. 4,/,/,/,,=6@ and the carr# & a" is set$ The instr!ction S)== A@ R0

wi

ea%e the %a !e 8+. 4,///,/,,=6 in the acc!m! ator@ with the carr# & a" and AC

c eared '!t OV set$ Notice that ,C-. min!s 5+. is 85.$ The di&&erence 'etween this and the a'o%e res! t is d!e to the 4'orrow6 & a" 'ein" set 'e&ore the operation$ I& the state o& the carr# is not 7nown 'e&ore startin" a sin" e or m! tip e?precision s!'traction@ it sho! d 'e eBp icit # c eared '# a CLR C instr!ction$ SKQQ A, R& Operation* S)== 4A6 U 4A6 F 4C6 F 4Rn6 =#tes* / C#c es* / SKQQ A, !i ,3t Operation* S)== 4A6 U 4A6 F 4C6 F 4direct6 =#tes* 0 C#c es* / SKQQ A, R Ri Operation* S)== 4A6 U 4A6 F 4C6 F 44Ri66 =#tes* / C#c es* / SKQQ A, 2!"t" Operation* S)== 4A6 U 4A6 F 4C6 F Rdata =#tes* 0 C#c es* / Encodin"* / , , / , / , / direct address Encodin"* / , , / , / / i Encodin"* / , , / , / , , immediate data

SHAP A F!nction* Swap ni'' es within the acc!m! ator Description* SWA( A interchan"es the ow and hi"h?order ni'' es 4&o!r?'it &ie ds6 o& the acc!m! ator 4'its 1?, and 'its 8?+6$ The operation can a so 'e tho!"ht o& as a &o!r 'it rotate instr!ction$ No & a"s are a&&ected$ EBamp e* The acc!m! ator ho ds the %a !e ,C5. 4//,,,/,/=6$ The instr!ction SWA( A ea%es the acc!m! ator ho din" the %a !e 5C. 4,/,///,,=6$ Operation* SWA( 4A1?,6 4A8?+6@ 4A8?+6 U 4A1?,6 =#tes* / C#c es* / Encodin"* / / , , , / , , PCH A, 5b;t,7 F!nction* EBchan"e acc!m! ator with '#te %aria' e Description* IC. oads the acc!m! ator with the contents o& the indicated %aria' e@ at the same time writin" the ori"ina acc!m! ator contents to the indicated %aria' e$ The so!rce3destination operand can !se re"ister@ direct@ or re"ister?indirect addressin"$ EBamp e* R, contains the address 0,.$ The acc!m! ator ho ds the %a !e 1F. 4,,//////=6$ Interna RAM ocation 0,. ho ds the %a !e 85. 4,///,/,/=6$ The instr!ction IC. A@ LR, wi ea%e RAM ocation 0,. ho din" the %a !e 1F. 4,,////// =6 and 85. 4,///,/,/=6 in the acc!m! ator$ PCH A, R& Operation* IC. 4A6 4Rn6 =#tes* / C#c es* / PCH A, !i ,3t Operation* IC.

4A6 4direct6 =#tes* 0 C#c es* / Encodin"* / / , , / r r r Encodin"* / / , , , / , / direct address PCH A, R Ri Operation* IC. 4A6 44Ri66 =#tes* / C#c es* / Encodin"* / / , , , / / i PCHD A,RRi F!nction* EBchan"e di"it Description* IC.D eBchan"es the ow?order ni'' e o& the acc!m! ator 4'its 1?,@ "enera # representin" a heBadecima or =CD di"it6M with that o& the interna RAM ocation indirect # addressed '# the speci&ied re"ister$ The hi"h?order ni'' es 4'its 8? +6 o& each re"ister are not a&&ected$ No & a"s are a&&ected$ EBamp e* R, contains the address 0,.$ The acc!m! ator ho ds the %a !e 19. 4,,//,//,=6$ Interna RAM ocation 0,. ho ds the %a !e 85. 4,///,/,/=6$ The instr!ction IC.D A@ L R, wi ea%e RAM ocation 0,. ho din" the %a !e 89. 4,///,//,=6 and 15. 4,,//,/,/=6 in the acc!m! ator$ Operation* IC.D 4A1?,6 44Ri6 1?,6 =#tes* / C#c es* / Encodin"* / / , / , / / i PRI 5!,stMb;t,7, 5s 3Mb;t,7 F!nction* Lo"ica EBc !si%e OR &or '#te %aria' es

Description* IRL per&orms the 'itwise o"ica EBc !si%e OR operation 'etween the indicated %aria' es@ storin" the res! ts in the destination$ No & a"s are a&&ected$ The two operands a ow siB addressin" mode com'inations$ When the destination is the acc!m! ator@ the so!rce can !se re"ister@ direct@ re"ister?indirect@ or immediate addressin"M when the destination is a direct address@ the so!rce can 'e acc!m! ator or immediate data$ Not,L When this instr!ction is !sed to modi&# an o!tp!t port@ the %a !e !sed as the ori"ina port data wi 'e read &rom the o!tp!t data atch@ not the inp!t pins$ EBamp e* I& the acc!m! ator ho ds ,C1. 4//,,,,//=6 and re"ister , ho ds ,AA. 4/,/,/,/,=6 then the instr!ction IRL A@ R, wi ea%e the acc!m! ator ho din" the %a !e 9-. 4,//,/,,/=6$ When the destination is a direct # addressed '#te@ this instr!ction can comp ement com'inations o& 'its in an# RAM ocation or hardware re"ister$ The pattern o& 'its to 'e comp emented is then determined '# a mas7 '#te@ either a constant contained in the instr!ction or a %aria' e comp!ted in the acc!m! ator at r!n?time$ The instr!ction IRL (/@ R,,//,,,/= wi comp ement 'its 5@ +@ and , o& o!tp!t port /$ PRI A, R& Operation* IRL0 4A6 U 4A6 _ 4Rn6 =#tes* / C#c es* / Encodin"* , / / , / r r r PRI A, !i ,3t Operation* IRL 4A6 U 4A6 _ 4direct6 =#tes* 0 C#c es* / PRI A, R Ri

Operation* IRL 4A6 U 4A6 _ 44Ri66 =#tes* / C#c es* / PRI A, 2!"t" Operation* IRL 4A6 U 4A6 Rdata =#tes* 0 C#c es* / PRI !i ,3t, A Operation* IRL 4direct6 U 4direct6 _ 4A6 =#tes* 0 C#c es* / Encodin"* , / / , , / , / direct address Encodin"* , / / , , / / i Encodin"* , / / , , / , , immediate data Encodin"* , / / , , , / , direct address PRI !i ,3t, 2!"t" Operation* IRL 4direct6 U 4direct6 _ Rdata =#tes* 1 C#c es* 0 Encodin"* , / / , , , / / direct address immediate data I&st 43tio& S,t S4mm" ; A it+m,ti3 O=, "tio&s M&,mo&i3 D,s3 i=tio& Q;t, C;3l, ADD A@ Rn Add re"ister to acc!m! ator / / ADD A@ direct Add direct '#te to acc!m! ator 0 / ADD A@ LRi Add indirect RAM to acc!m! ator / /

ADD A@ data Add immediate data to acc!m! ator 0 / ADDC A@ Rn Add re"ister to acc!m! ator with carr# & a" / / ADDC A@ direct Add direct '#te to A with carr# & a" 0 / ADDC A@ LRi Add indirect RAM to A with carr# & a" / / ADDC A@ Rdata Add immediate data to A with carr# & a" 0 / S)== A@ Rn S!'tract re"ister &rom A with 'orrow / / S)== A@ direct S!'tract direct '#te &rom A with 'orrow 0 / S)== A@LRi S!'tract indirect RAM &rom A with 'orrow / / S)== A@ data S!'tract immediate data &rom A with 'orrow 0 / INC A Increment acc!m! ator / / INC Rn Increment re"ister / / INC direct Increment direct '#te 0 / INC LRi Increment indirect RAM / / DEC A Decrement acc!m! ator / / DEC Rn Decrement re"ister / / DEC direct Decrement direct '#te 0 / DEC LRi Decrement indirect RAM / / INC D(TR Increment data pointer / 0 M)L A= M! tip # A and = / + DIV A= Di%ide A '# = / + DA A Decima adj!st acc!m! ator / /

&ndQdata rBQinp!t rBQo!t o!t/ 7e# rBQdata or" ,,,,h jmp main

eE! eE! 'it 'it 'it eE!

(, (/ (1$0 (0$, (1$1 0+h

or" ,,,1h reti or" ,,,'h reti or" ,,/1h reti or" ,,/'h reti or" ,,01h reti main* mo% mo% mo% psw@R,,h sp@R,8,h tmod@R,,h

mo% mo% mo% mo% mo% mo% mo% mo% mo% mo% mo% mo% mainQ p/* mo% cjne mo% cr ca jmp nBt/Qrec%* cjne mo%

th,@R,,h t ,@R,,h th/@R,,h t /@R,,h tcon@R,,h scon@R,,h ie@R,,h ip@R,,h p,@R,&&h p/@R,&&h p0@R,&&h p1@R,&&h

a@rBQinp!t a@R/5d@nBt/Qrec% &ndQdata@R//,,,,,,' o!t/ de a# nBt5Qrec%

a@R8d@nBt0Qrec% &ndQdata@R/////,,/'

ca jmp nBt0Qrec%* cjne mo% ca jmp nBt1Qrec%* cjne mo% ca jmp nBt+Qrec%* cjne mo% set' ca jmp nBt5Qrec%* jn' jmp nBt/*

de a# nBt5Qrec%

a@R1d@nBt1Qrec% &ndQdata@R/,/,,/,,' de a# nBt5Qrec%

a@R/d@nBt+Qrec% &ndQdata@R/,//,,,,' de a# nBt5Qrec%

a@R,d@nBt5Qrec% &ndQdata@R/,,//,,/' o!t/ de a# nBt5Qrec%

7e#@nBt/ mainQ p/

mo% mo% mo% mo% mo% cjne mo% cr jmp nBt/Qrec%/* cjne mo% jmp nBt0Qrec%/* cjne mo% cp jmp nBt1Qrec%/* cjne mo% cp

a@rBQinp!t rBQdata@a a@R,&,h rBQinp!t@a a@rBQdata a@R/5d@nBt/Qrec%/ &ndQdata@R//,,,,,,' o!t/ eB/Qend

a@R8d@nBt0Qrec%/ &ndQdata@R/////,,/' eB/Qend

a@R1d@nBt1Qrec%/ &ndQdata@R/,/,,/,,' o!t/ eB/Qend

a@R/d@nBt+Qrec%/ &ndQdata@R/,//,,,,' o!t/

jmp nBt+Qrec%/* cjne mo% set' jmp eB/Qend* ca jn' ca jn' jmp DELA;* mo% mo% DEL* djn2 djn2 ret end

eB/Qend

a@R,d@eB/Qend &ndQdata@R/,,//,,/' o!t/ eB/Qend

de a# 7e#@eB/Qend de a# 7e#@eB/Qend mainQ p/

r,@R,d r/@R0,d

r,@DEL r/@DEL