Design and Implementation of Square and Cube Algorithm using Vedic Mathematics

CHAPTER 1 INTRODUCTION
Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate(MAC) and inner product are among some of the frequently used Computation- Intensive Arithmetic Functions(CIAF) currently implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors in its arithmetic and logic unit. Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. Currently, multiplication time is still the dominant factor in determining the instruction cycle time of a DSP chip. The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications. One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a subject of interest over decades. Reducing the time delay and power consumption are very essential requirements for many applications. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier.Minimizing power consumption for digital systems involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. Digital multipliers are the most commonly used components in any digital circuit design. They are fast, reliable and efficient components that are utilized to implement any operation. Depending upon the arrangement of the components, there are different types of multipliers available. Particular multiplier architecture is chosen based on the application. In many DSP algorithms, the multiplier lies in the critical delay path and ultimately determines the performance of algorithm. The speed of multiplication operation is of great importance in DSP as well as in general processor. In the past multiplication was implemented generally with a sequence of addition and shift operations.
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Design and Implementation of Square and Cube Algorithm using Vedic Mathematics The multiplier is a fairly large block of a computing system. The amount of circuitry involved is directly proportional to the square of its resolution i.e. A multiplier of size n bits has 2n gates. For multiplication algorithms performed in DSP applications latency and throughput are the two major concerns from delay perspective. Latency is the real delay of computing a function, a measure of how long the inputs to a device are stable is the final result available on outputs. Throughput is the measure of how many multiplications can be performed in a given period of time; multiplier is not only a high delay block but also a major source of power dissipation. Thats why if one also aims to minimize power consumption, it is of great interest to reduce the delay by using various delay optimizations. Digital multipliers are the core components of all the digital signal processors (DSPs) and the speed of the DSP is largely determined by the speed of its multipliers. Two most common multiplication algorithms followed in the digital hardware are array multiplication algorithm and Booth multiplication algorithm. The computation time taken by the array multiplier is comparatively less because the partial products are calculated independently in parallel. The delay associated with the array multiplier is the time taken by the signals to propagate through the gates that form the multiplication array. Booth multiplication is another important multiplication algorithm. Large booth arrays are required for high speed multiplication and exponential operations which in turn require large partial sum and partial carry registers. Thus, a large propagation delay is associated with this case. Due to the importance of digital multipliers in DSP, it has always been an active area of research. The process of raising a number to a power i.e., exponentiation is an important operation. The exponentiation operation, like square and cube plays a vital role in communication systems, signal processing applications, Finite Field arithmetic etc. The efficiency of these systems depends on how fast these operations are performed. Squaring and cubing are frequently performed functions in most of the DSP systems. Squaring and cubing are the special case of multiplication. Squaring and cubing circuits forms the heart of different DSP operations like Image Compression, Decoding, Demodulation, Adaptive Filtering, Least mean squaring, etc. Traditionally, these operations were performed using multipliers itself. But, as the radix of the number used for these
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Design and Implementation of Square and Cube Algorithm using Vedic Mathematics increases, the process becomes complicated which would result in increased delay and hence the power consumption. Squaring and cubing can be performed using ordinary multipliers, which are scalable but they have a larger delay. Structure based array implementation are faster but scalability increases design complexity as well as expense. Moreover, multipliers occupy large area, have long latency and consume considerable power. Therefore, which offer either of the following design targets- scalability, re-configurability, high speed, low power consumption, regularity of layout and less area or even a combination of some of these features are to be designed. Vedic mathematics is an ancient mathematics that has a unique technique of calculations based on simple rules and principles with which any mathematical problem can be solved. Vedic mathematics refers to the technique of calculations based on a set of 16 Vedic sutras or aphorisms, as algorithms and their upa-sutras or corollaries derived from these sutras. Any mathematical problems may be in algebra, arithmetic, geometry or trigonometry can be solved using these sutras. Vedic mathematics is more coherent than modern mathematics. Vedic mathematics offers a fresh and highly efficient approach to mathematics covering a wide range- starts with elementary multiplication and concludes with a relatively advanced topic, the solution of non-linear partial differential equations. But the Vedic scheme is not simply a collection of rapid methods it is a system, a unified approach. Vedic mathematics extensively exploits the properties of numbers in every practical application. In the present work we are using the Vedic sutras to compute the square and cube of the input number. To compute square we have made use of the Duplex property of Urdhava Triyakbyam Sutra. And to find the cube of the number Anurupya Sutra of Vedic mathematics is used. This approach of obtaining the square and cube of a number is fast and it is easy and simple to implement. The algorithm is built using the VERILOG hardware description language and synthesised and simulated in XILINX tool.
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Design and Implementation of Square and Cube Algorithm using Vedic Mathematics

CHAPTER 2 LITERATURE SURVEY

There are number of techniques that to perform binary multiplication. In general, the choice is based upon factors such as latency, throughput, area, and design complexity. More efficient parallel approach uses some sort of array or tree of full adders to sum partial products. Array Multiplier, Booth Multiplier and Wallace Tree Multipliers are some of the standard approaches to have hardware implementation of binary Multiplier which are suitable for VLSI implementation at CMOS level [5]. 2.1 Array Multiplier

Array Multiplier [6] is an efficient layout of combinational Multiplier. Multiplication of two binary numbers can be obtained with one micro-operation by using a combinational circuit that forms the product bit all at once thus making it a fast way of multiplying two numbers since only delay is the time for the signals through the gates that forms the multiplication array. Array Multiplier gives more power consumption as well as the optimum number of components required ,but delay for this Multiplier is larger .It also requires large number of gates because of which area is increased ;due to this array Multiplier is less economical .Thus ,it is a fast Multiplier but hardware complexity is high. The Array Multiplier design is shown in the below Fig.2.1
+ +

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Design and Implementation of Square and Cube Algorithm using Vedic Mathematics

: Partial product inputs. : Partial sum

: Output : Carry

+ : Adder element

Figure 2.1 4 x 4 Array Multiplier

2.2 Wallace Tree Multiplier

A fast process for multiplication of two numbers were developed which consists of a three step process of multiplying the two numbers [7] in which the bit products are formed, the bit product matrix is reduced to a two row matrix where sum of bit products and the resulting rows are summed with a fast adder to produce a final product. Three bit signals are passed to a one bit full adder (3W) which is called a three input Wallace tree circuit, and the output signal (sum signal) is supplied to the next stage full adder of the same bit, and the carry output signal thereof is passed to the next stage full adder of the same number of bit, and the carry output signal thereof is supplied to the next stage of the full adder located at a one bit higher position [5]. Wallace tree is a tree of carry-save adders arranged as shown in Fig.2.2. A carry save adder consists of full adders like the more familiar ripple adders, but the carry output from each bit is brought out to form second result vector rather being than wired to the next most significant bit. The carry vector is 'saved' to be combined with the sum later. In the Wallace tree method, the circuit layout is not easy although the speed of the operation is high since the circuit is quite irregular.

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Design and Implementation of Square and Cube Algorithm using Vedic Mathematics

Figure 2.2 4 x4 Wallace Tree Multiplier

2.3 Booth Multiplier

Another improvement in the Multiplier is by reducing the number of partial products generated .The booth recording Multiplier is one such Multiplier. It scans three bits at a time to reduce the number of partial products .these three bits are: the two bits from present pair; and a third bit from the higher order bit of an adjacent lower order pair. After examining each triplet of bits, the triplets are converted by Booth logic into a set of five controls used by the adder cells in the array to control the operations performed by the adder cells. To speed up multiplication booth encoding performs several multiplications at once. From basis of booth multiplication it can be proved that addition/subtraction operation can be skipped if the successive bits in the multiplicand are same. Thus in most cases the delay associated with booth Multiplier is smaller than that with array Multiplier .However the performance of Booth Multiplier for delay is input data dependant .In worst case the delay of the booth Multiplier is on par with array Multiplier. The high performance of booth Multiplier comes with the drawback of power consumption as it uses large number of adder cells required that consumes large power. The block diagram of Modified Booth Multiplier is shown in the below Fig.2.3.

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Design and Implementation of Square and Cube Algorithm using Vedic Mathematics

Figure 2.3 Booth Block Diagram

2.4 PROBLEM FORMULATION

The problems that are to be handled in this present work is 1. To reduce area and delay. 2. To minimize power consumption. 3. To design a Multiplier with regular in structure.

2.5 OBJECTIVE

The main objective of this work is to implement an Arithmetic unit which makes use of Vedic Mathematics algorithm for multiplication. The Arithmetic unit that has been made performs multiplication, addition, subtraction and Multiply Accumulate operations. The MAC unit, used in the Arithmetic module uses a fast multiplier, built with Vedic Mathematics Algorithm. Also, square and cube algorithms of Vedic Mathematics, to reduce the multiplications required
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Design and Implementation of Square and Cube Algorithm using Vedic Mathematics

CHAPTER 3 VEDIC SUTRAS

The term Vedic is derived from the word Veda which means the store-house of all knowledge. Vedic mathematics is mainly based on the 16 sutras dealing with various branches of mathematics like arithmetic, algebra, geometry etc., these sutras along with their brief meaning are listed below. 1. (Anurupye) Shunyamanyat If one is in ratio, the other is zero. 2. Chalana-Kalanabyham Differences and Similarities. 3. Ekadhikina Purvena By one more than the previous One. 4. Ekanyunena Purvena By one less than the previous one. 5. Gunakasamuchyah The factors of the sum is equal to the sum of the factors. 6. Gunitasamuchyah The product of the sum is equal to the sum of the product. 7. Nikhilam Navatashcaramam Dashatah All from 9 and last from 10. 8. Paraavartya Yojayet Transpose and adjust. 9. Puranapuranabyham By the completion or noncompletion. 10. Sankalana- vyavakalanabhyam By addition and by subtraction. 11. Shesanyankena Charamena The remainders by the last digit. 12. Shunyam Saamyasamuccaye When the sum is the same that sum is zero. 13. Sopaantyadvayamantyam The ultimate and twice the penultimate. 14. Urdhva-tiryakbhyam Vertically and crosswise. 15. Vyashtisamanstih Part and Whole. 16. Yaavadunam Whatever the extent of its deficiency

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Design and Implementation of Square and Cube Algorithm using Vedic Mathematics 3.1 IMPLEMENTATION OF SQUARE ALGORITHM In order to calculate the square of a number Duplex D property of Urdhva Triyakbhyam is used. In the Duplex, we take twice the product of the outermost pair and then add twice the product of the next outermost pair and so on till no pairs are left. When there are odd numbers of bits in the original sequence, there is one bit left by itself in the middle and this enters as its square.

The Duplex property can be explained as follows: For a 1 bit number D is its square. For a 2 bit number D is twice their product For a 3 bit number D is twice the product of the outer pair + square of the middle bit. For a 4 bit number D is twice the product of the outer pair + twice the product of the inner pair. Let us consider how to obtain the square of a two bit number:

X1 X0 X1 X0 P3 P2 P1 P0

Where P0 = D(X0) = X02 P1 = D(X1 X0) = 2*X1*X0 P2 = D(X1) = X12

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Design and Implementation of Square and Cube Algorithm using Vedic Mathematics Thus in order to obtain the square of 8 bit number we partition the number into two parts as shown below:

A7 A6 A5 A4 X1

A3 A2 A1 A0 X0

Then to the above apply the algorithm. Thus in general to obtain the square of an N bit numbers following steps are performed: 1. The given N bit input is partitioned into two parts, each part is treated as a separate unit. 2. Find the square of each part. 3. Find twice the product of the two. 4. Add the above results to get the final result. 5. Algebraically the above algorithm can be put as (a+b)2 = a2 +2ab +b2

Consider an example to obtain the square of a 4 bit number 1234 In the above example X1 = 12 and X0 = 34 X12 = (12)2 = 144 X02 = (34)2 = 1156 2*X1*X0 = 2* 12* 34 = 816 Thus (1234)2 = 1156 816 144 1522756

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Design and Implementation of Square and Cube Algorithm using Vedic Mathematics

Block diagram for square architecture

Figure 3.1 Block diagram for square architecture

Thus for a 8 bit input to find the square using Vedic algorithm we need three 4 bit multipliers.

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Design and Implementation of Square and Cube Algorithm using Vedic Mathematics 3.2 IMPLEMENTATION OF CUBE ALGORITHM

The cube of the number is based on the Anurupya sutra of Vedic mathematics which states if you start with the cube of the first digit and take the next three numbers in the top row in the geometrical proportion in the ratio of the original digits themselves you will find that the fourth figure on the right end is just the cube of the second digit. Consider an example to find (11)3 1. The first thing one has to do is to put down the cube of the first digit in a row of 4 figures in a geometrical ratio in the exact proportion subsisting between them. 2. The second step is to put down under the second and third numbers, just two times the said numbers themselves and add up. Thus, (11)3 = 1 1 1 1 22 1331

The algebraic explanation for the algorithm is as follows: If a and b are the two digits, then according to the Anurupya sutra

a3 + a2 b + a b2 + b 2a2 b + 2 a b2 a3 + 3a2 b + 3 a b2 + b3 = (a+b)3

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Design and Implementation of Square and Cube Algorithm using Vedic Mathematics

Block diagram for cube architecture

Figures 3.2 Block diagram for cube architecture

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Design and Implementation of Square and Cube Algorithm using Vedic Mathematics 3.3 TYPES OF MULTIPLIERS Multipliers can be broadly classified into structure based and algorithm based multipliers. Again structure based multipliers can be of regular and irregular structured multipliers like array multipliers, Wallace tree and Dadda tree multipliers. As we have seen for both squaring and cube algorithms multipliers are to be employed. In the present we have chosen array multiplier and Wallace tree multiplier for square circuit and a comparison is made between them. For the cube circuit we have made use of Wallace tree multiplier and the performance is analysed. Array multipliers Array multipliers can be implemented by directly mapping the manual multiplication into hardware. The basic building block of an array multiplier is a full adder. For an N bit unsigned array multiplier the number of full adders required is N*(N-1). Array multipliers are very slow as their critical path is very long. The main advantage of these multipliers is the regular structure, which leads to ease of layout and design.

Wallace tree multipliers C.S.Wallace propounded a fast technique to perform multiplication in 1964. A Wallace tree multiplier offers faster performance for large operands. Unlike an array multiplier the partial product matrix for a Wallace tree multiplier is rearranged in a tree like format, reducing both the critical path and the number of adder cells needed. The Wallace tree multipliers belong to the family of multipliers called column compression multipliers. The underlying principle in this family of multipliers is to achieve partial product accumulation by successively reducing the number of bits of information in each column using full adders or half adders. The full adder is known as a (3:2) compressor because of its ability to add 3 bits from the single column of partial product matrix and output 2 bits 1 bit in the same column and 1 bit in the next column of the output matrix. The half adder is known as a (2:2) compressor
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Design and Implementation of Square and Cube Algorithm using Vedic Mathematics because of its ability to take 2 bits from a single column of the partial product matrix and output 2 bits, 1 bit in the same column and 1 bit in the next column of the output matrix. The Wallace tree consists of numerous levels of such column compression structures until finally, only two full width operands remain. These two operands can be added using fast carry propagate adder to obtain the final result.

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Design and Implementation of Square and Cube Algorithm using Vedic Mathematics

CHAPTER 4 EXPERIMENTAL RESULT

4.1 Simulation result for square algorithm

Figure 4.1 Simulation waveform of square algorithm using Wallace tree multiplier

Figure 4.2 Timing Constraints of square algorithm using Wallace tree multiplier

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Design and Implementation of Square and Cube Algorithm using Vedic Mathematics

Figure 4.3 Simulation waveform of square algorithm using Array multiplier

Figure 4.4 Timing Constraints of square algorithm using Array multiplier

4.2 Comparison results between Wallace tree and array multiplier

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Design and Implementation of Square and Cube Algorithm using Vedic Mathematics

4.3 Simulation result for cube algorithm

Figure 4.5 Simulation waveform of Cube algorithm using Wallace tree multiplier

Figure 4.6 Timing Constraints of square algorithm using Wallace tree multiplier

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Design and Implementation of Square and Cube Algorithm using Vedic Mathematics

CHAPTER 5 CONCLUSION
It is evident from the results that implementation of Vedic square algorithm using Wallace tree multiplier is better than that of using array multiplier in terms of power and area. Also Vedic mathematics approach of obtaining square and cube is faster and the power consumption is also reduced due to parallel computation. There is an overwhelming need to explore Vedic algorithms in detail so as to verify its applicability in different domains of engineering.

FUTURE WORK
Vedic Mathematics, developed about 2500 years ago, gives us a clue of symmetric computation. Vedic mathematics deals with various topics of mathematics such as basic arithmetic, geometry, trigonometry, calculus etc. All these methods are very efficient as far as manual calculations are concerned. If all those methods effectively implement hardware, it will reduce the computational speed drastically. Therefore, it could be possible to implement a complete ALU using all these methods using Vedic mathematics methods. By using these ancient Indian Vedic mathematics methods world can achieve new heights of performance and quality for the cutting edge technology devices.

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Design and Implementation of Square and Cube Algorithm using Vedic Mathematics

REFERENCES
1. M.Ramalatha, K.Deena Dayalan, P.Dharani, A Novel Time And Energy Efficient Cubing Circuit Using Vedic Mathematics For Finite Field Arithmetic June 2012. 2. Himanshu Thapliyal, Saurabh Kotiyal and M.B Srinivas, Design and Analysis of A Novel Parallel Square and Cube Architecture Based On Ancient Indian Vedic Mathematics May 2011. 3. Chandra Mohan Umapathy, High Speed Squarer July 2006.

4. Jagadguru Swami Sri Bharati Krsna Tirthaji Maharaja, Vedic Mathematics July 2003. 5. Sumit Vaidya, Deepak Dandekar, Delay-Power Performance Comparison Of Multipliers In Vlsi Circuit Design, International Journal of Computer Networks & Communications (IJCNC), Vol.2, No.4, July 2010. 6. M. M. Mano, Computer System Architecture. Englewood Cliffs, NJ:PrenticeHall, 1982.

7. GensukeGoto,High Speed Digital Parallel Multiplier, United States Patent5,465,226, November 7 1995. A.D. Booth, A Signed Binary

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