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ISOLATED 5-V FULL AND HALF-DUPLEX RS-485 TRANSCEIVERS

Check for Samples: ISO3080, ISO3086 ISO3082, ISO3088
1

FEATURES
4000-VPEAK Isolation, 560-Vpeak VIORM UL 1577, IEC 60747-5-2 (VDE 0884, Rev. 2), IEC 61010-1, IEC 60950-1 and CSA Approved Bus-Pin ESD Protection 16 kV HBM Between Bus Pins and GND2 6 kV HBM Between Bus Pins and GND1 1/8 Unit Load Up to 256 Nodes on a Bus Meets or Exceeds TIA/EIA RS-485 Requirements Signaling Rates up to 20 Mbps Thermal Shutdown Protection Low Bus Capacitance 16 pF (Typ) 50 kV/s Typical Transient Immunity Fail-safe Receiver for Bus Open, Short, Idle 3.3-V Inputs are 5-V Tolerant

APPLICATIONS
Security Systems Chemical Production Factory Automation Motor/Motion Control HVAC and Building Automation Networks Networked Security Stations
ISO3080 ISO3086 ISO3082 ISO3088 Full-Duplex Full-Duplex Half-Duplex Half-Duplex 200 kbps 20 Mbps 200 kbps 20 Mbps

DESCRIPTION
The ISO3080, and ISO3086 are isolated full-duplex differential line drivers and receivers while the ISO3082, and ISO3088 are isolated half-duplex differential line transceivers for TIA/EIA 485/422 applications. These devices are ideal for long transmission lines since the ground loop is broken to allow for a much larger common-mode voltage range. The symmetrical isolation barrier of the device is tested to provide 2500 Vrms of isolation for 60s between the bus-line transceiver and the logic-level interface. Any cabled I/O can be subjected to electrical noise transients from various sources. These noise transients can cause damage to the transceiver and/or near-by sensitive circuitry if they are of sufficient magnitude and duration. These isolated devices can significantly increase protection and reduce the risk of damage to expensive control circuits. The ISO3080, SO3082, ISO3086 and ISO3088 are qualified for use from 40C to 85C.
ISO3080, ISO3086
DW PACKAGE
Vcc1 GND1 R RE DE D GND1 GND1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Vcc2 GND2 A B Z Y GND2 GND2
R

ISO3082, ISO3088
DW PACKAGE
Vcc1 GND1 R RE DE D GND1 GND1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9

function diagram
GALVANIC ISOLATIO N
14 13 A B Z Y

function diagram
5 Vcc2 DE GND2 nc 6 D B 3 A R 4 nc RE GND2
GALVANIC ISOLATION

RE DE 5

3 4

13 12

B A

12 11

GND2

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ABSOLUTE MAXIMUM RATINGS (1)

VALUE VCC VO VIT VI IO Input supply voltage,
(2)

UNIT V V V V mA kV

VCC1, VCC2

0.3 to 6 9 to 14 50 to 50 0.5 to 7 10 Bus pins and GND1 6 16 4 1 200 150 JEDEC Standard 22, Test Method A114-C.01 JEDEC Standard 22, Test Method C101 ANSI/ESDS5.2-1996 Bus pins and GND2 All pins

Voltage at any bus I/O terminal Voltage input, transient pulse, A, B, Y, and Z (through 100, see Figure 11) Voltage input at any D, DE or RE terminal Receiver output current Human Body Model

ESD

Electrostatic discharge

Charged Device Model Machine Model

All pins

kV V C

TJ (1) (2)

Maximum junction temperature

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values

RECOMMENDED OPERATING CONDITIONS

MIN VCC1 VCC2 VOC VIH VIL VID RL IO TJ (1) Logic-side supply voltage Bus-side supply voltage (1) Voltage at either bus I/O terminal High-level input voltage Low-level input voltage Differential input voltage Differential input resistance Output current Operating junction temperature Driver Receiver A, B D, DE, RE A with respect to B
(1)

TYP 5

MAX 5.5 5.5 12 VCC 0.8 12

UNIT V V V V V

3.15 4.5 7 2 0 12 54 60 8 40 60

60 8 85

mA C

For 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For 3-V operation, VCC1 is specified from 3.15 V to 3.6V.

SUPPLY CURRENT
over recommended operating condition (unless otherwise noted)
PARAMETER ICC1 ICC2 Logic-side supply current Bus-side supply current TEST CONDITIONS RE at 0 V or VCC, DE at 0 V or VCC1 RE at 0 V or VCC, DE at 0 V or VCC1 RE at 0 V or VCC, DE at 0 V, No load 3.3-V VCC1 5-V VCC1 MIN TYP MAX 8 10 15 UNIT mA mA

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DRIVER ELECTRICAL CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS IO = 0 mA, no load | VOD | Differential output voltage magnitude RL = 54 , See Figure 1 RL = 100 (RS-422), See Figure 1 Vtest from 7 V to +12 V, See Figure 2 |VOD| VOC(SS) VOC(SS) VOC(pp) II Change in magnitude of the differential output voltage Steady-state common-mode output voltage Change in steady-state common-mode output voltage Peak-to-peak common-mode output voltage Input current See Figure 1 and Figure 2 MIN 3 1.5 2 1.5 0.2 1 See Figure 3 0.1 0.5 10 10 0 2.6 0.2 3 0.1 V V TYP 4.3 2.3 2.3 MAX VCC V UNIT

See Figure 3 D, DE, VI at 0 V or VCC1 ISO3082 ISO3088 See receiver input current VY or VZ = 12 V, VCC = 0 V or 5 V, DE = 0 V VY or VZ = 7 V. VCC = 0 V or 5 V, DE = 0 V

V A

IOZ

High-impedance state output current

1 Other input at 0 V 1 Other input at 0 V A

ISO3080 ISO3086

IOS CMTI

Short-circuit output current

VA or VB at 7 V VA or VB at 12 V

200 25 50

200

mA kV/s

Common-mode transient immunity VI = VCC1 or 0 V, See Figure 12

DRIVER SWITCHING CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)
PARAMETER tPLH, tPHL PWD (1) tr, tf Propagation delay Pulse skew (|tPHL tPLH|) Differential output signal rise and fall time Propagation delay, high-impedance-to-high-level ouput Propagation delay, high-impendance-to-low-level output Propagation delay, high-level-to-high-impedance output Propagaitin delya, low-level to high-impedance output ISO3080/82 ISO3086/88 ISO3080/82 ISO3086/88 ISO3080/82 ISO3086/88 ISO3080/82 ISO3086/88 ISO3080/82 ISO3086/88 50% Vo 90% Vo See Figure 5 and Figure 6, DE at 0 V See Figure 4 0.5 TEST CONDITIONS MIN TYP 0.7 25 20 3 0.9 7 2.5 1.8 25 95 25 55 225 55 ns MAX 1.3 45 200 7.5 1.5 15 7 UNIT ns ns s ns s

tPZH, tPZL

tPHZ, tPLZ (1)

Also known as pulse skew

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RECEIVER ELECTRICAL CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)
PARAMETER VIT(+) VIT() Vhys VOH Positive-going input threshold voltage Negative-going input threshold voltage Hysteresis voltage (VIT+ VIT) High-level output voltage VID = 200 mV, IO = 8 mA, See Figure 7 VID = 200 mV, IO = 8 mA, See Figure 7 3.3-V VCC1 5-V VCC1 3.3-V VCC1 5-V VCC1 1 0.04 Other input at 0 V 0.06 0.1 0.05 10 10 48 7 0.04 0.03 10 10 A A k pF VCC10.4 4 IO = 8 mA IO = 8 mA 200 TEST CONDITIONS MIN TYP 85 115 30 3.1 4.8 0.15 0.15 0.4 0.4 1 0.1 0.13 mA V A MAX 10 UNIT mV mV mV V

VOL IO(Z)

Low-level output voltage

High-impedance state output current VI = 7 to 12 V, Other input = 0 V VA or VB = 12 V VA or VB = 12 V, VCC = 0 VA or VB = 7 V VA or VB = 7 V, VCC = 0 VIH = 2 V VIL = 0.8 V A, B Test input signal is a 1.5 MHz sine wave with 1Vpp amplitude. CD is measured across A and B.

II

Bus input current

IIH IIL RID CD

High-level input current, RE Low-level input current, RE Differential input resistance Differential input capacitance

RECEIVER SWITCHING CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)
PARAMETER tPLH, tPHL PWD tr, tf tPZH, tPZL tPHZ, tPLZ (1)
(1)

TEST CONDITIONS See Figure 8 See Figure 9, DE at 0 V See Figure 10, DE at 0 V

MIN

TYP 90 4 1

MAX 125 12

UNIT

Propagation delay Pulse width distortion |tPHL tPLH| Output signal rise and fall time Propagation delay, high-level-to-high-impedance output Propagation delay, high-impedance-to-high-level output Propagation delay, high-impedance-to-low-level output Propagation delay, low-level-to-high-impedance output

ns ns

22 22

ns ns

lso known as pulse skew.

PARAMETER MEASUREMENT INFORMATION

VCC1 DE A 0 or VCC1
II

VCC2

IOA
DE A 375 W + VOD 60 W D B

B GND 1 VI GND 2 IOB

VOD

0 or3 V

-7 V to12 V

GND 1

VOB GND 2

VOA

GND 2

375 W

Figure 1. Driver VOD Test and Current Definitions

Figure 2. Driver VOD With Common-Mode Loading Test Circuit

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PARAMETER MEASUREMENT INFORMATION (continued)

VCC1 DE A Input
II

I OA

27 W A VOD B VB VA

B GND1 VI GND2 I OB VOB GND1 GND2

27 W VOC VOA V OC Input VOC(p-p)

Generator : PRR= 100 kHz, 50 % duty cycle, t r < 6ns , t f < 6 ns , ZO = 50 W

VOC(SS)

Figure 3. Test Circuit and Waveform Definitions For The Driver Common-Mode Output Voltage
VCC1 DE A D Input Generator B VI 50 W GND 1 VOD CL = 50 pF RL = 54 W 20% 1% VI tPLH VOD 50 % 10% tr 50% tPHL 90% 90% 50% 3V

VOD(H) 50 % 10% VOD(L)

Generator : PRR = 100 kHz, 50 % duty cycle, t r < 6ns , t f <6 ns , ZO = 50

C L includes fixture and instrumentation capacitance

tf

Figure 4. Driver Switching Test Circuit and Voltage Waveforms

3 V if testing A output , 0 V if testing B output 3 V or 0 V D DE Input V Generator I GND 1
Generator PRR = 50 kHz, 50% duty cycle, tr <6ns, tf <6ns, ZO = 50 W

3V S1 VO VI tPZH 90% VO 50% tPHZ ~0 V ~ 50% 50% 0V RL = 110 W 1% VOH

50 W

CL = 50 pF 20% CL includes fixture and instrumentation capacitance

Figure 5. Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms

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PARAMETER MEASUREMENT INFORMATION (continued)

3V
0 V if testing A output , 3 V if testing B output

A S1 D

RL = 110 W 1% VI 50% tPZL VO 50% 10% 50%

3V

3 V or 0 V B DE Input Generator CL = 50 pF 20% VI 50 W

CL includes fixture and instrumentation capacitance GND 2

0V tPLZ 5V

VOL

Generator: PRR =50 kHz ,50% duty cycle, t r< 6ns, t < 6ns, Z = 50 f

Figure 6. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveform
IA A R VA VA+ VB 2 VIC VB VID B IB VO IO

Figure 7. Receiver Voltage and Current Definitions

A Input Generator VI 50 W 1.5 V B RE R VO CL = 15 pF 20%
CL includes fixture and instrumentation capacitance

3 V VI tPLH VO 50% tr 50% tPHL 90% 50% 10% tf V OH 50% 0 V

Generator: PRR=100 kHz, 50% duty cycle, t < 6ns, t < 6ns, ZO = 50 W r f

V OL

Figure 8. Receiver Switching Test Circuit and Waveforms

VCC R VO B RE 1 kW 1% 3V S1 VI 50% tPZH VO VI 50 W
Generator:PRR=100 kHz, 50% duty cycle , t r<6ns, t f <6ns, Z O = 50 W

1.5 V

50% t pHZ 90% 50% 0V

0V

CL = 15 pF 20 %
CL includes fixture and instrumentation capacitance

V OH

Input Generator

Figure 9. Receiver Enable Test Circuit and Waveforms, Data Output High

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PARAMETER MEASUREMENT INFORMATION (continued)

A R VO B RE 1 kW 1% S1
CL includes fixture and instrumentation capacitance

VCC VI 50% 50%

0V

3V

1.5 V

CL = 15 pF 20% tPZL 50% 10% tPLZ

0V VCC V O

Input Generator

VI

50 W
Generator: PRR =100 kHz, 50% dutycycle, tr< 6 ns, t f < 6ns, ZO= 50 W

VOL

Figure 10. Receiver Enable Test Circuit and Waveforms, Data Output Low
0V A B
Pulse Generator 15 ms duration 1% duty cycle tr, tf 100 ns

RE R

100 W 1% + _ D

DE 3V
Note:This test is conducted to test survivability only. Data stability at the R output is not specified.

Figure 11. Transient Over-Voltage Test Circuit

2V C = 0.1 mF 1% VCC1 DE GND1 S1 B D VCC2 A C = 0.1 mF 1%

54 W

VOH or VOL

0.8 V R VOH or VOL 1 kW RE GND1 CL = 15 pF

(includes probe and jig capacitance)

GND2

V TEST

Figure 12. Half-Duplex Common-Mode Transient Immunity Test Circuit

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PARAMETER MEASUREMENT INFORMATION (continued)

2V C = 0.1 mF 1% VCC1 DE GND1 S1 B Y D 54 W VOH or VOL VCC2 A C = 0.1 mF 1%

0.8 V

1.5 V or 0 V 54 W

VOH or VOL

RE 1 kW GND1 CL = 15 pF
(includes probe and jig capacitance)

Z GND2

0 V or 1.5 V

VTEST

Figure 13. Full-Duplex Common-Mode Transient Immunity Test Circuit

DEVICE INFORMATION
Table 1. Driver Function Table
VCC1 VCC2 INPUT (D) ENABLE INPUT (DE) Y PU PU PU PU PU PD PU PD PU PU PU PU PU PU PD PD H L X X OPEN X X X H H L OPEN H X X X H L Z Z H Z Z Z OUTPUTS Z L H Z Z L Z Z Z

Table 2. Receiver Function Table

VCC1 PU PU PU PU PU PU 8 VCC2 PU PU PU PU PU PU DIFFERENTIAL INPUT VID = (VA VB) 0.01 V VID 0.2 V < VID < 0.01 V VID 0.2 V X X Open circuit ENABLE (RE) L L L H OPEN L OUTPUT (R) H ? L Z Z H

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Table 2. Receiver Function Table (continued)

VCC1 PU PU PD PU VCC2 PU PU PU PD DIFFERENTIAL INPUT VID = (VA VB) Short Circuit Idle (terminated) bus X X ENABLE (RE) L L X L OUTPUT (R) H H Z H

PACKAGE CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER L(I01) L(I02) CTI
(1)

TEST CONDITIONS Shortest terminal to terminal distance through air Shortest terminal to terminal distance across the package surface DIN IEC 60112 / VDE 0303 Part 1 Distance through the insulation Input to output, VIO = 500 V, all pins on each side of the barrier tied together creating a two-terminal device VI = 0.4 sin (4E6t) VI = 0.4 sin (4E6t)

MIN 8.34 8.1 175 0.008

TYP

MAX

UNIT mm mm V mm

Minimum air gap (Clearance) Minimum external tracking (Creepage) Tracking resistance (Comparative Tracking Index) Minimum Internal Gap (Internal Clearance)

RIO CIO CI (1)

Isolation resistance Barrier capacitance Input to output Input capacitance to ground

>1012 2 2

pF pF

Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance. Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.

IEC 60664-1 RATINGS TABLE

PARAMETER Basic isolation group Installation classification TEST CONDITIONS Material group Rated mains voltage 150 VRMS Rated mains voltage 300 VRMS Rated mains voltage 400 VRMS SPECIFICATION IIIa I-IV I-III I-II

IEC 60747-5-2 INSULATION CHARACTERISTICS

(1)

over recommended operating conditions (unless otherwise noted)

PARAMETER VIORM VPR VIOTM RS Maximum working insulation voltage Input to output test voltage Transient overvoltage Insulation resistance Pollution degree (1) Climatic Clasification 40/125/21 Method b1, VPR = VIORM 1.875, 100% Production test with t = 1 s, Partial discharge < 5 pC t = 60 s VIO = 500 V at TS TEST CONDITIONS SPECIFICATION 560 1050 4000 >10 2
9

UNIT V V V

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REGULATORY INFORMATION
VDE Certified according to IEC 60747-5-2 File Number: 40016131 (1) CSA Approved under CSA Component Acceptance Notice File Number: 1698195 UL Recognized under 1577 Component Recognition Program (1) File Number: E181974

Production tested 3000 VRMS for 1 second in accordance with UL 1577.

IEC SAFETY LIMITING VALUES

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER IS TS Safety input, output, or supply current Maximum case temperature DW-16 DW-16 JA = 212C/W, VI = 5.5 V, TJ = 170C, TA = 25C MIN TYP MAX 210 150 UNIT mA C

The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Characteristics table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages and is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

THERMAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER JA JB JC PD (1) Junction-to-Air Junction-to-Board Thermal Resistance Junction-to-Case Thermal Resistance Device Power Dissipation VCC1 = VCC2 = 5.25 V, TJ = 150C, CL = 15 pF, Input a 20 MHz 50% duty cycle square wave TEST CONDITIONS Low-K Thermal Resistance (1) High-K Thermal Resistance MIN TYP MAX 168 96.1 61 48 220 UNIT C/W C/W C/W mW

Tested in accordance with the Low-K or High-K thermal metric defintions of EIA/JESD51-3 for leaded surface mount packages.

10

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150

125

Safety Limiting Current -- mA

VCC1,2 at 5.5 V

100

75

50

25

0 0 50 100 150 TC - Case Temperature - C 200

Figure 14. DW-16 JC Thermal Derating Curve per IEC 60747-5-2

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EQUIVALENT CIRCUIT SCHEMATICS

D and RE Input VCC1 VCC1 DE Input VCC1

VCC1

VCC1

1 MW Input 500 W Input 500 W

1 MW

A Input VCC 16 V 180 kW Input 16 V 36 kW Input 36 kW 16 V

B Input VCC 36 kW

180 kW 36 kW 16 V

Y and Z Outputs VCC 16 V Output 16 V

3.3V R Output VCC1 VCC1

5V R Output

4W

5.5 W

6.4 W

11 W

12

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REVISION HISTORY
Changes from Original (May 2008) to Revision A Page

Changed the Package Characteristics table - L(101) Minimum air gap (Clearance) From 7.7mm To 8.34mm .................. 9 Deleted the CSA column from the Regulatory Information Table. ..................................................................................... 10 Changed the file number in the VDE column of the Regulatory Information table From: 40014131 To: 40016131 .......... 10

Changes from Revision A (June 2008) to Revision B

Page

Changed Features bullet From: 4000-VPEAK Isolation, To: 4000-VPEAK Isolation,, 560-VPEAK VIORM ..................................... 1 Added Features sub bullet: UL 1577, IEC 60747-5-2 (VDE 0884, Rev. 2), IEC 61010-1, IEC 60950-1 and CSA Approved ............................................................................................................................................................................... 1 Added the CSA column to the Regulatory Information table .............................................................................................. 10

Changes from Revision B (December 2008) to Revision C

Page

Changed Recommended Operatings Condition table note From: For 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6V. To: For 3-V operation, VCC1 is specified from 3.15 V to 3.6V. ..................................................................... 2

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11-Apr-2013

PACKAGING INFORMATION
Orderable Device ISO3080DW ISO3080DWG4 ISO3080DWR ISO3080DWRG4 ISO3082DW ISO3082DWG4 ISO3082DWR ISO3082DWRG4 ISO3086DW ISO3086DWG4 ISO3086DWR ISO3086DWRG4 ISO3088DW ISO3088DWG4 ISO3088DWR ISO3088DWRG4 Status
(1)

Package Type Package Pins Package Drawing Qty SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 40 40 2000 2000 40 40 2000 2000 40 40 2000 2000 40 40 2000 2000

Eco Plan
(2)

Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU

MSL Peak Temp

(3)

Op Temp (C) -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85

Top-Side Markings
(4)

Samples

ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE

Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR

ISO3080 ISO3080 ISO3080 ISO3080 ISO3082 ISO3082 ISO3082 ISO3082 ISO3086 ISO3086 ISO3086 ISO3086 ISO3088 ISO3088 ISO3088 ISO3088

(1)

The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. Addendum-Page 1

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11-Apr-2013

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com 26-Oct-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins Type Drawing SOIC SOIC SOIC SOIC DW DW DW DW 16 16 16 16

SPQ

Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 330.0 330.0 330.0 16.4 16.4 16.4 16.4 10.75 10.75 10.75 10.75

B0 (mm) 10.7 10.7 10.7 10.7

K0 (mm) 2.7 2.7 2.7 2.7

P1 (mm) 12.0 12.0 12.0 12.0

W Pin1 (mm) Quadrant 16.0 16.0 16.0 16.0 Q1 Q1 Q1 Q1

ISO3080DWR ISO3082DWR ISO3086DWR ISO3088DWR

2000 2000 2000 2000

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 26-Oct-2013

*All dimensions are nominal

Device ISO3080DWR ISO3082DWR ISO3086DWR ISO3088DWR

Package Type SOIC SOIC SOIC SOIC

Package Drawing DW DW DW DW

Pins 16 16 16 16

SPQ 2000 2000 2000 2000

Length (mm) 367.0 367.0 367.0 367.0

Width (mm) 367.0 367.0 367.0 367.0

Height (mm) 38.0 38.0 38.0 38.0

Pack Materials-Page 2

IMPORTANT NOTICE
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