ADAPTIVE FILTER FOR NOISE CANCELLATION

MINI PROJECT (LAB) REPORT Submitted in partial fulllment of the requirements for the award of M.Tech Degree in Electronics and Communication Engineering (Signal Processing) of the University of Kerala

Submitted by LINZ MATHEW First Semester M.Tech, Signal Processing

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING COLLEGE OF ENGINEERING TRIVANDRUM 2011

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING COLLEGE OF ENGINEERING TRIVANDRUM

CERTIFICATE

This is to certify that this mini project report entitled Adaptive Filter for Noise Cancellation is a bonade record of the work done by Lnz Mathew, under our guidance towards partial fulllment of the requirements for the award of Master of Technology Degree in Electronics and Communication Engineering (Signal Processing), of the University of Kerala during the year 2012.

Mr. Pradeep R. Associate Professor Dept. of ECE CET (Project Guide)

Prof. J. David Professor Dept. of ECE CET (Head of the Department)

ACKNOWLEDGEMENTS
I would like to express my sincere gratitude and heartful indebtedness to my guide Mr. Pradeep R., Associate Professor, Department of Electronics and Communication Engineering for his valuable guidance and encouragement in pursuing this project.

I am thankful to Prof. J. David, Head of the Department and Dr. Jiji C.V., P.G Co-ordinator , Department of Electronics and Communication Engineering for their help and support.

I also extend my hearty gratitude to Mr. Pradeep R. and for providing necessary facilities and his sincere co-operation. My sincere thanks are extended to all the teachers of the department of ECE and to all my friends for their help and support.

Linz Mathew

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ABSTRACT
An adaptive lter is a self-designing system that relies for its operation on a recursive algorithm, which makes it possible for the lter to perform satisfactorily in an environment where knowledge of the relevant statistics is not available. Adaptive lters are classied into two main groups: linear and non linear. Linear adaptive lters compute an estimate of a desired response by using a linear combination of the available set of observables applied to the input of the lter. Otherwise, the adaptive lter is said to be nonlinear.Adaptive lters nd applications in highly diverse elds: channel equalization, system identication, predictive deconvolution, spectral analysis, signal detection, noise cancellation, and beamforming.In this proposed project the application of the LMS criterion to cancel an undesirable sinusoidal noise is to be implemented. Here LMS criterion is to be used in an adaptive FIR lter.

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TABLE OF CONTENTS

INTRODUCTION ADAPTIVE LMS ALGORITHM

2.1 2.2 The Filtering Process . . . . . . . . . . . . . . . . . . . . . . . . . The Adaptive Process . . . . . . . . . . . . . . . . . . . . . . . . .

2 2 3

HARDWARE AND SOFTWARE PLATFORM

3.1 3.2 Hardware Platform-DSK 6416 . . . . . . . . . . . . . . . . . . . . Software Platform-Code composer Studio . . . . . . . . . . . . . .

4 4 5

CIRCUIT DIAGRAM
4.1 4.2 Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit Diagram Description . . . . . . . . . . . . . . . . . . . . .

7 7 7

PROGRAM CODE RESULT

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LIST OF FIGURES
1.1 4.1 6.1 General scheme for an adaptive lter. . . . . . . . . . . . . . . . . Circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . Correpted and Filtered signal . . . . . . . . . . . . . . . . . . . . . 1 7 11

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CHAPTER 1
INTRODUCTION

Communications systems development increases considerably obtaining more troubles as additive noise, signal interference and echo, therefore errors in data transmission are generated, but adaptive lter is an option to reduce these channel effects. Adaptive lters are systems with four terminals as showed in Fig 1., where x is the input signal, d is the wished signal, y is output signal lter and e is the output lter error.

Figure 1.1: General scheme for an adaptive lter. Adaptive lters design technique may be digital, analog or mixed. Every technique presents advantages and disadvantages, for example, analog adaptive lters are very fast, but offset avoids to get the least error . Digital lters are slow but precise, because is necessary the use of a lot of components, due to oating point operations . Mixed design (analog and digital), offers a good compromise between precision and speed, but VLSI (Very Large Scale Integration) design is more complicated , because is necessary to separate analog and digital components inside the chip. In this project a noise canceller employing a modied LMS (Least Mean Square) adaptive algorithm is implemented. The objectives are digital design reduction of an adaptive lter, making use of a low complexity algorithm and to achieve improvement in convergence speed.

CHAPTER 2
ADAPTIVE LMS ALGORITHM

Actually there are different adaptive algorithms like RLS (Recursive Least Square) or LMS. These algorithms works on time domain and also exist frequency domain algorithms. The time domain algorithm often used is LMS, because its computational complexity lets an easy implementation on a chip. The LMS algorithm is based on gradient search error, the mathematical expression is , w(n + 1) = w(n) + (n)e(n)x(n) (2.1)

where w(n + 1) are the next lter weights,w(n) are the current weights, x(n) is the sampled input signal, e(n) is the lter error and the convergence factor, which must satisfy 0 1 M x2 (n) (2.2)

where M is the lter taps number and x2 (n) is the mean power estimated using some input samples. If convergence factor is high, thus speed convergence is fast but least error cant be gotten. Making use of a low convergence factor, the algorithm reaches to least error but on the other hand speed convergence is slow.

2.1

The Filtering Process

An M-by-1 tap input vector x(n) consists of the elements x(n),x(n 1) ,............, x(n M + 1) that span a multidimensional space, x( n). The value of M is the lter order. The tap-weight vectorw(n) is composed of the elements w0 (n),w1 (n),...,wM 1 (n). The tap-weight vector must be initialized. A common practice is to set the initial vector w(0) = 0. Thus the lter output begins at zero and gradually approaches the optimal solution. In order for the ltering to take place, the desired response d(n) as well as the tap-input vector must be available. The error is e(n) = d(n) y (n) (2.3)

which is the difference between the desired response, d(n), and the lter output, denoted y (n). This is the overall system output. The lter produces an output an output d(n), which is an estimate of the desired response. The adaptive weight-control mechanism requires the error and the tap-input vector to be supplied to close the feedback loop around the tap weights. The feedback loop behaves like a low-pass lter.The average time constant is inversely proportional to the stepsize parameter . The step-size parameter is a convergence factor that controls stability as well as the rate of adaptation. The adaptive process progresses slowly when a small step-size parameter is used and the effects of gradient noise on the tap weights are largely ltered I

2.2

The Adaptive Process

The adaptive process adapts the weights until the correlation between the noise in the signal and the reference noise is cancelled from the output. In order to determine the correction dwk (n) that is applied to the tap weight wk (n) for the following iteration, the product of e(n) and x(n k ) is calculated for k = 0,1,2......,M-2, M-1 and is scaled by . This update of the tap-weights can be described by the equation w(n + 1) = w(n) + 2 x(n)e(n) (2.4)

The lter response at each iteration is the sum of the previous lter response and the correction factor. As the step-size increases the speed of convergence increases proportionally. In summary, there are ve main computations that should be performed in this order: 1. At a particular time n, the lter weight must be available. 2. The output of the lter is computed. 3. The estimation error is calculated. 4. The next lter weight is computed. 5. Perform the next iteration.

CHAPTER 3
HARDWARE AND SOFTWARE PLATFORM

3.1

Hardware Platform-DSK 6416

Signal processors such as the TMS320C6x (C6x) family of processors are like fast special-purpose microprocessors with a specialized type of architecture and an instruction set appropriate for signal processing. The C6x notation is used to designate a member of Texas Instruments TMS320C6000 family of digital signal processors. The architecture of the C6x digital signal processor is very well suited for numerically intensive calculations. Based on a very-long-instruction-word (VLIW) architecture, the C6x is considered most powerful processor. Digital signal processors are used for a wide range of applications, from communications and controls to speech and image processing. The general-purpose digital signal processor is dominated by applications in communications (cellular). Applications embedded digital signal processors are dominated by consumer products. They are found in cellular phones, fax/modems, disk drives, radio, printers, hearing aids, MP3 players, high-denition television (HDTV), digital cameras, and so on. These processors have become the products of choice for a number of consumer applications, since they have become very cost-effective. They can handle different tasks, since they can be reprogrammed readily for a different application. DSP techniques have been very successful because of the development of low-cost software and hardware support. For example, modems and speech recognition can be less expensive using DSP techniques. DSP processors are concerned primarily with real-time signal processing. Real-time processing requires the processing to keep pace with some external event, whereas non-real-time processing has no such timing constraint. They are easy to use, exible, and economical. The DSK package is powerful, yet relatively inexpensive, with the necessary hardware and software support tools for real-time signal processing . It is a complete DSP system. The DSK board includes the C6416 oating-point digital signal processor and a 32-bit stereo codec TLV320AIC23 (AIC23) for input and output. The onboard codec AIC23 uses a sigmadelta technology that provides ADC and DAC. It connects to a 12-MHz system clock. Variable sampling

rates from 8 to 96 kHz can be set readily A daughter card expansion is also provided on the DSK board. Two 80-pin connectors provide for external peripheral and external memory interfaces. The DSK board includes 16MB (megabytes) of synchronous dynamic random access memory (SDRAM) and 256kB (kilobytes) of ash memory. Four connectors on the board provide input and output: MIC IN for microphone input, LINE IN for line input, LINE OUT for line output, and HEADPHONE for a headphone output (multiplexed with line output). The status of the four user dip switches on the DSK board can be read from a program and provides the user with a feedback control interface. TMS320C6713 Digital Signal Processor The C64x is a xed-point processor. Features of the C6416 architecture include: four 16-bit multiplier (each .M unit can perform two multiplies per cycle), sixty-four 32-bit general-purpose registers, more than 1MB of internal memory consisting of 1MB of L2 RAM/cache, 16 kB of each L1P program cache and L1D data cache. The C64x can operate at a much higher clock rate. The C6416 DSK operates at 720MHz for a 1.39 ns instruction cycle time. With eight instructions per cycle, this translates into 5760 million instructions per second (MIPS). The C64x is based on the architecture VELOCITI.2, which is an extension of VELOCITI. The extra registers allow for packed data types to support 8-bit or two 16-bit operations associated with one 32-bit register, increase g parallelism. Several specialpurpose instructions have also been added to handle many operations encountered in wireless and digital imaging applications, where 8-bit data processing is common. In addition, the .M unit (for multiply operations) can also handle shift and rotate operations. Similarly, the .D unit (for data manipulation) can also handle logical operations.

3.2

Software Platform-Code composer Studio

CCS provides an IDE to incorporate the software tools. CCS includes tools for code generation, such as a C compiler, an assembler, and a linker. It has graphical capabilities and supports real-time debugging. It provides an easy-to-use software tool to build and debug programs.

The C compiler compiles a C source program with extension .c to produce an assembly source le with extension.asm. The assembler assembles an .asm source le to produce a machine language object le with extension.obj. The linker combines object les and object libraries as input to produce an executable le with extension. out. This executable le represents a linked common object le format (COFF), popular in Unix-based systems and adopted by several makers of digital signal processors. This executable le can be loaded and run directly on the C6416 processor. A linear optimizer optimizes this source le to create an assembly le with extension .asm (similar to the task of the C compiler). To create an application project, one can add I the appropriate les to the project. Compiler/linker options can readily be specied. A number of debugging features are available, including setting breakpoints and watching variables; viewing memory, registers, and mixed C and assembly code; graphing results; and monitoring execution time. One can step through a program in different ways (step into, over, or out). Real-time analysis can be performed using real-time

data exchange (RTDX). RTDX allows for data exchange between the host PC and the target DSK, as well as analysis in real time without stopping the target. Key statistics and performance can be monitored in real time. Through the joint team action group (JTAG), communication with on-chip emulation support occurs to control and monitor program execution. The C6416 DSK board includes a JTAG interface through the USB port.

CHAPTER 4
CIRCUIT DIAGRAM

4.1

Circuit Diagram

Figure 4.1: Circuit diagram

4.2

Circuit Diagram Description

The input to the DSK is a contaminated signals (YK) containing both the desired signal (SK) and noise (NK).Both are uncorrelated with each other. Another input is the noise signal (XK).The input (XK) is correlated with (NK) and uncorrelated with (SK).The inputs are taken from function generators. The signals are given to a two input one output adapter. The adapter has one input connector white (or silver) that represents the left channel and another input connector red (or gold) that represents the right channel. The output of the adapter is given to the LINE IN of the DSK. By using the C program in the processor we can separate the signals from the left and the right channels. From the LINE IN, the signals are given to the onboard codec (AIC23). It uses a sigmadelta technology that provides ADC and DAC. The given analog signals are converted to digital using the ADC. The digital values are read by the C program for adaptive lter. By using the program we can separate the desired signal from noise. The output is in digital form which is converted into analog by using the DAC in AIC23.

The output can be displayed on the CRO through the LINE OUT of the DSK. As an example the contaminated signal is sine1500Hz (desired signal) + sine312Hz (noise signal). Another noise signal is cosine312Hz which is uncorrelated with desired signal and correlated with the noise signal (sine312Hz). By using the LMS algorithm we can separate the desired signal from the contaminated signal.

CHAPTER 5
PROGRAM CODE

#include "DSK6713_AIC23.h" //codec-DSK support file Uint32 fs=DSK6713_AIC23_FREQ_48KHZ; #define beta 1E-13 #define N 30 #define LEFT 0 #define RIGHT 1 //set sampling rate //rate of convergence //weights (coefficients) //left channel //right channel

float w[N]; float delay[N]; short output; short out_type = 1;

//weights for adapt filter //input buffer to adapt filter //overall output //output type for slider

volatile union{unsigned int uint; short channel[2];}AIC23_data;

interrupt void c_int11() { short i;

//ISR

float yn=0, E=0, dplusn=0, desired=0, noise=0;

AIC23_data.uint = input_sample();//input 32-bit from two channels desired =(AIC23_data.channel[LEFT]); //input left channel noise = (AIC23_data.channel[RIGHT]); //input right channel

dplusn = desired + noise; delay[0] = noise;

//desired+noise //noise as input to adapt FIR

for (i = 0; i < N; i++) yn += (w[i] * delay[i]); E = (desired + noise) - yn;

//to calculate out of adapt FIR //output of adaptive filter //"error" signal=(d+n)-yn

for (i = N-1; i >= 0; i--) { w[i] = w[i] + beta*E*delay[i]; delay[i] = delay[i-1]; } if(out_type == 1)

//to update weights and delays

//update weights //update delay samples

//if slider in position 1

output=((short)E); //error signal as overall output else if(out_type==2) //if slider in position 2

output=((short)dplusn); //output (desired+noise) output_sample(output); return; } //overall output result

void main() { short T=0; for (T = 0; T < 30; T++) { w[T] = 0; //init buffer for weights //init buffer for delay samples

delay[T] = 0; } comm_intr(); while(1); }

//init DSK, codec, McBSP //infinite loop

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CHAPTER 6
RESULT

Code Composer Studio, DSK and TMS320C6713 processor has been familiarized. Adaptive lter using TMS320C6713 processor has been done successfully. Desired frequency is fed to the left channel and undesired to the right channel. The desired signal is obtained as the output which is displayed on a DSO.Different waveforms used and obtained are shown below.

Figure 6.1: Correpted and Filtered signal

REFERENCES
[1] Chassaing, R., DSP Applications Using C and the TMS320C6x DSK, (Wiley, 2002). [2] Texas Instruments, Code Composer Studio Getting Started Guide (SPRU509C).

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