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Synopsys 2012 1

Debug Methods for


FPGA-Based Prototypes
Troy Scott
Product Marketing Manager
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Debugging Throughout the Prototype Lifecycle
Key debug scenarios
Prototype bring-up debug & troubleshooting
RTL design flaw isolation
Software-driven system debug
System
Debug
RTL
Debug
Prototype
Bring-Up
Debug
1 2 3
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Confirm Prototype Integrity
System
Debug
RTL
Debug
Prototype
Bring-Up
Debug
1 3
Confirm
Connections
Reference
Design
2
SCENARIO
Assemble hardware
Derive hardware target for prototype
planning and synthesis software
Confirm daughter board operation
Confirm connector integrity
Confirm partition and mux logic
Confirm clock/reset distribution
Check module operation via co-sim
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Find Design Flaws
System
Debug
Prototype
Bring-Up
Debug
1 3
RTL
Debug
2
SCENARIO
Instrument suspect RTL modules
Isolate behavior with trigger
expressions
Observe signal history
(Repeat if necessary)
Locate and correct bug
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HAPS System
Validate with SoC Software
Prototype
Bring-Up
Debug
1
System
Debug
3
RTL
Debug
2
Test
Equipment
PHY
Board
PHY
Board
FPGA #1 FPGA #2
FPGA #3 FPGA #4
DUT RTL
Host PC
DUT uP
U
M
R
B
u
s
SCENARIO
Connect real-world IO to prototype
Distribute design across FPGA/Host
Confirm long term tests
Distribute for firmware/driver dev
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What are some good ways
to confirm the prototype
setup is correct?
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Prototype Integrity Checks
Filter Test Design Example
Incremental Module Migration
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Filter test design for multiple FPGAs
Synopsys Press - FPMM 11.3.1 Example
4-tap pre-loadable transposed FIR filter test design
FPGA 1
+
x
Input
Clock
Coeff4
Tap4
0
+
x
Coeff3
Tap3
+
x
Coeff2
Tap2
+
x
Coeff1
Tap1
Output
FPGA 2 FPGA 3 FPGA 4
Reset timing
Acceptable clock skew
FPGA-to-FPGA connection integrity
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Test Fixture
Module 1 Module 2
Module n
DUT
Synopsys VCS Simulator

Incrementally Migrate Modules


With Co-Sim HDL-Bridge
HDL
Bridge
Simulator Environment replacement
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Test Fixture
Module 1
HDL
Bridge
Module n
DUT
Synopsys VCS Simulator
Module 2
Synopsys HAPS Prototype
UMRBus
HDL
Bridge

Reducing Time to Prototype


HDL-Bridge
Cycle Based
PLI Interface
HDL Bridge
Supports Multiple Modules
Module
2+n
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Certify / CHIPit Manager Pro VCS
HDL Bridge Design Flow
1. Add Top Level Model to
HAPS/CHIPit Manager project
2. Select target HAPS platform
3. Select simulator
4. Generate HDL bridges
5. Compile into simulator
6. Implement into prototype
7. Co-simulate
Top Level
Module
CHIPit Manager Pro
hdlbridge_gen
HDL Bridge
Simulator Environment
- Simulation Mode
- Warning Level
- Unique Identifier
HDL Bridge
Hardware Environment
- Unique Identifier
Simulator
Synthesis
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Other Links to VCS
Simulate the post
partitioning to validate
transformations and
inserted capabilities
such and pin
multiplexing.
Revert to simulator to
enable 100% debug
visibility
Design files
Certify
Synplify
Identify
VCS
FPGA-Based Prototyping
HDL
Export
VCD
Export
Post-Partition
Model Export
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Checklist: Prototype Integrity
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What are some good
ways to detect and
isolate RTL bugs?
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RTL Debug
Expanding Signal Visibility
Increasing Sample Storage
Faster Turnaround Time
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Evolution of Hardware Debug
Logic Analyzer
Identify Solution
(Simulator-Like)
Embedded
HDL Analyzer
ChipScope/ SignalTap
(Logic Analyzer-Like)
Embedded
Logic Analyzer
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Introducing Identify RTL Debugger
Identify Instrumentor
Compiles design to find nodes & branches
you use to trigger & sample
Displays design hierarchy for easy navigation
Automatically inserts IICE (probe and
communication logic)
Supports mixed language designs
Qualified sampling is very useful
Identify Debugger
Controls triggering
Displays data in RTL or waveform
Supports multiple IICE on multiple clocks and
cross-triggering between clocks
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Multiplexed Instrumentation Sets
Selectively trace across multiple groups
Increased design visibility
Increased capacity through shared sample memory
Supports up to 8 sample groups
Group
#1
Group
#2
Group
#n
Identify Debugger
Debug
Sample
Memory
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MUX Set Instrumentation
8
8
8
8
4
32 Signals to Debug
4 Signals to Trigger on
Depth as 1000 K
=~ 32000 K + IICE Logic
32 Signals to Debug
4 Signals to Trigger on
Depth as 1000 K
=~ 8000 K + IICE Logic + 4 Mux Set
Identify Buffer
Identify IICE Logic
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Mux Instrumentation Setup
Identify Instrumentor
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Mux Group Selection
Identify Debugger
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Multiplexed Instrumentation Summary
Strengths
Increased visibility through over-instrumentation
Manages limited BRAM resources
Dynamic re-configuration of debug views
No need to re-instrument OR re-synthesize
Preserve current timing and behavioral properties
Limitations
Maximum 8 groups per IICE
All on the same clock
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Limited Memory for Debug Sampling
Example: Virtex-6 LX760 Memory Consumption
Xilinx Virtex-6 LX760 FPGA BEFORE
Logic
Memory
DSP
Processing
High-speed I/O
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Limited Memory for Debug Sampling
Example: Virtex-6 LX760 Memory Consumption
9
0
%
~10% remaining for
debug storage
(2.592MBit)
Xilinx Virtex-6 LX760 FPGA AFTER
Logic
Memory
DSP
Processing
High-speed I/O
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Managing Sample Buffer Consumption
IICE and Sample Buffer Architecture
Breakpoints
Watchpoints
P1
P2
Pn
Trigger
Circular Sample Buffer
Programmable Depth
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Managing Sample Buffer Consumption
IICE and Sample Buffer Architecture
Breakpoints
Watchpoints
Trigger
S1
S2
S3
S4
Sn
Counter
P1
P2
Pn
Trigger
Circular Sample Buffer
Programmable Depth
Smaller sample depth
More elaborate trigger
conditions
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HAPS Deep Trace Debug
100x more signal visibility; Over 1 Gbit possible
Store sample to HapsTrak II 4MBx72 bit SRAM cards
(SRAM_1x1_HTII Daughter Board)
Requires 1 card or card stack per Identify IICE
Supports up to 4 SRAM boards stacked
HAPS-60/50 Series
Sample
Data
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External HapsTrak II SRAM Daughter Card for Debug
Each SRAM card 4M x 72 bit words
Cards can be stacked up to 4 high (1 Gigabit of samples)
Sample frequency range: 20-60 MHz
Uses 1 HapsTrak connector
Overview HAPS Deep Trace Debug
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Synplify / Identify flow remains unchanged
Enabling HDTD in the GUI
Click on Edit IICE settings
Select hapssram
Select HapsTrak connector in GUI
Setup and Usage
Buffer type:
- behavioral
- hapssram
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A built-in hardware self test is provided in the Identify
debugger
Confirms proper communication with the external SRAM cards
Confirms whether the configured SRAM depth can be fully
utilized.
Tcl Invocation in the Debugger:
iice sampler runselftest 1
Bit files need to be loaded on the target FPGA before executing
this command.
HAPS DTD Self Test
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HAPS DTD Summary
Single FPGA automation
Instrument standalone project or SLP output only
At least 1 HapsTrak connector per FPGA
User must pre-allocate debug connectors
IICE SRAM pairing
Multiple IICEs require multiple SRAM cards
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HAPS-50/60 Series
HAPS Real Time Debug
Agilent 16700, 16900 series and Tektronix TLA series
Specify probe points from Identify
Connect external LA to store sample data
Apply complex trigger conditions
Leverage familiar lab tools for debugging internal nodes
HAPS-50/60 Series + MICT_1x1
Logic Analyzer MICT_1x1
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HAPS RTD Setup
1. Specify RTD-type IICE (I/R)
2. Specify Board and Locations
3. Instrument
4. View Signal Assignments
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Logic Analyzer Interface Setup
1. Logic Analyzer Scan
2. Logic Analyzer Properties
3. Logic Analyzer Submit
4. IICE Assignments
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HAPS-62 with External Debug Storage
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Apply small IICE connectivity changes
ECO confirmed by Synplify Physical Synthesis
NCD update via Xilinx FPGA Editor or xdl2ncd
Uses Xilinx FPGA Editor
Leverages Synplify physical synthesis knowledge
More stable and predictable re-incarnation of previous
incremental functionality
Bypasses synthesis and P&R for rapid turnaround of
Sample/Trigger conditions
Xilinx Virtex 6/5 based designs
Incremental Instrumentation
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Incremental Flow
Setup
Project
1
st
Pass 2
nd
Pass
Instrument
Design
Synthesize &
Place and Route
Debug
Modify
Instrumented
Signals
Debug
Incremental
Re-Route
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Registers qualify
Swap existing debug signals
Debug type stays the same
Sample Only, Trigger Only, Sample and Trigger
Incremental Use Model
Pre synthesis, RTL instrumentation
Any data type can be instrumented
Instrumented objects will be preserved
through P&R
Post P&R, incremental instrumentation
Register and primary IO names are preserved
Net names can change no link to original RTL
IICE IICE
Net_X
Net_YY_0 Net_Y_1
Net_Y
Net_X
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Incremental Setup
Initial Setup
Base
instrumentation
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Benefits
Quick turnaround time for re-instrumentation
Minimal changes to FPGA data base
Limitations
Not a full re-instrumentation flow
Only registers and primary IO objects are sure to be preserved
through P&R and thus linked back to original RTL
Physical limitations: Some ECOs may not be able to route
Incremental Instrumentation Summary
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Checklist: Prototype Debug Visibility
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How can I connect the
prototype to other EDA
tools and models?
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Extending FPGA-Based Prototyping
Capabilities with the UMRBus
Advanced Verification Capabilities
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What is the UMRBus?
Universal Multi-Resource Bus
Pre-built interface from C/C++/Tcl
Implemented by insertion of UMRBus IP module
UMRBus Interface Kit to connect host workstation
UMRBus Interface Pod
PCIe Gen1 4-lane interface to host computer
CDE cable for HAPS-6x
CON cable for HAPS-5x/6x
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Universal Multi-Resource Bus (UMRBus)
Configure/Debug/Co-Simulation
Host
Remote Access
System Configuration System Monitoring
C / C++ / TCL
direct to HW
Application
Programming Interface
UMRBus
UMRBus
Co-Simulation
Transaction Based
Verification
Link to Virtual
Prototyping
Enabling Advanced
Use Modes
UMRBus
UMRBus
UMRBus
Bus Monitoring
Memory Preload and
Readback
Data Streaming
Modification of
Signal Values
Observation of
Design Status
Design Interaction &
Monitoring
UMRBus
UMRBus
UMRBus
UMRBus
UMRBus
What It Is
High-performance, low latency communication bus
Up to 80MB/s
Unique to Synopsys HAPS Hardware
Connections to every FPGA, memory, registers, etc
Benefits
Remote prototype management
Application level programming
Co-simulation
Transaction-based verification
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Host Application Interface Module
Software Interface Module
UMRBus
Communication
Hardware Interface Module
Software (host workstation)
UMRBus
Host
Application
Interface
do
wr
di
rd
intr
inta
inttype
32
32
16
CAPI
Reset Clock
CAPIM
Client
Application
Interface
Module
DUT
Part1
DUT
Part2
DUT
Part3
CAPIM CAPIM CAPIM
Synopsys Prototyping Hardware
User
App
1
User
App
2
User
App
N
UMRBus
Comprehensive and fully tested mechanism
that allows bi-directional data exchange (at
runtime) between software (C/C++or Tcl/Tk
application) and hardware (DUT)
Up to 63, 32-bit communication channels
(CAPIMs) available to communicate with the
DUT
Description
UMRBus Implementation Architecture
8
8
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Host Application Interface (HAPI)
UMRBus on software side (host computer)
Functions provide access to Client Application (CAPP)
Description C-language UMRBus Tcl/Tk
to open a connection to the CAPP umrbus_open() umrbus_open
to close a connection to the CAPP umrbus_close() umrbus_close
to write data to client application umrbus_write() umrbus_write
to read data from client application umrbus_read() umrbus_read
to verify the client interrupt requests umrbus_interrupt() umrbus_interrupt
to search for all active UMRBuses and UMRBus Clients umrbus_scan() umrbus_scan
to free the data returned from the scan function umrbus_scan_free() -
to free the error message returned by a HAPI function umrbus_errormessage_free() -
to check the data transfer on specified UMRBus umrbus_testframe() -
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Synopsys SCE-MI Implementation
Co-Emulation API
Software Side (host workstation) Hardware Side (emulator/prototype)
Untimed
C++Model
Untimed
C++Model
RT-level
C++Model
Untimed
C++Model
C/C++Kernel
(SystemC)
Message In Port
Proxy 1
Message In Port
Proxy 2
Message Out Port
Proxy 3
SCE-MI Infrastructure
Xtor 1
Message In Port
Port 1
Xtor 2
Message In Port
Port 2
Message Out Port
Port 3
DUT
Clock/Reset
Generation
and Control
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Synopsys Hybrid Prototyping Solution
Virtual (Pre-RTL)
SystemC
TLM
Synopsys Virtual
Prototype
Software Stack
Synopsys
Virtualizer Development Kit (VDK)
Synopsys
HAPS FPGA-Based Prototype
HDL
RTL
FPGA-Based (RTL)
Data Exchange
Physical Link:
UMRBus
New: Transactor
Protocol: AMBA
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Transactor Library for AMBA
Complete Transactor: Software & Hardware
Workstation - Software
U
s
e
r

A
p
p
l
i
c
a
t
i
o
n
SW
Transactor
C
+
+

A
P
I
U
M
R
B
u
s

A
P
I

&

D
r
i
v
e
r
U
M
R
B
u
s

-
I
n
t
e
r
f
a
c
e
HAPS - Hardware
User Design
HW
Transactor
UMRBus
Adapter
Trans
actor
Core
CAPIM
AMBA
U
s
e
r

A
M
B
A

C
o
m
p
o
n
e
n
t
s
UMR PCIe
Synopsys supplied hardware, object code,
encrypted or tool inserted IP
SystemC
TLM 2.0
S
y
s
t
e
n
m
C

A
P
I
C++API
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Validating IP (like H.264 decoder) in
real world environment
RTL or IP block with AMBA interface
C++ program to generate test data
Requirements
DUT
(e.g. H.264 decoder)
FPGA-Based Hardware
AXI/AHB
Transactor
SDRAM
Controller
SDRAM
Utilize UMRBus & AMBA based
transactor to stream data to FPGA-
based prototyping hardware
Solution
Data stream
Host
Example Data Streaming
LCD
Ctrl
LCD
UMRBus
AXI/AHB
Transactor
C++ program
Host
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Validating IP (like USB controller) in
real world environment
RTL or IP block with AMBA interface
Embedded Linux OS program to
generate test data
Requirements
DUT
(e.g. USB 3.0 device controller)
FPGA-Based Hardware
AXI/AHB
Transactor
USB 3.0
PHY
Laptop
Utilize UMRBus & AMBA based
transactor to connect virtual CPU
subsystem to FPGA-based
prototyping hardware
Solution
Host
Example In-Context Validation
UMRBus
AXI/AHB
Transactor
Linux OS
ARM Cortex
VDK
USB Device
Driver
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Checklist: Prototype Connectivity
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Synopsys Software Synopsys Hardware
SystemC/FPGA hybrid prototyping
Multi-FPGA implementation for HAPS
SystemC/C++software libraries and IP for FPGA
Co-simulation or transaction based verification VCS
Host Workstation
HAPS-60 Series
HAPS-60
Co-Sim & TBV Suite
Certify
HAPS UMRBus
Interface Kit
Virtualizer
UMRBus Interface Pod
HAPS-64 System
UMRBus
Products Presented
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Predictable Success