Do An

I HC QUC GIA THNH PH H CH MINH
TRNG I HC BCH KHOA

KHOA KHOA HC & K THUT MY TNH
----------
n mn hc Thit K Lun L.
TNG QUAN VI X L LPC2300

HNG DN S DNG BOARD MCB 2300
Ging vin hng dn
Nguyn Quc Tun
Sinh vin thc hin

Nguyn Thanh Bi 51100264
Minh Chin - 51100372
TP. HCM, 12/2013
......................................................................................................................................................... I
Phc Lc Hnh ............................................................................................................................................ IV

Ph Lc Bng.............................................................................................................................................. VI
LI CM N ............................................................................................................................................... 1
CHNG M U .................................................................................................................................... 2
I.
TNG QUAN V VI X L LPC2300 ........................................................................................... 3

I.1.
M t chung v LPC2300 .................................................................................................... 3
I.2.
c im chnh. ................................................................................................................... 4
I.3.
S khi ............................................................................................................................ 5
I.4.
a Ch B Nh Trong LPC2300 ...................................................................................... 10
I.4.1 T chc b nh v a ch ca cc thit b ngoi vi........................................................... 10

I.4.2 Phn vng b nh. ........................................................................................................... 11
I.4.3 Phn vng b nh thit b ngoi vi ................................................................................... 16
I.4.4 a ch thit b APB. ........................................................................................................ 18
I.4.5 Phn vng li b nh trong LPC2300 v boot ROM. ........................................................ 19
I.5.
Khi iu Khin H Thng. .............................................................................................. 23
I.5.1 Gii thiu ......................................................................................................................... 23

I.5.2 Chn kt ni ngoi ca khi iu khin h thng. ............................................................. 23
I.5.3 Cc thanh ghi lin quan. ................................................................................................... 24
I.5.4 Reset ................................................................................................................................ 24
I.5.5 External interrupt. ............................................................................................................ 27
I.6.
M un Tng Tc B Nh (Memory Acceleration Module - MAM). ............................. 29
I.7.
Khi iu Khin Vect Interrupt (Vectored Interrupt Controller - VIC). .................... 29
I.7.2 Gii thiu. ........................................................................................................................ 29

I.7.2 Cc loi thanh ghi VIC. .................................................................................................... 30
I.7.3 Kin trc Interrupt ........................................................................................................... 31
I.7.4 Ngun Interrupt ............................................................................................................... 32
I.8.
Cc Thit Lp Chn Cho LPC2300 .................................................................................. 34
I.9.
Tng Quan Chc Nng Cng Input/Ouput Vi X L LPC2300(GPIO) ......................... 35
I.9.1 c im chung ............................................................................................................... 35

I.9.2 a ch thanh ghi .............................................................................................................. 35
I.9.3 Mt s code mu s dng GPIO....................................................................................... 37
I.10. Ethernet ............................................................................................................................. 38
I.10.1
c im chung............................................................................................................ 39
I.10.2
Kin trc ...................................................................................................................... 40
I.10.3
DMA ............................................................................................................................ 40
I.10.3
Gi trong Etherrnet ....................................................................................................... 41
I.10.4
M t chc nng cc chn............................................................................................. 41
I.10.5
a ch thanh ghi .......................................................................................................... 42
I.11. CAN.................................................................................................................................... 44
I.11.1
nh ngha.................................................................................................................... 44
I.11.2
Kin trc ...................................................................................................................... 44
I.11.3
a ch b nh .............................................................................................................. 46
I.11.4
Thanh ghi iu khin CAN ........................................................................................... 46
I.12. USB .................................................................................................................................... 48

I.12.1
nh ngha.................................................................................................................... 48
I.12.2
Kin trc ...................................................................................................................... 48
I.12.3
a ch thanh ghi .......................................................................................................... 49
I.13. UART ................................................................................................................................. 50

I.13.1
Gii thiu ..................................................................................................................... 50
I.13.2
Kin trc ...................................................................................................................... 50
I.13.3
a ch thanh ghi .......................................................................................................... 53
I.14. SPI ...................................................................................................................................... 59

I.14.1
nh ngha.................................................................................................................... 59
I.14.2
Truyn d liu trong SPI .............................................................................................. 59
I.14.3
a ch thanh ghi .......................................................................................................... 60
I.14.4
Kin trc ...................................................................................................................... 65
I.15. I2C ...................................................................................................................................... 66

I.15.1
Gii thiu ..................................................................................................................... 66
I.15.2
Nguyn l hot ng ca I2C ....................................................................................... 66
I.15.3
Cc ch hot ng ca I2C ...................................................................................... 66
II
I.15.4
Kt ni vt l ................................................................................................................ 70
I.15.5
S khi ca I2C ....................................................................................................... 71
I.15.6
a ch thanh ghi .......................................................................................................... 73
I.16. TIMER ............................................................................................................................... 77

I.16.1
Gii thiu ..................................................................................................................... 77
I.16.2
Hot ng ca TIMER ................................................................................................. 77
I.16.3
a ch thanh ghi .......................................................................................................... 77
I.16.4
V d hoat ng ca Timer ........................................................................................... 78
I.16.5
Kin trc ...................................................................................................................... 79
II. CCH S DNG BOARD MCB2300 ............................................................................................ 81

II.16.1 Gii thiu board thc tp MCB 2300 ............................................................................ 81
II.16.2 Kit th nghim MCB2300 ............................................................................................. 81
II.16.3 c im chnh ca MCB2300.board ........................................................................... 82
II.16.4 Chun b v phn cng. ................................................................................................ 82
II.16.5 Chun b v phn mm. ................................................................................................ 83
II.16.6 Ci t board th nghim MCB2300. ............................................................................ 83
II.16.7 Thit lp jumper trn board MCB2300. ........................................................................ 87
PH LC .................................................................................................................................................... 88
IU KHIN LED ........................................................................................................................ 88
IU KHIN LCD........................................................................................................................ 89
III
Phc Lc Hnh
Hnh 1. S khi LPC2361/62 .......................................................................................................... 5

Hnh 2 S khi LPC2364/65/66/67/68 ............................................................................................ 6
Hnh 3 S khi LPC2377/78 ........................................................................................................... 7
Hnh 4 S khi LPC2387 ................................................................................................................ 8
Hnh 5 S khi LPC2388 ................................................................................................................ 9
Hnh 6 Phn vng b nh LPC2461/63 .............................................................................................. 11
Hnh 7 Phn vng b nh LPC2364/65/66/67/68 ............................................................................... 12
Hnh 8 Phn vng b nh LPC2377/78 .............................................................................................. 13
Hnh 9 Phn vng b nh LPC2387 ................................................................................................... 14
Hnh 10 Phn vng b nh LPC2388 ................................................................................................. 15
Hnh 11 Phn vng b nh Thit b ngoi vi ...................................................................................... 16
Hnh 12 Phn vng b nh thit b AHB ............................................................................................ 17
Hnh 13 B nh mc thp cho thy qu trnh ti phn vng b nh ............................................ 22
Hnh 14 Thit lp li s khi bao gm b m thi gian wakeup................................................... 25
Hnh 15 V d khi ng li sau reset ................................................................................................ 26
Hnh 16 S khi n gin ca MAM ............................................................................................ 29
Hnh 17 S khi ca VIC .............................................................................................................. 31
Hnh 18 S khi Etherrnet ............................................................................................................ 40
Hnh 19 Ethernet packet fields .......................................................................................................... 41
Hnh 20 Khi iu khin CAN ........................................................................................................... 44
Hnh 21 Giao din b tr ca TXB t c bn n m rng ................................................................. 45
Hnh 22 Giao din b tr ca RXB t c bn n m rng ................................................................. 45
Hnh 23 S khi thit b iu khin USB ...................................................................................... 48
Hnh 24 S khi LPC2300 UART0, 2 v 3 ................................................................................... 51
Hnh 25 S khi LPC2300 UART1 ............................................................................................... 52
Hnh 26 Autobaud mode 0 .............................................................................................................. 55
Hnh 27 Autobaud mode 1 .............................................................................................................. 56
Hnh 28 S flow chart ................................................................................................................... 57
Hnh 29 Truyn d liu trong SPI (CPHA = 0 v CPHA = 1) ............................................................ 59
Hnh 30 S khi SPI ..................................................................................................................... 65
Hnh 31 nh dng ch Master truyn ........................................................................................ 67
Hnh 32 nh dng ch Master nhn .......................................................................................... 68
Hnh 33 Ch Master nhn chuyn thnh Master truyn sau khi gi START lp li ........................ 68
Hnh 34 nh dng ch Slave nhn ............................................................................................ 69
Hnh 35 nh dng ch Slave truyn .......................................................................................... 69
Hnh 36 Cu hnh bus I2C ................................................................................................................. 70
Hnh 37 S khi I2C ..................................................................................................................... 71
Hnh 38 Xung clock ng b ............................................................................................................. 72
Hnh 39 a ch thanh ghi I2C ........................................................................................................... 73
Hnh 40 Chu k ca mt timer vi PR=2, MRx=6 v interrupt, reset c kch hot ...................... 79
IV
Hnh 41 Chu k ca mt timer vi PR=2, MRx=6 v interrupt, stop c kch hot....................... 79

Hnh 42 S khi ca Timer ........................................................................................................... 80
Hnh 43 Board MCB 2370 ................................................................................................................. 82
Hnh 44 Board MCB2300 vi cng USB ........................................................................................... 83
Hnh 45 Board MCB2300 vi ch thch trn hnh .............................................................................. 84
Hnh 46 Board MCB2300 vi kt ni ULink ..................................................................................... 84
Hnh 47 Setup ARM .......................................................................................................................... 85
Ph Lc Bng
Bng 1 c im tng qut LPC2300 .................................................................................................. 4

Bng 2 Bng Phn b a ch ca vng b nh trong ARM ................................................................ 10
Bng 3 Phn vng a ch c bn ca thit b APB ............................................................................. 18
Bng 4 a ch nh ngoi l ca ARM ............................................................................................ 19
Bng 5 Nhng ch hot ng ca b nh trong LPC2300 ............................................................. 19
Bng 6 Thanh ghi iu khin phn vng b nh ................................................................................ 21
Bng 7 Thanh ghi iu khin phn vng b nh - m t bit a ch 0xE01F C040 .............................. 21
Bng 8 B nh mc thp cho thy qu trnh ti phn vng b nh ............................................. 23
Bng 9 Tm tt cc thanh ghi iu khin h thng ............................................................................. 24
Bng 10 S tng tc gia 4 ngun Reset .......................................................................................... 27
Bng 11 Cc thanh ghi ca External interrupt .................................................................................... 27
Bng 12 Thanh ghi Flag ca External interrupt (EXTINT). ................................................................ 28
Bng 13 Thanh ghi Mode ca External interrupt (EXTMODE).......................................................... 28
Bng 14 Thanh ghi Polar ca External interrupt (EXTPOLAR). ........................................................ 28
Bng 15 Cc loi thanh ghi VIC ........................................................................................................ 30
Bng 16 S kt ni ca ngun Interrupt n VIC ............................................................................... 32
Bng 17 Chc nng ca cc chn ....................................................................................................... 34
Bng 18 a ch ca cc thanh ghi chc nng .................................................................................... 34
Bng 19 a ch thanh ghi GPIO (legacy APB accessible registers) ................................................... 35
Bng 20 a ch thanh ghi GPIO (local bus accessible registers - enhanced GPIO features) ............... 36
Bng 21 a ch thanh ghi interrupt GPIO ......................................................................................... 37
Bng 22 Bng vit tt, nh ngha trong phn ny .............................................................................. 38
Bng 23 Ethernet RMII pin descriptions ............................................................................................ 41
Bng 24 Ethernet MIIM pin descriptions ........................................................................................... 41
Bng 25 a ch thanh ghi Etherrnet .................................................................................................. 42
Bng 26 a ch b nh ca khi CAN .............................................................................................. 46
Bng 27 a ch thanh ghi iu khin CAN ....................................................................................... 46
Bng 28 a ch thanh ghi thit b USB ............................................................................................. 49
Bng 29 Mi quan h gia d liu SPI v giai on ca Clock .......................................................... 60
Bng 30 a ch thanh ghi trong SPI .................................................................................................. 60
Bng 31 M t chc nng cc bit ca thanh ghi S0SPCR ................................................................... 61
Bng 32 M t chc nng cc bit ca thanh ghi S0SPSR ................................................................... 63
Bng 33 M t cc bit ca thanh ghi SPTCR ..................................................................................... 64
Bng 34 M t cc bit ca thanh ghi SPTSR ...................................................................................... 64
Bng 35 Thanh ghi I2CnCONSET c s dng trong ch Master ............................................... 67
Bng 36 Thanh ghi I2CnCONSET c s dng trong ch Slave ................................................. 68
Bng 37 I2C PIN ............................................................................................................................... 70
Bng 38 M t cc bit ca thanh ghi I2CCONSET ............................................................................ 75
Bng 39 M t cc bit ca thanh ghi I2CCONCLR ............................................................................ 75
VI
LI CM N
Trn thc t khng c s thnh cng no m khng gn lin vi nhng
s h tr, gip d t hay nhiu, d trc tip hay gin tip ca ngi khc.
Trong sut thi gian t khi bt u hc tp ging ng i hc n nay,
em nhn c rt nhiu s quan tm, gip ca qu Thy C, gia nh
v bn b.
Vi lng bit n su sc nht, em xin gi n qu Thy C Khoa
Khoa Hc & K Thut My Tnh Trng i Hc Bch Khoa Thnh Ph
H Ch Minh cng vi tri thc v tm huyt ca mnh truyn t vn
kin thc qu bu cho chng em trong sut thi gian hc tp ti trng. V
c bit, trong hc k ny, Khoa t chc cho chng em c tip cn vi
mn hc m theo em l rt hu ch i vi sinh vin ngnh K Thut My
Tnh cng nh tt c cc sinh vin thuc cc chuyn ngnh Khoa Hc K
Thut khc. l mn hc n Thit K Lun L.
Em xin chn thnh cm n Thy Nguyn Quc Tun tn tm hng
dn chng em trong nhng bui ni chuyn, tho lun v lnh vc vi x l.
Nu khng c nhng li hng dn, dy bo ca thy th em ngh bi thu
hoch ny ca em rt kh c th hon thin c. Mt ln na, em xin chn
thnh cm n thy.
Bi thu hoch c thc hin trong khong thi gian gn 4 tun. Bc
u i vo thc t, tm hiu v lnh vc vi x l, kin thc ca em cn hn
ch v cn nhiu b ng. Do vy, khng trnh khi nhng thiu st l iu
chc chn, em rt mong nhn c nhng kin ng gp qu bu ca qu
Thy C v cc bn hc cng lp kin thc ca em trong lnh vc ny
c hon thin hn. Sau cng, em xin knh chc qu Thy C trong Khoa
Khoa Hc & K Thut My Tnh v Thy Nguyn Quc Tun tht di do
sc khe, nim tin tip tc thc hin s mnh cao p ca mnh l truyn
t kin thc cho th h mai sau.
Trn trng.
TP HCM, ngy 2 thng1 nm 2014
Nhm Sinh vin thc hin
KHOA HC & K THUT MY TNH

n Thit K Lun L GVHD : Nguyn Quc Tun
Thc hin : Nguyn Thanh Bi Minh Chin
Trang 1
LI M U
Trong s nghip cng nghip ha v hin i ha hin nay, khoa hc v

k thut chim mt v tr c bit. Cng ngh lun chy ua ni tip nhau
tng ngy. Ngay t u vi nh hng xy dng kin thc tng qut phi
cng nn tng trc, vic nghim cu v cc vi x l mt phn quan trng
ca cng ngh l iu m cc sinh vin lnh vc k thut my tnh cn
nghim cu.
Chng ta cn phi nm bt nhng g? l tng quan v vi x l cng
nh nguyn l hot ng v cch s dng. l l do v sao nhm nghim
cu v ti ny.

Trang 2
I. TNG QUAN V VI X L LPC2300

I.1. M t chung v LPC2300
LPC2300 l mt vi x l da trn nn tng CPU ARM vi m phng thi gian thc kt hp vi
vi iu khin c nhng b nh flash tc cao. LPC2300 rt ph hp vi cc ng dng truyn nhn
d liu tun t, cc ng dng giao tip ni tip a nng. Vi x l ny tnh hp mt giao tip 10/100
Ethernet Media Access Controller (MAC), giao tip USB 2.0 Full Speed, 4 giao tip UART, 2 knh
CAN, 1 cng SPI, 2 cng SSP (Synchronous Serial Ports), 3 giao tip I2C, 1 giao tip I2S v 1
MiniBus.
Thut ng LPC2300 c p dng cho ton b h vi x l gm :
LPC2361/62
LPC2364/65/66/67/68
LPC2377/78
LPC2387
LPC2388
ng dng trong iu khin cng nghip, h thng y t, thng tin lin lc, Protocol converter.

Trang 3
I.2. c im chnh.
Bng di y l nhng c im khc bit ca h LPC2300.
Bng 1 c im tng qut LPC2300
Part
Local
Bus
SRAM
(kB)
Flash
(kB)
EMC
USB/
GP
SRAM
(kB)
USB
device
USB
Host/
OTG
Ethernet
Ethernet
GP
SRAM
(kB)
CAN
channels
SD/
MMC
ADC
channels
GPIO
pins
LPC2361
64
No
Yes
Yes
No
16
No
70
LPC2362
32
128
No
Yes
Yes
Yes
16
No
70
LPC2364
128
No
Yes
No
Yes
16
No
70
LPC2365
32
256
No
Yes
No
Yes
16
No
70
LPC2366
32
256
No
Yes
No
Yes
16
No
70
LPC2367
32
512
No
No
No
Yes
16
Yes
70
LPC2368
32
512
No
Yes
No
Yes
16
Yes
70
LPC2377
32
512
Mini
No
No
Yes
16
Yes
104
LPC2378
32
512
Mini
Yes
No
Yes
16
Yes
104
LPC2387
64
512
No
16
Yes
Yes
Yes
16
Yes
70
LPC2388
64
512
Mini
16
Yes
Yes
Yes
16
Yes
104

Trang 4
I.3. S khi
Hnh 1. S khi LPC2361/62

Trang 5
Hnh 2 S khi LPC2364/65/66/67/68

Trang 6
Hnh 3 S khi LPC2377/78

Trang 7
Hnh 4 S khi LPC2387

Trang 8
Hnh 5 S khi LPC2388

Trang 9
I.4. a Ch B Nh Trong LPC2300

I.4.1 T chc b nh v a ch ca cc thit b ngoi vi.
B x l ARM c th qun l mt khng gian a ch b nh 4 GB. Bng di y th hin s
phn b a ch ca vng b nh trong cc thit b ARM:
Bng 2 Bng Phn b a ch ca vng b nh trong ARM
Address
range
General use
Address range details and description
0x0000 0000 to
0x3FFF FFFF
on-chip NV
memory and
fast I/O
on-chip RAM
0x0000 0000 - 0x0007 FFFF flash memory (up to 512 kB)

0x3FFF C000 - 0x3FFF FFFF fast GPIO registers
0x4000 0000 to
0x7FFF FFFF
0x8000 0000 to
0xDFFF FFFF
off-chip
memory
0xE000 0000
to
0xEFFF FFFF
0xF000 0000 to
0xFFFF FFFF
APB
peripherals
AHB
peripherals
0x4000 0000 - 0x4000 7FFF RAM (up to 32 kB)

0x4000 0000 - 0x4000 FFFF RAM (64 kB for LPC2387/88)
0x7FD0 0000 - 0x7FD0 1FFF USB RAM (8 kB)
0x7FD0 0000 - 0x7FD0 3FFF USB RAM (16 kB for LPC2387/88)
0x7FE0 0000 - 0x7FE0 3FFF Ethernet RAM (16 kB)
Two static memory banks, 64 KB each (LPC2377/78 and LPC2388
only):
0x8000 0000 - 0x8000 FFFF static memory bank 0, 64 KB
0x8100 0000 - 0x8100 FFFF static memory bank 1, 64 KB
0xE000 0000 - 0xE008 FFFF 36 peripheral blocks, 16 kB each (some
unused).
0xE01F C000 - 0xE01F FFFF System Control Block
0xFFE0 0000 - 0xFFE0 3FFF Ethernet Controller (not LPC2361)
0xFFE0 4000 - 0xFFE0 7FFF General Purpose DMA Controller
0xFFE0 8000- 0xFFE0 BFFF External Memory Controller (EMC)
(LPC2377/78, LPC2388 only)
0xFFE0 C000 - 0xFFE0 FFFF USB Controller (LPC2361/62/64/66/68,
LPC2378,LPC2387, and LPC2388 only).
0xFFFF F000 - 0xFFFF FFFF Vectored Interrupt Controller (VIC)

Trang 10
I.4.2 Phn vng b nh.

LPC2300 qun l cht ch tng vng nh ring bit. Bng sau th hin ton b khng gian a
ch. Vng nh cha a ch vector ngt phc v cho vic nh li a ch nh, vn ny s c
cp trong phn sau.
Hnh 6 Phn vng b nh LPC2461/63

Trang 11
Hnh 7 Phn vng b nh LPC2364/65/66/67/68

Trang 12
Hnh 8 Phn vng b nh LPC2377/78

Trang 13
Hnh 9 Phn vng b nh LPC2387

Trang 14
Hnh 10 Phn vng b nh LPC2388

Trang 15
I.4.3 Phn vng b nh thit b ngoi vi
Hnh 11 Phn vng b nh Thit b ngoi vi

C hai vng nh cho thit b AHB v APB c khng gian l 2MB v chia u cho 128 thit
b., mi thit b c phn 16 KB. iu ny n gin vic gii m a ch cho tng thit b.

Trang 16
Hnh 12 Phn vng b nh thit b AHB

Trang 17
I.4.4 a ch thit b APB.

Bng sau th hin phn vng ca thit b APB.
Bng 3 Phn vng a ch c bn ca thit b APB
Thit b APB
a ch c bn
Tn thit b ngoi vi
0xE000 0000
Watchdog Timer
0
0xE000 4000
Timer 0
1
0xE000
8000
Timer 1
2
0xE000 C000
UART0
3
0xE001 0000
UART1
4
0xE001 4000
Khng s dng
5
0xE001 8000
PWM1
6
0xE001 C000
I2C0
7
0xE002 0000
SPI
8
0xE002
4000
RTC
9
0xE002 8000
GPIO
10
0xE002 C000
Pin Connect Block
11
0xE003 0000
SSP1
12
0xE003 4000
ADC
13
0xE003 8000
CAN Acceptance Filter RAM[1]
14
0xE003 C000
CAN Acceptance Filter Registers[1]
15
0xE004 0000
CAN Common Registers[1]
16
0xE004 4000
CAN Controller 1[1]
17
0xE004 8000
CAN Controller 2[1]
18
0xE004 C000 - 0xE005 8000 Khng s dng
19 - 22
0xE005 C000
I2C1
23
0xE006 0000
Khng s dng
24
0xE006 4000
Khng s dng
25
0xE006 8000
SSP0
26
0xE006 C000
DAC
27
0xE007 0000
Timer 2
28
0xE007 4000
Timer 3
29
0xE007 8000
UART2
30
0xE007 C000
UART3
31
0xE008 0000
I2C2
32
0xE008 4000
Battery RAM
33
0xE008 8000
I2S
34
0xE008 C000
SD/MMC Card Interface[2]
35
0xE009 0000 - 0xE01F BFFF Khng s dng
36- 126
0xE01F C000
System Control Block
127
[1] CAN c dng trong cc vi x l LPC2364/66/68, LPC2378, LPC2387, v LPC2388.
[2] The SD/MMC card c dng trong cc vi x l LPC2365/66, LPC2377/78, LPC2387, v
LPC2388.

Trang 18
I.4.5 Phn vng li b nh trong LPC2300 v boot ROM.

I.4.5.1
Nguyn l v nhng ch hot ng.
Mi vng nh trong LPC2300 c mt v tr c nh trong bn b nh. Phn ln mi
khng gian b nh vn lun c nh vnh vin trong cng mt v tr, v loi b s cn thit
phi c cc phn ca m c thit k chy trong phm vi a ch khc nhau.
Bng vector ngt ca ARM7 c phn vng t 0x000 0000 n 0x0000 001C, v th,
mt phn chia ca Boot ROM v SRAM cn c phn vng li c th hot ng trong
nhng ch khc nhau. Vic phn vng li vector ngt lin quan cht ch n B iu khin
Phn vng nh.
Bng 4 a ch nh ngoi l ca ARM
a ch
0x0000 0000
0x0000 0004
0x0000 0008
0x0000 000C
0x0000 0010
0x0000 0014
0x0000 0018
0x0000 001C
Trng hp ngoi l
Reset.
Undefined Instruction.
Software Interrupt.
Prefetch Abort (instruction fetch memory fault).
Data Abort (data access memory fault).
Reserved.
IRQ.
FIQ.
Bng 5 Nhng ch hot ng ca b nh trong LPC2300

Ch
Boot
Loader
mode
Hot ng
Hardware
activation by
any Reset
User
Flash
mode
Software
activation by
boot code
User
RAM
mode
User
External
Memory
mode
Software
activation by
user program
Software
activation by
user code
Cch s dng.
The Boot Loader alwaysexecutes after any reset. The Boot ROM interrupt
vectors are mapped to the bottom of memory to allow handling
exceptions and using interrupts during the Boot Loading process. A sector
of the Flash memory(the Boot Flash) is available to hold part of the Boot
Code.
Activated by the Boot Loader when a valid User Program Signature is
recognized in memory and Boot Loader operation is not forced. Interrupt
vectors are not re-mapped and are found in the bottom of the Flash
memory.
Activated by a User Program as desired. Interrupt vectors are re-mapped
to the bottom of the Static RAM
Activated by a User Program as desired. Interrupt vectors are re-mapped
to external memory bank 0

Trang 19
I.4.5.2
Phn vng li b nh.
Boot ROM c phn vng trn cng ca b nh, mt chng trnh d chim nhiu
hay t b nh u khng nh hng n v tr ca Boot ROM hoc khng thay i phn vng
ca vc t ngt Boot ROM.
Phn vng b nh c cp pht li cho php thc hin qu trnh ngt nhng ch
khc nhau, p dng cho vng vect ngt (32 bytes) v c 32 bytes m rng. M iu khin
vic phn vng c ct gi a ch t 0x0000 0000 v 0x0000 003F. Chng trnh trong b
nh Flash c c iu khin FIQ lu 0x0000 001C. Vect cha trong SRAM, b nh ngoi
v Boot ROM phi cha a ch n iu khin ngt tht s mt cch trc tip hay gin tip
hng qua mt cu lnh khc.
C ba l do cu hnh ny c la chn:
1. cung cp cho cc x l FIQ trong b nh Flash li th l khng phi mt mt
ranh gii b nh gy ra bi nh x li vo ti khon.
2. Gim thiu s cn thit phi cho SRAM v khi ng vector ROM gii quyt
vi bt k gii hn gia khng gian m.
3. cung cp khng gian lu tr cc hng s vt ra ngoi phm vi ca nhng
cu lnh chuyn ng cnh.
Phn vng li b nh bao gm c boot ROM v vector interrupt, tip tc xut hin
trong b nh gc thm vo cc a ch phn vng li b nh
I.4.5.3
iu khin phn vng b nh
iu khin phn vng b nh thay i phn vng ca nhng vector ngt xut hin
a ch 0x0000 0000. M chng trnh s c php chy nhng vng nh khc v iu
khin nhng ngt.
I.4.5.3.1 Thanh ghi iu khin phn vng b nh (MEMMAP 0xE01FC040)
Khi mt iu khin ngoi l cn thit, vi x l s np cu lnh in khin a ch ca

ngoi l cn c vo bng 4 trang 20. Thanh ghi MEMMAP xc nh a ch ngun ca d liu
s np vo bng ny.

Trang 20
Bng 6 Thanh ghi iu khin phn vng b nh

Name
MEMMAP
Description
Access Reset Address

value
Memory mapping control. Selects whether the R/W
0x00 0xE01F C040
ARM interrupt vectors are read from the Boot
ROM, User Flash, or RAM.
Bng 7 Thanh ghi iu khin phn vng b nh - m t bit a ch 0xE01F C040

Bit Symbol Value Description
1:0 MAP
7:2 -
Reset
value
00
Boot Loader Mode. Interrupt vectors are re-mapped to Boot 00
ROM.
01
User Flash Mode. Interrupt vectors are not re-mapped and
reside in Flash.
10
User RAM Mode. Interrupt vectors are re-mapped to Static
RAM.
11
User External Memory Mode (available on LPC2377/78 and
LPC2388 only).
Warning: Improper setting of this value may result in incorrect
operation of the device.
Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.
I.4.5.3.2 Ghi ch s dng iu khin phn vng b nh.
iu khin phn vng b nh ch n gin l la chn mt trong s ba ngun

c sn d liu (mi ngun c 64 byte) cn thit x l cc trng hp ngoi l ARM
(interrupts).

Trang 21
Hnh 13 B nh mc thp cho thy qu trnh ti phn vng b nh

Trang 22
I.5. Khi iu Khin H Thng.

I.5.1 Gii thiu
Khi iu khin h thng bao gm nhiu c tnh h thng v n iu khin nhng thanh ghi
cho mt s chc nng ring bit, khng lin quan n bt c thit b ngoi vi no. Nhng chc nng
l:
Reset.
Brown-Out Detection.
Ng nhp ngoi to ngt.
iu khin/ Thng s h thng.
Bo mt v Tm li code.
AHB configuration.
Mi chc nng c mt hay nhiu thanh ghi ca ring n. Nhng bit khng cn thit trong thanh
ghi s c gi li cho nhng m rng v sau. Nhng chc nng khng lin quan vi nhau khng chia
s chung bt c thanh ghi no.
I.5.2 Chn kt ni ngoi ca khi iu khin h thng.
Bng sau y th hin nhng chn kt ni ngoi lin quan n nhng chc nng ca khi iu
khin h thng.
Bng 8 B nh mc thp cho thy qu trnh ti phn vng b nh
Pin name Pin
direction
EINT0 Input
EINT1
EINT2
EINT3
RESET
Input
Input
Input
Input
Pin description
External Interrupt Input 0- An active low/high level or falling/rising
edge general purpose interrupt input. This pin may be used to wake up
the processor from Idle or Power-down modes.
External Interrupt Input 1- See the EINT0 description above.
External Reset input- A LOW on this pin resets the chip, causing
I/O ports and peripherals to take on their default states, and the
processor to begin execution at address 0x0000 0000.

Trang 23
I.5.3 Cc thanh ghi lin quan.

Bng sau y th hin nhng thanh ghi lin quan n nhng chc nng ca khi iu khin h
thng.
Bng 9 Tm tt cc thanh ghi iu khin h thng
Name
Description
Access Reset
value
Address
R/W
R/W
R/W
0x00
0x00
0x00
0xE01F C140
0xE01F C148
0xE01F C14C
R/W
see
text
0xE01F C180
AHB configuration registers

AHBCFG1
Configures the AHB1 arbiter.
R/W
AHBCFG2
R/W
0x0000 0xE01F C188

0145
0x0000 0xE01F C18C
0145
External interrupts
EXTINT
External Interrupt Flag Register
EXTMODE External Interrupt Mode register
EXTPOLAR External Interrupt Polarity Register
Reset
RSID
Reset Source Identification Register
Configures the AHB2 arbiter.
Syscon miscellaneous registers

SCS
System Control and Status
R/W
0x08
0xE01F C1A0
I.5.4 Reset
C 4 cch Reset trn LPC2300:
Chn RESET (ng nhp Schmitt trigger)

Lnh Reset ca Watchdog.
Reset khi m ngun.
Mch Brown Out Dectection.

Trang 24
Hnh 14 Thit lp li s khi bao gm b m thi gian wakeup

S xc nhn ca bt k ngun reset no : POR, BOD reset, External reset v Watchdog reset
th IRC khi ng. Sau thi gian IRC khi ng (ti a l 60 s ) v sau khi IRC cp pht xung clock
n nh, tn hiu reset c cht v ng b IRC clock.
Sau , hai trnh t sau y bt u cng mt lc:
1. 2-bit IRC wake-up m thi gian bt u khi reset ng b c kch hot. Cc m khi
ng trong ROM bt u chy khi IRC wake-up ht thi gian hn gi (times out). Cc m
khi ng thc hin cc nhim v khi ng v c th nhy n Flash. Nu Flash l khng
sn sng, cc MAM s chn nhng chu k ch i (wait cycles) cho n khi Flash sn
sng.
2. Flash wake-up-timer (9-bit) m thi gian bt u khi reset ng b c kch hot. Sau
Flash wake-up-timer i 100 s . Sau khi times out trnh t khi to Flash c bt u
( tn khong 250 chu k). Sau khi hon thnh, cc MAM s c cp quyn truy cp vo
Flash.

Trang 25
Khi b vi x l bt u x l ti a ch 0, l bc u Reset vector nh x t Boot Block.

Vo thi im , tt c cc thanh ghi x l v thit b ngoi vi c khi to cc gi tr xc
nh.
Sau y l mt v d v mi lin h gia RESET, IRC, v tnh trng x l khi LPC2300 sau
khi reset.
Reset khc nhau c mt s khc bit nh.
Hnh 15 V d khi ng li sau reset

Trang 26
II.4.5.1
Reset Source Identification Register (RSIR - 0xE01F C180)
Thanh ghi cha 1 bit cho tng ngun Reset ring bit. Di y l bng th hin s
tng tc gia 4 ngun Reset.
Bng 10 S tng tc gia 4 ngun Reset
Bit
Symbol
POR
EXTR
WDTR
BODR
Description
Reset
value
Assertion of the POR signal sets this bit, and clears all of the other bits See
in this register. But if another Reset signal (e.g., External Reset) text
remains asserted after the POR signal is negated, then its bit is set. This
bit is not affected by any of the other sources of Reset
Assertion of the RESET signal sets this bit. This bit is cleared by POR, See
but is not affected by WDT or BOD reset.
text
This bit is set when the Watchdog Timer times out and the See
WDTRESET bit in the Watchdog Mode Register is 1. It is cleared by text
any of the other sources of Reset.
This bit is set when the 3.3 V power reaches a level below 2.6 V.If the See
VDD(DCDC)(3V3) voltage dips from 3.3 V to 2.5 V and backs up, the text
BODR bit will be set to 1.If the VDD(DCDC)(3V3) voltage dips from
3.3 V to 2.5 V and continues to decline to the level at which POR is
asserted (nominally 1 V), the BODR bit is cleared. If the
VDD(DCDC)(3V3) voltage rises continuously from below 1 V to a
level above 2.6 V, the BODR will be set to 1. This bit is not affected
by External Reset nor Watchdog Reset. Note:Only in case when a reset
occurs and the POR = 0, the BODR bit indicates if the
VDD(DCDC)(3V3)voltage was below 2.6 V or not.
I.5.5
External interrupt.
Vi x l LPC2300 bao gm bn u vo External interrupt. Ngoi ra, External interrupt c
kh nng wakeup CPU t ch Power iu ny c iu khin bi thanh ghi INTWAKE.
Bng 11 Cc thanh ghi ca External interrupt
Name
EXTINT
EXTMODE
EXTPOLAR
Description

value
The External Interrupt Flag Register R/W
00
0xE01F C140
contains interrupt flags for EINT0,
EINT1, EINT2 and EINT3.
The External Interrupt Mode Register
0xE01F C148
controls whether each pin is edge-or
level-sensitive.
The External Interrupt Polarity
0xE01F C14C
Register controls which level or edge
on each pin will cause an interrupt.

Trang 27
Bng 12 Thanh ghi Flag ca External interrupt (EXTINT).

Bit Symbol Description
0
EINT0
EINT1
EINT2
EINT3
Reset
value
In level-sensitive mode, this bit is set if the EINT0 function is selected for 00
its pin, and the pin is in its active state. In edge-sensitive mode, this bit is
set if the EINT0 function is selected for its pin, and the selected edge occurs
on the pin.
In level-sensitive mode, this bit is set if the EINT1 function is selected for
on the pin.
on the pin.
on the pin.
Bng 13 Thanh ghi Mode ca External interrupt (EXTMODE).

Bit Symbol
0
EXTMODE0
EXTMODE1
EXTMODE2
EXTMODE3
Value Reset
value
0
00
1
0
1
0
1
0
1
Bng 14 Thanh ghi Polar ca External interrupt (EXTPOLAR).

Bit Symbol
0
EXTPOLAR0
EXTPOLAR1
EXTPOLAR2
EXTPOLAR3
Value Reset
value
0
00
1
0
1
0
1
0
1

Trang 28
I.6. M un Tng Tc B Nh (Memory Acceleration Module - MAM).

Khi MAM trong vi x l LPC2300 gp phn ti a hiu sut ca b vi x l ARM khi chy cc
on code trong b nh flash.
Hnh 16 S khi n gin ca MAM

I.7. Khi iu Khin Vect Interrupt (Vectored Interrupt Controller - VIC).
I.7.2 Gii thiu.
LPC2300 h tr 32 vector IRQ interrupt v c 16 mc u tin.
Ct li ca vi x l ARM c 2 interrupt c gi l Interrupt Request (IRQ) v Fast Interrupt
reQuest (FIQ).
Vectored Interrupt Controller (VIC) h tr 32 yu cu interrupt, ta s lp trnh vector tng
ng vi loi interrupt no (IRQ hay FIQ)
Fast Interrupt Request l interrupt c u tin cao nht. Nu c cng u tin th interrupt
vector c ch s nh nht s c lm trc. IRQ c u tin thp hn, cng tng t nh FIQ
nu c nhiu interrupt cng u tin th interrupt no vector c ch s nh hn s c thc thi
trc.

Trang 29
I.7.2 Cc loi thanh ghi VIC.

Bng 15 Cc loi thanh ghi VIC
Name
VICIRQStatus
VICFIQStatus
VICRawIntr
VICIntSelect
VICIntEnable
VICIntEnClr
VICSoftInt
VICSoftIntClear
VICProtection
VICSWPriority
Mask
VICVectAddr0
VICVectAddr1
to
VICVectAddr31
VICVectPriority
0
Description

value
IRQ Status Register. This register reads out the
RO
0
0xFFFF
state of those interrupt requests that are enabled and
F00
classified as IRQ.
FIQ Status Requests. This register reads out the
RO
0
0xFFFF
state of those interrupt requests that are enabled and
F04
classified as FIQ.
Raw Interrupt Status Register. This register
RO
0xFFFF
readsout the state of the 32 interrupt requests /
F08
software interrupts, regardless of enabling or
classification
Interrupt SelectRegister. This register classifies R/W
0
0xFFFF
each of the 32 interrupt requests as contributing to
F0C
FIQ or IRQ
Interrupt EnableRegister. This register controls R/W
0
0xFFFF
which of the 32 interrupt requests and software
F10
interrupts are enabled to contribute to FIQ or IRQ.
Interrupt Enable Clear Register. This register
WO
0xFFFF
allows software to clear one or more bits in the
F14
Interrupt Enable register
Software Interrupt Register. The contents of this R/W
0
0xFFFF
register are ORed with the 32 interrupt requests
F18
from various peripheral functions.
Software Interrupt Clear Register. This register
WO
0xFFFF
allows software
F1C
to clear one or more bits in the Software Interrupt
register.
Protection enable register. This register allows R/W
0
0xFFFF
limiting access to the VIC registers by software
F20
running in privileged mode
Software Priority Mask Register. Allows masking R/W
0xFF 0xFFFF
individual interrupt priority levels in any
FF
F24
combination.
Vector address 0 register. Vector Address Registers R/W
0
0xFFFF
0-31 hold
F100
the addresses of the Interrupt Service routines
(ISRs) for the 32
vectored IRQ slots
Vector address 1 register to Vector address 31 R/W
0
0xFFFF
register.
F104 to
0xFFFF
F17C
Vector priority 0 register. Vector Priority Registers R/W
0xF 0xFFFF
0-31. Each of
F200

Trang 30
these registers designates the priority of the

corresponding
vectored IRQ slot.
VICVectPriority Vector priority 1 register to Vector priority 25
1
to register.
VICVectPriority
25
R/W
0xF
0xFFFF
F204 to
0xFFFF
F264
I.7.3 Kin trc Interrupt
Hnh 17 S khi ca VIC

Nhn vo s khi ta c th thy : Phn interrupt ca LPC2378 c 4 khi: phn interrupt
request, khi status interrupt, khi priority, khi vecto interrupt.
Trong gm :
Khi interrupt request : c vai tr khi bt c interrupt no c bt ln th n s cp nht li
khi status interrupt.
Trang 31
Khi status interrupt c vai tr : cha cc thng tin v cc interrupt hin ti v sinh ra FIQ
Khi vectored interrupt cha thng tin v vector IRQ v a ch cn nhy ti khi c interrupt
Khi priority and generation: c nhim v chn interrupt no s lm, v a ch no s nhy
ti.
I.7.4 Ngun Interrupt
Bng 16 S kt ni ca ngun Interrupt n VIC
Block
Flag(s)
WDT
Watchdog Interrupt (WDINT)

Reserved for Software Interrupts only
Embedded ICE, DbgCommRx
Embedded ICE, DbgCommTX
Match 0 - 1 (MR0, MR1)
Capture 0 - 1 (CR0, CR1)
Match 0 - 2 (MR0, MR1, MR2)
Capture 0 - 1 (CR0, CR1
Rx Line Status (RLS)
Transmit Holding Register Empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
Modem Control Change
Match 0 - 6 of PWM1
Capture 0-1 of PWM1
SI (state change)
SPI Interrupt Flag of SPI (SPIF)
Mode Fault of SPI0 (MODF)
Tx FIFO half empty of SSP1
Rx FIFO half full of SSP1
Rx Timeout of SSP1
Rx Overrun of SSP1
Tx FIFO half empty
Rx FIFO half full
Rx Timeout
Rx Overrun
PLL Lock (PLOCK)
Counter Increment (RTCCIF)
Alarm (RTCALF)
Subsecond Int (RTCSSF)
External Interrupt 0 (EINT0)
ARM Core
ARM Core
TIMER0
TIMER1
UART0
UART1
PWM1
I2C0
SPI, SSP0
SSP 1
PLL
RTC
System Control
(External Interrupts)

VIC
Hex
0
1
2
3
4
Channel # and
Mask
0x0000 0001
0x0000 0002
0x0000 0004
0x0000 0008
0x0000 0010
0x0000 0020
0x0000 0040
0x0000 0080
0x0000 0100
9
10
0x0000 0200
0x0000 0400
11
0x0000 0800
12
13
0x0000 1000
0x0000 2000
14
15
0x0000 4000
0x0000 8000
Trang 32
ADC0
I2C1
BOD
Ethernet
USB
CAN
SD/ MMC
interface
GP DMA
Timer 2
Timer 3
UART 2
UART 3
I2C2
I2 S

External Interrupt 3 (EINT3).
A/D Converter 0 end of conversion
SI (state change)
Brown Out detect
WakeupInt, SoftInt, TxDoneInt,
TxFinishedInt,
TxErrorInt, TxUnderrunInt, RxDoneInt,
RxFinishedInt, RxErrorInt, RxOverrunInt.
USB_INT_REQ_LP,
USB_INT_REQ_HP,
USB_INT_REQ_DMA
CAN Common, CAN 0 Tx, CAN 0 Rx,
CAN 1 Tx, CAN 1 Rx
RxDataAvlbl, TxDataAvlbl,
RxFifoEmpty, TxFifoEmpty, RxFifoFull,
TxFifoFull, RxFifoHalfFull,
TxFifoHalfEmpty, RxActive, TxActive,
CmdActive,DataBlockEnd, StartBitErr,
DataEnd, CmdSent, CmdRespEnd,
RxOverrun, TxUnderrun, DataTimeOut,
CmdTimeOut, DataCrcFail, CmdCrcFail
IntStatus of DMA channel 0, IntStatus of
DMA channel 1
Match 0-3
Capture 0-1
Match 0-3
Capture 0-1
SI (state change)
irq_rx
irq_tx

16
17
18
19
20
21
0x0001 0000
0x0002 0000
0x0004 0000
0x0008 0000
0x0010 0000
0x0020 0000
22
0x0040 0000
23
0x0080 0000
24
0x0100 0000
25
0x0200 0000
26
0x0400 0000
27
0x0800 0000
28
0x1000 0000
29
0x2000 0000
30
31
0x4000 0000
0x8000 0000
Trang 33
I.8. Cc Thit Lp Chn Cho LPC2300

Mi chn trong LPC2378 c th c nhiu chc nng hoc input, output hay lm 1 chc nng c
th ca 1 phn no y. V d nh : P0[1] (port s 0 chn s 1) c th lm chc nng input, output cn
bn hay cng c th lm chc nng l chn nhn d liu ca Control Area Network 1 (CAN1).
Chi tit ca tng chn tham kho trong user manual trang 95. tng y l chng ta bit mi
chn c nhiu chc nng v khi mun s dng chc nng no th ta phi thit lp 1 s gi tr nht nh
cho thanh ghi no .
Nh vy ta s phi c 1 thanh ghi chn chc nng cho tng chn. Thanh ghi l PINSEL, c
10 thanh ghi PINSEL0 -> PINSEL9. Mi 1 chn ca LPC2378 s tng ng vi 2 bit trong 1 thanh
ghi ny.
Bng 17 Chc nng ca cc chn
PINSEL
Chc nng
Gi tr sau khi Reset
00
Chc nng input,output cn bn
00
01
Chc nng s 1
10
Chc nng s 2
11
Chc nng s 3
Mi chn u c th lm input,output, ty vo tng chn m chc nng s 1,2,3 s l g.
Bng 18 a ch ca cc thanh ghi chc nng
Name
Description
Access
Reset Value
Address
Pin mode select register 0.
R/W
00
0xE002 C040
PINMODE0
R/W
0xE002 C044
PINMODE1
R/W
0xE002 C048
PINMODE2
Pin
mode
select
register
3.
R/W
0xE002 C04C
PINMODE3
R/W
0xE002 C050
PINMODE4
R/W
0xE002 C054
PINMODE5
R/W
0xE002 C058
PINMODE6
R/W
0xE002 C05C
PINMODE7
R/W
0xE002 C060
PINMODE8
R/W
0xE002 C064
PINMODE9
Thanh ghi PINSEL0 iu khin cc chc nng ca cc chn. Bit iu khin hng vo thanh ghi
IO0DIR (hoc thanh ghi FIO0DIR nu chc nng nng cao ca GPIO c chn cho cng 0) ch c
hiu lc khi chc nng ca GPIO c chn cho mt chn nht nh. i vi cc chc nng khc th
s c t ng iu khin.

Trang 34
I.9. Tng Quan Chc Nng Cng Input/Ouput Vi X L LPC2300(GPIO)

I.9.1 c im chung
I.9.1.1 Digital I/O ports
GPIO PORT0 v PORT1 mun truy cp cn phi thng qua mt trong hai iu kin
sau : nhm thanh ghi cung cp tnh nng nng cao v cng truy cp tng tc (the group of
registers providing enhanced features and accelerated port access) hoc nhm thanh ghi k
tha (the legacy group of registers). PORT2/3/4 c truy cp nh cng nhanh (fast ports).
I.9.1.2
Interrupt generating digital ports
PORT0 v PORT2 cung cp mt ngt cho mi port.
Mi interrupt c th c lp trnh to ra mt interrupt c cnh ln, xung hoc c
hai ty thuc vo ngi lp trnh.
C th hot ng trong ch ng b hoc khng ng b.
Lin quan n ch Wake-up v Power-down.
C h tr thanh ghi kim tra cnh ln, cnh xung.
I.9.2 a ch thanh ghi
Bng 19 a ch thanh ghi GPIO (legacy APB accessible registers)
Generic Description
Name
IOPIN
IOSET
IODIR
IOCLR
GPIO Port Pin value register. The current state of

the GPIO configured port pins can always be read
from this register, regardless of pin direction. By
writing to this register ports pins will be set to
the desired level instantaneously
GPIO Port Output Set register. This register
controls the state of output pins in conjunction
with the IOCLR register. Writing ones produces
highs at the corresponding port pins. Writing
zeroes has no effect.
GPIO Port Direction control register. This
register individually controls the direction of each
port pin.
GPIO Port Output Clear register. This register
controls the state of output pins. Writing ones
produces lows at the corresponding port pins and
clears the corresponding bits in the IOSET
register. Writing zeroes has no effect.

Access Reset
value
PORTn Register
Address & Name
R/W
NA
IO0PIN - 0xE002 8000

IO1PIN - 0xE002 8010
R/W
0x0
IO0SET - 0xE002 8004

IO1SET - 0xE002 8014
R/W
IO0DIR - 0xE002 8008

IO1DIR - 0xE002 8018
WO
IO0CLR - 0xE002 800C

IO1CLR - 0xE002 801C
Trang 35
Bng 20 a ch thanh ghi GPIO (local bus accessible registers - enhanced GPIO features)
Generic
Name
Description
Access Reset
value
FIODIR
Fast GPIO Port Direction control register. R/W

This register individually controls the
direction of each port pin.
FIOMASK Fast Mask register for port. Writes, sets, R/W

clears, and reads to port (done via writes to
FIOPIN, FIOSET, and FIOCLR, and reads
of FIOPIN) alter or return only the bits
enabled by zeros in this register
FIOPIN
FIOSET
FIOCLR
Fast Port Pin value register using R/W

FIOMASK. The current state of digital port
pins can be read from this register,
regardless of pin direction or alternate
function selection (as long as pins are not
configured as an input to ADC). The value
read is masked by ANDing with inverted
FIOMASK.Writing to this register places
corresponding values in all bits enabled by
zeros in FIOMASK.
Fast Port OutputSet register using R/W
FIOMASK. This register controls the state
of output pins. Writing 1s produces highs at
the corresponding port pins. Writing 0s has
no effect. Reading this register returns the
current contents of the port output register.
Only bits enabled by 0 in FIOMASK can be
altered.
Fast Port Output Clear register using WO
FIOMASK0. This register controls the state
of output pins. Writing 1s produces lows at
the corresponding port pins. Writing 0s has
no effect. Only bits enabled by 0 in
FIOMASK0 can be altered.

0x0
PORTn Register
Address & Name
FIO0DIR - 0x3FFF C000
FIO0MASK - 0x3FFF
C010
FIO1MASK - 0x3FFF
C030
FIO2MASK - 0x3FFF
C050
FIO3MASK - 0x3FFF
C070
FIO4MASK - 0x3FFF
C090
FIO0PIN - 0x3FFF C014
FIO0SET - 0x3FFF C018

FIO0CLR - 0x3FFF C01C

Trang 36
Bng 21 a ch thanh ghi interrupt GPIO

Generic
Name
Description
Access Reset PORTn Register

value Address & Name
IntEnR
GPIO Interrupt Enable for Rising edge. R/W
IntEnF
GPIO Interrupt Enable for Falling edge R/W
IntStatR
GPIO Interrupt Status for Rising edge.
RO
IntStatF
GPIO Interrupt Status for Falling edge.
RO
IntClr
GPIO Interrupt Clear.
WO
IntStatus
GPIO overall Interrupt Status.
RO
0x0
IO0IntEnR - 0xE002 8090

IO2IntEnR - 0xE002 80B0
IO0IntEnR - 0xE002 8094
IO2IntEnR - 0xE002 80B4
IO0IntStatR - 0xE002 8084
IO2IntStatR - 0xE002 80A4
IO0IntStatF - 0xE002 8088
IO2IntStatF - 0xE002 80A8
IO0IntClr - 0xE002 808C
IO2IntClr - 0xE002 80AC
IOIntStatus - 0xE002 8080
I.9.3 Mt s code mu s dng GPIO

V d 1: Truy cp tun t IOSET v IOCLR
Trng thi cu hnh u ra GPIO PIN th c xc nh bng cch ghi vo chn ca thanh ghi
IOSET v IOCLR. Truy cp cui cng vo thanh ghi IOSET / IOCLR s quyt nh u ra cui cng
ca mt chn.
Mi GPIO PIN th c iu khin gm 4

thanh ghi GPIO.
Hng n d liu c 3 thanh ghi l set,
clear, status
Code mu mt chng trnh n gin s dng n flash :

int main(void)
{
unsigned int delay;
unsigned int flasher = 0x00010000;
IODIR1 = 0x00FF0000;
// set tt c cng output

Trang 37
while(1)
{
for(delay = 0;delay<0x10000;delay++)
// delay
{
;
}
IOCLR1 = ~flasher;
//clear cc cng ouput
IOSET1 = flasher;
//set trng thi ca cc cng
flasher = flasher <<1;

if(flasher&0x01000000)
flasher li
//shift led
flasher
0x00010000;
//
Tng
}
}
I.10.
Ethernet
Bng 22 Bng vit tt, nh ngha trong phn ny
Ch vit tt
AHB
CRC
DMA
Double-word
FCS
Fragment
Frame
Half-word
LAN
MAC
MII
MIIM
Octet
Packet
PHY
RMII
Rx
TCP/IP
nh ngha
Advanced High-performance bus
Cyclic Redundancy Check
Direct Memory Access
64 bit entity
Frame Check Sequence (CRC)
A (part of an) Ethernet frame; one ormultiple fragments can add up to a single
Ethernet frame
An Ethernet frame consists of destination address, source address, length
type field, payload and frame check sequence
16 bit entity
Local Area Network
Media Access Control sublaye
Media Independent Interface
MII management
An 8 bit data entity, used in lieu of "byte" by IEEE 802.3
A frame that is transported across Ethernet; a packet consists of a preamble,
a start of frame delimiterand an Ethernet frame.
Ethernet Physical Layer
Reduced MII
Receive
Transmission Control Protocol / Internet Protocol. The most common

Trang 38
Tx
VLAN
WoL
Word
high-level protocol used with Ethernet

Transmit
Virtual LAN
Wake-up on LAN
32 bit entity
I.10.1 c im chung
Ethernet c nhng h tr c bn sau:
10 or 100 Mbps PHY devices bao gm 10 Base-T, 100 Base-TX, 100 Base-FX, and 100
Base-T4.
Ph hp vi IEEE 802.3 v 802.3xFull Duplex Flow Control and Half Duplex.
Truyn dn linh hot.
H tr VLAN frame.
Qun l b nh :
Truyn dn c lp ng thi nhn c b nh m nh x vo shared SRAM.
Qun l DMA vi phn tn / tp hp DMA km theo mng m t khung.
Traffic c ti u ha bng buffering and pre-fetching.
Tnh nng nng cao:
Nhn v lc d liu.
H tr frame Multicast v broadcast cho ch truyn v nhn.
T ng chn FCS (CRC) cho truyn.
C th la chn frame hnh truyn t ng padding.
C th nhn ch Promiscuous.
T ng backoff khi ng v truyn li frame.
H tr qun l nng lng bng clock switching.
H tr qun l nng lng bng Wake-on-LAN.

Trang 39
I.10.2 Kin trc
Hnh 18 S khi Etherrnet

S khi cho khi Ethernet bao gm:
Cc module thanh ghi host c cha cc thanh ghi trong giao din phn mm v x l AHB
truy cp vo khi Ethernet. Thanh ghi host kt ni truyn v nhn c ng d
liu cng nh MAC.
DMA cung cp mt kt ni cho tng th AHB, cho php khi Ethernet c th truy cp vo
SRAM Ethernet c cc m t, vit trng thi ca d liu, c v vit vo b m.
Khi Etherrnet MAC v RMII Adapter kt ni vi off-chip PHY.
ng d liu truyn, bao gm:
Qun l Transmit DMA c d liu t b nh v vit trng thi vo b nh.
Khi transmit retry x l khi Ethernet retry v loi tnh hung xu.
Khi transmit flow control c th chm Ethernet pause frames
ng d liu nhn c, bao gm:
Qun l Receive DMA c t b nh v d liu, trng thi vo b nh.
Khi Ethernet MAC phn loi cc frame da vo header ca frame .
Khi receive filter c th lc cc frame nh vo cc chng trnh lc ring bit.
I.10.3 DMA
Khi Ethernet c thit k cung cp hiu sut ti u ha nh vo DMA. Cc cng c DMA
c kt ni c lp vi AHB bus truyn d liu t CPU ARM7.
B m t (descriptors) c lu tr trong b nh ng thi cha thng tin v fragments n
hoc i ca Ethernet frames. Mt fragment c th l mt phn d liu hoc ton b frame. Mi b m
t cha mt con tr n mt b nh m cha d liu lin kt vi mt fragment, kch thc ca b
m fragment, v chi tit v cch fragment s c truyn ti hoc nhn.
B m t c lu tr trong mt mng trong b nh v c xc nh bng cch ghi con tr
trong khi Ethernet. Cc thanh ghi khc xc nh kch thc ca mng , im n tip theo ca b
Trang 40
m t trong mi mng s c s dng bi cc cng c DMA no, v im n tip theo ca b

m t trong mi mng s c s dng bi cc thit b iu khin Ethernet.
I.10.3 Gi trong Etherrnet
Hnh 19 Ethernet packet fields

I.10.4 M t chc nng cc chn
Bng 23 Ethernet RMII pin descriptions

Pin Name
ENET_TX_EN
ENET_TXD[1:0]
ENET_RXD[1:0]
ENET_RX_ER
ENET_CRS
ENET_REF_CLK
Type
Output
Output
Input
Input
Input
Input
Pin Description
Transmit data enable
Transmit data, 2 bits
Receive data, 2 bits
Receive error.
Carrier sense/data valid
Reference clock
Bng 24 Ethernet MIIM pin descriptions

Pin Name
ENET_MDC
ENET_MDIO
Type
Output
Input/Output
Pin Description
MIIM clock
MI data input and output

Trang 41

Bng 25 a ch thanh ghi Etherrnet
Symbol
MAC registers
MAC1
MAC2
IPGT
IPGR
CLRT
MAXF
SUPP
TEST
MCFG
MCMD
MADR
MWTD
MRDD
MIND
Address
R/W Description
0xFFE0 0000
0xFFE0 0004
0xFFE0 0008
0xFFE0 000C
0xFFE0 0010
0xFFE0 0014
0xFFE0 0018
0xFFE0 001C
0xFFE0 0020
0xFFE0 0024
0xFFE0 0028
0xFFE0 002C
0xFFE0 0030
0xFFE0 0034
0xFFE0 0038 to
0xFFE0 00FC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WO
RO
RO
SA0
SA1
SA2
0xFFE0 0040
0xFFE0 0044
0xFFE0 0048
0xFFE0 004C to
0xFFE0 00FC
R/W
R/W
R/W
0xFFE0 0100
0xFFE0 0104
0xFFE0 0108
0xFFE0 010C
0xFFE0 0110
0xFFE0 0114
0xFFE0 0118
0xFFE0 011C
0xFFE0 0120
0xFFE0 0124
0xFFE0 0128
0xFFE0 012C
0xFFE0 0130 to
0xFFE0 0154
R/W
RO
R/W
R/W
R/W
RO
R/W
R/W
R/W
R/W
R/W
RO
0xFFE0 0158
0xFFE0 015C
0xFFE0 0160
RO
RO
RO
Control registers
Command
Status
RxDescriptor
RxStatus
RxDescriptorNumber
RxProduceIndex
RxConsumeIndex
TxDescriptor
TxStatus
TxDescriptorNumber
TxProduceIndex
TxConsumeIndex
TSV0
TSV1
RSV

MAC configuration register 1.

MAC configuration register 2.
Back-to-Back Inter-Packet-Gap register.
Non Back-to-Back Inter-Packet-Gap register.
Collision window / Retry register.
Maximum Frame register.
PHY Support register.
Test register.
MII Mgmt Configuration register.
MII Mgmt Command register.
MII Mgmt Address register.
MII Mgmt Write Data register.
MII Mgmt Read Data register.
MII Mgmt Indicators register.
Reserved, user software should not write ones
to reserved bits. The value read from a reserved
bit is not defined.
Station Address 0 register.
bit is not defined.
Command register.
Status register.
Receive descriptor base address register.
Receive status base address register.
Receivenumber of descriptors register.
Receive produce index register.
Receive consume index register.
Transmit descriptor base address register.
Transmit status base address register.
Transmit number of descriptors register.
Transmit produce index register.
Transmit consume index register
bit is not defined.
Transmit status vector 0 register.
Transmit status vector 1 register.
Receive status vector register.
Trang 42
0xFFE0 0164 to
0xFFE0 016C
FlowControlCounter
FlowControlStatus
Rx filter registers
RxFliterCtrl
RxFilterWoLStatus
RxFilterWoLClear
HashFilterL
HashFilterH
0xFFE0 0170
0xFFE0 0174
0xFFE0 0178 to
0xFFE0 01FC
R/W
RO
0xFFE0 0200
0xFFE0 0204
0xFFE0 0208
0xFFE0 020C
Receive filter control register.

Receive filter WoL status register.
Receive filter WoL clear register.
bit is not defined.
Hash filter table LSBs register.
Hash filter table MSBs register.
bit is not defined.
0xFFE0 0210
0xFFE0 0214
0xFFE0 0218 to
0xFFE0 0FDC
Module control registers

IntStatus
0xFFE0 0FE0
IntEnable
0xFFE0 0FE4
IntClear
0xFFE0 0FE8
IntSet
0xFFE0 0FEC
0xFFE0 0FF0
RO
R/W
WO
WO
PowerDown
R/W
0xFFE0 0FF4
0xFFE0 0FF8

bit is not defined.
Flow control counter register.
Flow control status register.
bit is not defined.

Interrupt status register.

Interrupt enable register.
Interrupt clear register.
Interrupt set register.
bit is not defined.
Power-down register.
bit is not defined.
Trang 43
I.11.
CAN
I.11.1 nh ngha
Controller Area Network (CAN) l mt giao thc truyn thng hiu sut cao trong truyn thng
d liu ni tip. CAN Controller c thit k nhm mc ch cung cp chc nng ca giao thc
CAN.
Vi iu khin vi b iu khin CAN trn chip ny c s dng xy dng mng li khu
vc no mt cch mnh nht bng cc h tr thng qua kim sot thi gian thc vi mc bo
mt rt cao. Mt s ng dng l : t, cng nghip, v cc mng tc cao cng nh chi ph thp,
ghp ni cc h thng dy in. Kt qu l h thng dy in gim mnh v nng cao kh nng sa
cha v gim st.
Khi CAN c thit k vi h tr ng thi nhiu CAN bus v d nh gateway, switch, hoc
router. Module CAN bao gm hai yu t: the controller v the Acceptance Filter.
Tt c cc thanh ghi v b nh RAM c truy cp vi 32 bit.
I.11.2 Kin trc
Khi iu khin CAN bao gm cc khi :
APB Interface
Acceptance Filter
Vectored Interrupt Controller (VIC)
CAN Transceiver
Common Status Registers
Hnh 20 Khi iu khin CAN

Trang 44
Khi giao din APB (AIB) cung cp quyn truy cp vo tt c cc thanh ghi iu khin CAN.
B qun l giao din logic (IML) bin dch cc lnh t CPU, kim sot a ch thanh ghi CAN
v cung cp thng tin trng thi v interrupt t CPU.
B m truyn dn (TXB) l giao din gia qun l Interface Management Logic (IML) v Bit
Stream Processor (BSP). Mi Transmit Buffer c th lu tr tt c thng tin c truyn trn mng
CAN c vit bi CPU v c bi BSP.
Hnh 21 Giao din b tr ca TXB t c bn n m rng

B m nhn (RXB) c th truy cp vo Double Receive Buffer, RXB nm gia CAN
Controller Core Block v APB Interface Block v stores cha tt c thng tin nhn c t CAN Bus
line. Vi s h tr t Double Receive Buffer th RXB c th x l mt thng ip trong khi mt tin
nhn ang c nhn.
Hnh 22 Giao din b tr ca RXB t c bn n m rng

Trang 45
B qun l li Logic (EML) chu trch nhim v hn ch li. EML c thng bo li t BSP
v sau thng bo cho BSP v IML v thng k li.
Bit Timing Logic (BTL) kim sot serial CAN Bus line v x l cc Bus line lin quan n Bit
Timing. BTL cn dng ng b trn phn cng (hard synchronization) cng nh ti ng b trn
phn mm (soft synchronization) nu cn thit trong tng lai.
Bit Stream Processor (BSP) l mt chui, kim sot lung d liu gia Transmit Buffer,
Receive Buffers v CAN Bus.
CAN controller self-tests bao gm hai ty chn sau : Global Self-Test (thit lp cc yu cn t
nhn bit trong ch bnh thng - normal Operating Mode) v Local Self-Test (thit lp cc yu cn
t nhn bit trong ch t kim tra - Self Test Mode).
I.11.3 a ch b nh
Bng 26 a ch b nh ca khi CAN
Address Range
0xE003 8000 - 0xE003 87FF
0xE003 C000 - 0xE003 C017
0xE004 0000 - 0xE004 000B
0xE004 4000 - 0xE004 405F
0xE004 8000 - 0xE004 805F
Used for
Acceptance Filter RAM.
Acceptance Filter Registers.
Central CAN Registers.
CAN Controller 1 Registers.
CAN Controller 2 Registers.
I.11.4 Thanh ghi iu khin CAN

Bng 27 a ch thanh ghi iu khin CAN
Generic
Name
Description
MOD
IER
Controls the operating mode of the

CAN Controller.
Command bits that affect the state of
the CAN Controller.
Global Controller Status and Error
Counters
Interrupt status, Arbitration Lost
Capture, Error Code Capture
Interrupt Enable
BTR
Bus Timing
EWL
Error Warning Limit
CMR
GSR
ICR

Access CAN1 Register

Address &
Name
R/W
CAN1MOD 0xE004 4000
WO
CAN1MOD 0xE004 4004
RO
CAN1MOD 0xE004 4008
RO
CAN1MOD 0xE004 400C
R/W
CAN1MOD 0xE004 4010
R/W
CAN1MOD 0xE004 4014
R/W
CAN1MOD 0xE004 4018
CAN2 Register
Address &
Name
CAN2MOD 0xE004 8000
CAN2MOD 0xE004 8004
CAN2MOD 0xE004 8008
CAN2MOD 0xE004 800C
CAN2MOD 0xE004 8010
CAN2MOD 0xE004 8014
CAN2MOD 0xE004 8018
Trang 46
SR
Status Register
RO
RFS
Receive frame status
R/W
RID
Received Identifier
R/W
RDA
Received data bytes 1-4
R/W
RDB
Received data bytes 5-8
R/W
TFI1
Transmit frame info (Tx Buffer 1)
R/W
TID1
Transmit Identifier (Tx Buffer 1)
R/W
TDA1
Transmit data bytes 1-4 (Tx Buffer 1
R/W
TDB1
R/W
TFI2
Transmit data bytes 5-8 (Tx Buffer

1)
TID2
R/W
TDA2
R/W
TFI3

2)
2)
TID3
R/W
TDA3

3)
3)
R/W
TDB2
TDB3

R/W
R/W
R/W
R/W
CAN1MOD 0xE004 401C

CAN1MOD 0xE004 4020
CAN1MOD 0xE004 4024
CAN1MOD 0xE004 4028
CAN1MOD 0xE004 402C
CAN1MOD 0xE004 4030
CAN1MOD 0xE004 4034
CAN1MOD 0xE004 4038
CAN1MOD 0xE004 403C
CAN1MOD 0xE004 4040
CAN1MOD 0xE004 4044
CAN1MOD 0xE004 4048
CAN1MOD 0xE004 404C
CAN1MOD 0xE004 4050
CAN1MOD 0xE004 4054
CAN1MOD 0xE004 4058
CAN1MOD 0xE004 405C
CAN2MOD 0xE004 801C

CAN2MOD 0xE004 8020
CAN2MOD 0xE004 8024
CAN2MOD 0xE004 8028
CAN2MOD 0xE004 802C
CAN2MOD 0xE004 8030
CAN2MOD 0xE004 8034
CAN2MOD 0xE004 8038
CAN2MOD 0xE004 803C
CAN2MOD 0xE004 8040
CAN2MOD 0xE004 8044
CAN2MOD 0xE004 8048
CAN2MOD 0xE004 804C
CAN2MOD 0xE004 8050
CAN2MOD 0xE004 8054
CAN2MOD 0xE004 8058
CAN2MOD 0xE004 805C
Trang 47
I.12.
USB
I.12.1 nh ngha
Universal Serial Bus (USB) l 1 bus c bn dy h tr lin kt gia mt my ch vi mt hoc
nhiu (ln n 127) thit b ngoi vi. B iu khin my ch cp pht bng thng cho USB vi cc
thit b gn vo thng qua giao thc token. Cc bus h tr cm vo v cu hnh ng cho cc thit b.
Mi giao dch c vn hnh bi cc b iu khin my ch.
I.12.2 Kin trc
Hnh 23 S khi thit b iu khin USB

B Truyn tn hiu Analog: Cc thit b iu khin USB c tch hp b thu pht tng t
(ATX). ATX USB gi / nhn c tn hiu hai chiu D + v D- ca USB bus.
B Serial Interface Engine (SIE): l hardwired c tc rt nhanh v khng cn s can thip
ca firmware. N x l chuyn giao d liu gia cc thit b u cui trong b m EP_RAM v
USB bus. Cc chc nng ca khi ny bao gm: synchronization pattern recognition, parallel/serial
conversion, bit stuffing/de-stuffing, CRC checking/generation, PID verification/generation, address
recognition, and handshake evaluation/generation.
B Endpoint RAM (EP_RAM): l b m u cui c thc hin nh mt SRAM da trn
gii thut FIFO.
B iu khin a ch EP_RAM: x l logic chuyn d liu i / n EP_RAM. Ba ngun c
th truy cp n: CPU, SIE, v DMA.

Trang 48
B giao din thanh ghi: cho php CPU iu khin hot ng ca cc thit b iu khin USB.
N cng cung cp mt cch vit truyn d liu n b iu khin v c nhn d liu t b iu
khin.
B DMA v giao din bus ch: Khi c kch hot cho mt thit b u cui, d liu chuyn
n DMA gia RAM nh vo AHB bus v b m ca thit b u cui trong EP_RAM.
GoodLink: Good USB connection indication c cung cp thng qua cng ngh GoodLink.
Khi cc thit b c cu hnh thnh cng th cc n LED s ON vnh vin v trong qu trnh
suspend th LED s OFF.
Bng 28 a ch thanh ghi thit b USB
Name
Description
Port select egister (LPC2378 only)

USBPortSel
USB Port Select
Clock control registers
USBClkCtrl
USB Clock Control
USBClkSt
USB Clock Status
Device interrupt registers
USBIntSt
USB Interrupt Status
USBDevIntSt
USB Device Interrupt Status
USBDevIntEn
USB Device Interrupt Enable
USBDevIntClr
USB Device Interrupt Clear
USBDevIntSet
USB Device Interrupt Set
USBDevIntPri
USB Device Interrupt Priority
Endpoint interrupt registers
USBEpIntSt
USB Endpoint Interrupt Status
USBEpIntEn
USB Endpoint Interrupt Enable
USBEpIntClr
USB Endpoint Interrupt Clear
USBEpIntSet
USB Endpoint Interrupt Set
USBEpIntPri
USB Endpoint Priority
Endpoint realization registers
USBReEp
USB Realize Endpoint
USBEpInd
USB Endpoint Index
USBMaxPSize
USB MaxPacketSize
USB transfer registers
USBRxData
USB Receive Data
USBRxPLen
USB Receive Packet Length
USBTxData
USB Transmit Data
USBTxPLen
USB Transmit Packet Length
USBCtrl
USB Control
SIE Command registers
USBCmdCode
USB Command Code
Access Reset value
Address
R/W
0x0000 0000
0xFFE0 C110
R/W
RO
0x0000 0000
0x0000 0000
0xFFE0 CFF4
0xFFE0 CFF8
R/W
RO
R/W
WO
WO
WO
0x8000 0000
0x0000 0010
0x0000 0000
0x0000 0000
0x0000 0000
0x00
0xE01F C1C0
0xFFE0 C200
0xFFE0 C204
0xFFE0 C208
0xFFE0 C20C
0xFFE0 C22C
RO
R/W
WO
WO
WO
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0xFFE0
0xFFE0
0xFFE0
0xFFE0
0xFFE0
R/W
WO
R/W
0x0000 0003
0x0000 0000
0x0000 0008
0xFFE0 C244
0xFFE0 C248
0xFFE0 C24C
RO
RO
WO
WO
R/W
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0xFFE0 C218
0xFFE0 C220
0xFFE0 C21C
0xFFE0 C224
0xFFE0 C228
WO
0x0000 0000
0xFFE0 C210
C230
C234
C238
C23C
C240
Trang 49
USBCmdData
DMA registers
USBDMARSt
USBDMARClr
USBDMARSet
USBUDCAH
USBEpDMASt
USBEpDMAEn
USBEpDMADis
USBDMAIntSt
USBDMAIntEn
USBEoTIntSt
USB Command Data
USB DMA Request Status

USB DMA Request Clear
USB DMA Request Set
USB UDCA Head
USB Endpoint DMA Status
USB Endpoint DMA Enable
USB Endpoint DMA Disable
USB DMA Interrupt Status
USB DMA Interrupt Enable
USB End of Transfer Interrupt
Status
USBEoTIntClr
Clear
USBEoTIntSet
Set
USBNDDRIntSt USB New DD Request Interrupt
Status
USBNDDRIntClr USB New DD Request Interrupt
Clear
USBNDDRIntSet USB New DD Request Interrupt
Set
USBSysErrIntSt USB System Error Interrupt
Status
USBSysErrIntClr USB SystemError Interrupt
Clear
USBSysErrIntSet USB SystemError Interrupt Set
I.13.
RO
0x0000 0000
0xFFE0 C214
RO
WO
WO
R/W
RO
WO
WO
RO
R/W
RO
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0xFFE0 C250
0xFFE0 C254
0xFFE0 C258
0xFFE0 C280
0xFFE0 C284
0xFFE0 C288
0xFFE0 C28C
0xFFE0 C290
0xFFE0 C294
0xFFE0 C2A0
WO
0x0000 0000
0xFFE0 C2A4
WO
0x0000 0000
0xFFE0 C2A8
RO
0x0000 0000
0xFFE0 C2AC
WO
0x0000 0000
0xFFE0 C2B0
WO
0x0000 0000
0xFFE0 C2B4
RO
0x0000 0000
0xFFE0 C2B8
WO
0x0000 0000
0xFFE0 C2BC
WO
0x0000 0000
0xFFE0 C2C0
UART
I.13.1 Gii thiu

Trc ht UART l g: Universal Asynchronous Receiver Transmitter.
Dng truyn v nhn d liu ni tip. LPC2378 h tr 4 b truyn nhn ni tip UART0,
UART1, UART2 v UART3 (truyn nhn 16 byte vi c ch FIFO). Tip theo chng ta s xem xt
n phn kin trc ca UART.
I.13.2 Kin trc
Mi s truyn nhn thng tin gia CPU v UART u thng qua APB
Vic nhn tn hiu ca UART : thng qua chn RXD v i vo thanh ghi dch (UnRSR) sau
d liu s c chuyn qua thanh ghi cha d liu (UART RX Buffer Register FIFO) v d liu
s y ch CPU ti c.

Trang 50
Vic truyn tn hiu ca UART : cng tng t nh th, CPU truyn d liu vo trong buffer
trong thanh ghi UnTHR (UART TX Holding Register FIFO), sau d liu t thanh ghi ny c
chuyn sang thanh ghi dch (UnTSR) v t t truyn ra ngoi thng qua chn TXD
V tc truyn d liu UART cho php cho thit lp tc baud thng qua cc thanh ghi.
V ta phi t tm ra tc baud no hp l nht (tc xc sut li trn ng truyn t nht) Vn
ny s c tho lun trong phn sau.
Cc s thit lp interrupt trong thanh ghi UnIER v UnIIR
Thng tin t vic truyn nhn (2 chn TX v RX) c lu trong thanh ghi UnLSR.
Thng tin iu khin nm trong thanh ghi UnLCR
Hnh 24 S khi LPC2300 UART0, 2 v 3

Trang 51
Hnh 25 S khi LPC2300 UART1

UART giao tip vi bn ngoi qua 2 chn TXD v RXD.
B Interrupt : iu khin vic interrupt, lu tr status v khi no c interrupt s y ra chn
UnINTR
B iu khin Clock UnBRG iu khin vic sinh ra CLK t 2 d liu vo l UnDLL v
UnDLM
B truyn d liu : UnTX c 2 thanh ghi : thanh ghi cha d liu v thanh ghi truyn serial ra
ngoi thng qua chn TXD
B nhn d liu : UnRX gm c 2 thanh ghi l thanh ghi cha d liu v thanh ghi truyn
serial. D liu nhn vo chn RXD s y vo thanh ghi truyn serial ri a vo thanh ghi nhn d
liu.
Trang 52

I.13.3.1 UnRBR - UART Receiver Buffer Register (U0RBR - 0xE000 C000, U1RBR
- 0xE001 C000, U2RBR - 0xE007 8000, U3RBR - 0xE007 C000 khi DLAB =0)
UnRBR l thanh ghi ch c (read only, cha 8 bit data) cha thong tin c nht c th
c c bi CPU. truy xut c vo thanh ghi ny th bit DLAB trong thanh ghi LCR
phi l 0.
I.13.3.2 UnTHR - UART Transmit Holding Register (U0THR - 0xE000 C000,
U1THR - 0xE001 0000, U2THR - 0xE007 8000, U3THR - 0xE007 C000 khi DLAB = 0)
UnTHR cng tng t thanh ghi UnRBR nhng n dng truyn d liu nn n s
l thanh ghi cha d liu mi nht c truyn. UnTHR l thanh ghi ch ghi (write only, 8 bit
data) DLAB phi l 0 khi ta truy xut vo thanh ghi ny.
I.13.3.3 UnIER - UART Interrupt Enable Register (U0IER - 0xE000 C004, U1IER
- 0xE001 0004, U2IER - 0xE007 8004, U3IER - 0xE007 C004 khi DLAB = 0)
UnIER c s dng kch hot 3 interrupt (RBR interrupt, THRE interrupt, RX Line
Status Interrupt) v cho php auto-baud rate v time out. Chi tit tham kho trang 333.
I.13.3.4 UnIIR - UART Interrupt Identification Register (U0IIR - 0xE000 C008,
U1IIR - 0xE001 0008, U2IIR - 0xE007 8008, U3IIR - 0x7008 C008)
UnIIR cung cp cho chng ta l interrupt g v u tin ca n nh th no. Nu
mt interrupt xy ra trong qu trnh truy cp UnIIR, interrupt s c ghi nhn cho vic truy
cp UnIIR tip theo.
V u tin interrupt th c 3 u tin:
Receive Line Status (RLS) (u tin cao nht)
Receive Data available (RDA) (u tin mc 2)
Character Time out Indicator (CTI) (u tin mc 2)
THRE interrupt
I.13.3.5 UnDLL - UART Divisor Latch LSB Register v UnDLM - UART Divisor
Latch MSB Registers (U0DLL - 0xE000 C000, U1DLL - 0xE001 0000 , U1DLM - 0xE001
0004 , U2DLL - 0xE007 8000, U3DLL - 0xE007 C000 v U0DLM - 0xE000 C004, U2DLL
- 0xE007 8004, U3DLL - 0xE007 C004 khi DLAB = 1)

Trang 53
UnDLL l mt phn ca UART Baud Rate Generator. Thanh ghi UnDLL v UnDLM
dng chia mt s 16 bit, thanh ghi UnDLL cha 8 bit thp cn thanh ghi UnDLM cha 8
bit cao.
I.13.3.6 UnFCR - UART FIFO Control Register (U0FCR - 0xE000 C008, U1FCR
- 0xE001 0008, U2FCR - 0xE007 8008, U3FCR - 0xE007 C008)
UnFCR thanh ghi iu khin cc hot ng ca UARTn Rx v TX FIFOs
I.13.3.7 UnLCR - UART Line Control Register (U0LCR - 0xE000 C00C, U1LCR 0xE001 000C , U2LCR - 0xE007 800C, U3LCR - 0xE007 C00C)
UnLCR thit lp cc nh dng truyn v nhn.
I.13.3.8 UnLSR - UART Line Status Register ((U0LSR - 0xE000 C014, U1LCR 0xE001 000C, U2LSR - 0xE007 8014, U3LSR - 0xE007 C014)
UnLSR cha cc thng tin v vic truyn nhn (li, thanh ghi cha d liu ang rng ).
I.13.3.9 UnSPR - UART Scratch Pad Register (U0SCR - 0xE000 C01C, U1SCR 0xE001 001C , U2SCR - 0xE007 801C U3SCR - 0xE007 C01C)
UnSCR khng nh hng n hot ng UARTn. Thanh ghi ny cho php vit and /
or v c theo quyt nh ca ngi dng.
I.13.3.10 UnACR - UART Auto-baud Control Register (U0ACR - 0xE000 C020,
U1ACR - 0xE001 0020 , U2ACR - 0xE007 8020, U3ACR - 0xE007 C020)
UnACR kim sot qu trnh o tc clock / d liu v c th c c v vit theo
ca ngi dng.
I.13.3.11 UFDR - UART Fractional Divider Register (U0FDR - 0xE000 C028,
U1FDR - 0xE001 0028 , U2FDR - 0xE007 8028, U3FDR - 0xE007 C028)
UFDR kim sot clock pre-scaler ca cc baud rate v c th c c/vit theo
ca ngi dng.
I.13.3.12 Auto Flow Chart
khi ng cho UART u tin ta phi thit lp chn TXD v RXD cho n
UART0 (c chn TXD0 l P0.2 v RXD0 l P0.3)
UART3 (c chn TXD3 l P0.0 hay P4.28 v RXD3 l P0.1 hay P4.29)

Trang 54
Nh ta bit 1 chn c th c nhiu chc nng v mun n lm chc nng g ta phi

thit lp cho n thng qua thanh ghi PINSEL.
VD : ta thit lp cho UART0 th dng cu lnh sau :
PINSEL0 |= 0x00000050;
/* RxD0 and TxD0 */
PINSEL0 &= ~0xA0;

Tip theo thit lp thanh ghi iu khin UnLCR ( to format cho vic truyn nhn)
(Nh c s dng Parity checking khng? S dng bao nhiu bit Stop bit )
Set tc baud
Cc thanh ghi dng set tc baud: UnACR, UnFDR,UnDLL, UnDLM
UnACR thit lp mode (C 2 mode: mode 0 v mode 1), khi ng auto baud, kt
thc auto baud
Mode 0: Baud rate c tnh ton da trn 2 cnh xung ca chn RX (1 cnh
xung l ca Start bit v 1 cnh xung l ca tn hiu d liu)
Hnh 26 Autobaud mode 0

Trang 55
Mode 1: Baud rate c tnh ton gia cnh xung v cnh ln ca Start bit (n
chnh l di ca Start bit)
Hnh 27 Autobaud mode 1

Auto baud c th sinh ra 2 interupt: UnIIR ABTOInt interrupt (khi counter overflow)
v UnABEOInt interrupt khi m auto baud thnh cng
Baud rate phi nm trong khong ny:
=
16 215
16 (2 + + + )
Cng thc tnh tc baud:
16 256 + (1+
Mc d c cng thc tnh nhng tc baud vn khng phi l tc truyn sinh

ra t li nht. By gi ta s xem xt 1 gii thut tnh ton sinh ra c baud rate hp l nht.

Trang 56
Hnh 28 S flow chart

Trang 57
Ci t hm interrupt: Xem li phn thit lp cc interrupt bit r hn

Cng vic cui cng l kch hot cho UART bt u hot ng:
VD: cho UART0
#define IER_RBR
0x01
#define IER_THRE
0x02
#define IER_RLS
0x04
U0IER = IER_RBR | IER_THRE | IER_RLS;

Gi d liu:
Kim tra c cho php gi nu cho php th a 1 byte d liu vo thanh ghi
UnTHR, tt c cho php gi.
Khi no gi xong th c s t ng bt ln (trong lm interrupt)
Tip tc gi cho n khi ht d liu
Nhn d liu: c thc hin lun trong hm interrupt
Kim tra thanh ghi UnLSR, nu bit 0 Receive Data Ready RDR l 1 tc l ang c
d liu
c thanh UnRBR ly d liu (Khi ta c thanh ghi ny th c interrupt trong

UnLSR t ng b xa i)
VD khi ng UART0
#define IER_RBR
0x01
#define IER_THRE
0x02
#define IER_RLS
0x04
PINSEL0 |=0x00000050; //set RxD0 va TxD0

PINSEL0 &=~0xA0;
U0LCR=0x83 ; //8 bits, khng parity,1 stop bit
Fdiv=(Fpclk /16) / baudrate;
U0DLM=Fdiv/256;
U0DLL=Fdiv%256;

Trang 58
I.14.
SPI
I.14.1 nh ngha
SPI l giao din kt ni full duplex. SPI c th x l masters v slaves c kt ni thng
qua cc bus. Ch c th giao tip gia mt master v mt slave trn giao din trong mt truyn d
liu nht nh. Trong mt truyn d liu, master lun lun gi 8-16 bit d liu cho cc slave, v slave
lun lun gi mt byte d liu n master.
I.14.2 Truyn d liu trong SPI

Hnh sau y l mt s thi gian minh ha bn nh dng truyn d liu khc nhau m
c sn vi SPI. S thi gian ny minh ha mt truyn d liu 8-bit duy nht.
Hnh 29 Truyn d liu trong SPI (CPHA = 0 v CPHA = 1)

Trang 59
Bng 29 Mi quan h gia d liu SPI v giai on ca Clock

CPOL and
CPHA First data driven
Other data driven
Data sampled
settings
CPOL = 0, CPHA = 0
Prior to first SCK risingedge
SCK falling edge
SCK rising edge
CPOL = 0, CPHA = 1
First SCK rising edge
SCK rising edge
SCK rising edge
CPOL = 1, CPHA = 0
Prior to first SCK falling edge
SCK rising edge
SCK rising edge
CPOL = 1, CPHA = 1
First SCK falling edge
SCK falling edge
SCK rising edge

Bng 30 a ch thanh ghi trong SPI
Name
Description
Access Reset
Address
Value
S0SPCR
SPI Control Register. This register R/W
0x00
0xE002 0000
0x00
0xE002 0004
0x00
0xE002 0008
0x00
0xE002 000C
0x00
0xE002 001C
controls the operation of the SPI.

S0SPSR
SPI Status Register. This register shows RO

the status of the SPI.
S0SPDR
SPI Data Register. This bi-directional R/W

register provides the transmit and
receive data for the SPI. Transmit data is
provided to the SPI0 by writing to this
register. Data received by the SPI0 can
be read from this register.
S0SPCCR
SPI Clock Counter Register. This R/W

register controls the frequency of a
masters SCK0.
S0SPINT
SPI Interrupt Flag. This register contains R/W

the interrupt flag for the SPI interface.

Trang 60
I.14.3.1
SPI Control Register (S0SPCR - 0xE002 0000)
S0SPCR thanh ghi iu khin thit lp cc bit hot ng ca SPI0 nh bng di y.

Bng 31 M t chc nng cc bit ca thanh ghi S0SPCR
Bit
Symbol
Value
Description
Reset
Value
1:0
Reserved, user software should not write ones to reserved NA

bits. The value read from a reserved bit is not defined.
BitEnable
The SPI controller sends and receives 8 bits of data per 0

transfer.
The SPI controller sends and receives the number of bits

selected by bits 11:8.
CPHA
Clock phase control determines the relationship between 0

the data and the clock on SPI transfers, and controls when
a slave transfer is defined as starting and ending. Data is
sampled on the first clock edge of SCK. A transfer starts
and ends with activation and deactivation of the SSEL
signal.
Data is sampled on the second clock edge of the SCK. A

transfer starts with the first clock edge, and ends with the
last sampling edge when the SSEL signal is active.
CPOL
Clock polarity control.
SCK is active high.
MSTR
SCK is active low.
Master mode select.
The SPI operates in Slave mode.
LSBF
The SPI operates in Master mode.
LSB First controls which direction each byte is shifted

Trang 61
when transferred.SPI data is transferred MSB (bit 7) first.
SPIE
SPI data is transferred LSB (bit 0) first.
Serial peripheral interrupt enable.
SPI interrupts are inhibited.

1
A hardware interrupt is generated each time the SPIF or

MODF bits are activated.
11:8
BITS
When bit 2 of this registeris 1, this field controls the 0000

number of bits per transfer:
15:12 -
1000
8 bits per transfer
1001
9 bits per transfer
1010
10 bits per transfer
1011
1100
1101
1110
1111
0000
Reserved, user software should not write ones to reserved NA

bits. The value read from a reserved bit is not defined.

Trang 62
I.14.3.2
SPI Status Register (S0SPSR - 0xE002 0004)
S0SPSR thanh ghi iu khin thit lp cc bit hot ng ca SPI0 nh bng di y.

Bng 32 M t chc nng cc bit ca thanh ghi S0SPSR
Reset
Value
2:0 -
Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.
ABRT
Slave abort. When 1, this bit indicates that a slave abort has occurred. This 0
bit is cleared by reading this register.
MODF
Mode fault. when 1, this bit indicates that a Mode fault error has occurred.
This bit is cleared by reading this register, then writing the SPI0 control
register.
ROVR
Read overrun. When 1, this bit indicates that a read overrun has occurred.
This bit is cleared by reading this register.
WCOL
Write collision. When 1, this bit indicates that a write collision has
occurred. This bit is cleared by reading this register, then accessing the SPI
data register.
SPIF
SPI transfer complete flag. When1, this bit indicates when a SPI data
transfer is complete. When a master, this bit is set at the end of the last cycle
ofthe transfer. When a slave, this bit is set on the last data sampling edge
of the SCK. This bit is cleared by first reading this register, then accessing
the SPI data register.
Note:this is not the SPI interrupt flag. This flag is found in the
SPINT register.
I.14.3.3
SPI Data Register(S0SPDR - 0xE002 0008)
Thanh ghi d liu 2 chiu cung cp kh nng truyn v nhn cho SPI. D liu truyn
th c cung cp nh SPI v c vit vo thanh ghi ny. Tng t d liu nhn t SPI cng
c c t thanh ghi ny. Khi mt master hot ng, thanh ghi s bt u vic vit d liu,

Trang 63
khi SPIF status c set th d liu truyn b block, ng thi trng thi thanh ghi s khng
c c na.
I.14.3.4
SPI Clock Counter Register (S0SPCCR - 0xE002 000C)
Thanh ghi ny iu khin tn s SCK, ng thi cho s chu k PCLK to nn 1 clock

SPI. Gi tr ca thanh ghi ny phi lun lun l s chn dn n bit 0 luon lun l 0. ng thi
gi tr ca thanh ghi lun lun ln hn hoc bng 8.
I.14.3.5
SPI Test Control Register (SPTCR - 0xE002 0010)
Cc bit ca thanh ghi SPTCR ch nhm vo mc ch nht nh, khng s ng trong

cc chc nng bnh thng. C th tham kho thm bng di y.
Bng 33 M t cc bit ca thanh ghi SPTCR
Reset
Value
read from a reserved bit is not defined
7:1 Test
SPI test mode. When 0, the SPI operates normally. When 1, SCK will 0
always be on, independent of master mode select, and data availability
setting.
I.14.3.6
SPI Test Status Register (SPTSR - 0xE002 0014)
Cc bit ca thanh ghi SPTCR ch nhm vo mc ch nht nh, khng s ng trong

cc chc nng bnh thng. C th tham kho thm bng di y.
Bng 34 M t cc bit ca thanh ghi SPTSR
Bit
Symbol
Description
Reset
Value
2:0
ABRT
Slave abort.
MODF
Mode fault.
ROVR
Read overrun.

Trang 64
WCOL
Write collision.
SPIF
SPI transfer complete flag
I.14.3.7
SPI Interrupt Register (S0SPINT - 0xE002 001C)
Thanh ghi cha cc c ca interrupt.

I.14.4 Kin trc
Hnh 30 S khi SPI

Khi SPI bao gm:
B SPI REGISTER INTERFACE

B SPI SHIFT REGISTER
B SPI CLOCK GENERATOR &DETECTOR
B SPI STATE CONTROL
B OUTPUT ENABLE LOGIC

Trang 65
I.15.
I2C
I.15.1 Gii thiu

I2C l giao thc kt ni vi cc thit b bn ngoi, nh LCD, b nh ngoi, ...
Giao tip chun I2C, c th thit lp ch Master, Slave hay Master/Slave.
C ch trng ti, cho php truyn nhn d liu lin tc m khng b gin on d liu.
Xung c th thay i ph hp vi tc truyn.
Truyn nhn 2 chiu gia Master v Slave.
ng b bng xung tun t cho php nhiu thit b vi tc truyn nhn khc nhau
giao tip trn cng mt knh.
I.15.2 Nguyn l hot ng ca I2C

C 2 loi d liu c chp nhn trn knh truyn I2C.
D liu c gi t Master n Slave. Byte u tin l a ch ca Slave. Sau l chui
byte d liu cn truyn. Slave cn gi tr v ACK i vi mi byte nhn.
D liu gi t Slave n Master. Slave nhn byte u tin, cng l a ch ca Slave, c
gi bi Master. Slave tr v ACK. Sau Salve gi chui byte d liu cn truyn. Master
cn gi tr v ACK i vi mi byte nhn, ngoi tr byte d liu cui cng. Sau khi nhn
tt c cc byte d liu, Master s gi NACK. Master cng l thit b to ra tt c cc xung
ng b v tn hiu START / STOP. Trc khi tn hiu START (cng l tn hiu bt u
ca mt qu trnh chuyn d liu tuu t khc), knh truyn I2C s vn c tch cc.
Giao thc I2C hng n byte, v hot ng 4 ch : Master truyn, Master nhn, Slave
truyn v Slave nhn. LPC2300 c 3 giao tip I2C, ring b I2C[0] c th iu khin tt thit b
LPC2300 m khng nh hng n cc thit b cn li trn knh truyn.
I.15.3 Cc ch hot ng ca I2C
I.15.3.1 Master truyn.
Khi Master ch truyn v Slave ch nhn. Thanh ghi I2CONSET phi
c thit lp nh sau. I2EN phi c gn = 1 kch hot chc nng I2C. Nu bit AA = 0
th giao tip I2C s nhn ra bt c a ch no nu c mt thit b khc ang l Master trn knh
truyn.

Trang 66
Bng 35 Thanh ghi I2CnCONSET c s dng trong ch Master

Bit
7
Symbol Value
-
6
5
4
3
2
1
0
I2EN
STA
STO
SI
AA
1
0
0
0
0
Trong ch ny, bit R/W nn l 0, tc l ghi. Byte u tin gi i ch a ch ca
thit b nhn (7 bit) v bit R/W quyt nh chiu ca d liu. Giao tip I2C s khi ng vo
ch Master truyn khi chng trnh phn mm gn STA = 1. Giao tip I2C s gi tn hiu
START khi knh truyn rnh. Sau khi START c truyn, bit SI s c gn = 1, v gi tr
ca thanh ghi I2STAT l 0x08. Byte gm a ch ca Slave v bit R/W c truyn vo thanh
ghi I2DAT, sau bit SI c xo = 0. Bit SI c xo bng cch gn 1 vo bit SIC trong
thanh ghi I2CONCLR.
Sau khi truyn byte cha a ch Slave v bit R/W, v ACK c tr v, bit SI li c
gn = 1, thanh ghi I2STAT lc ny c th mang gi tr 0x18, 0x20 hay 0x38 ( ch Master);
0x66, 0x78 hay 0xB0 ( ch Slave).
Hnh 31 nh dng ch Master truyn

I.15.3.2 Master nhn.
ch ny, d liu c Slave gi v. Qu trnh truyn nhn tng t ch
Master truyn. Tuy nhin, bit R/W c gn = 1, tc l c. Khi a ch ca Slave v bit
R/W c gi, ACK s c tr v, bit SI li c gn = 1, thanh ghi I2STAT lc ny c th
mang gi tr 0x40, 0x48 hay 0x38 ( ch Master); 0x68, 0x78 hay 0xB0 ( ch Slave).

Trang 67
Hnh 32 nh dng ch Master nhn

Nu tn hiu START c khi to mt ln na, giao tip I2C ca LPC2300 c th tr
v ch Master truyn.
Hnh 33 Ch Master nhn chuyn thnh Master truyn sau khi gi START lp li
I.15.3.3 Ch Slave nhn
D liu s c gi t Master n, thit lp ch ny, thanh ghi I2ADR v
I2CONSET phi c thit lp nh sau:
Bng 36 Thanh ghi I2CnCONSET c s dng trong ch Slave
Bit
7
Symbol Value
-
6
5
4
3
2
1
0
I2EN
STA
STO
SI
AA
1
0
0
0
1
Sau khi cc thanh ghi I2ADR v I2CONSET c thit lp, giao tip I2C s ch n
khi n c gn a ch. Nu bit R/W l 0, giao tip ny l Slave nhn, ngc li, n s tr
thnh Slave truyn. Sau khi byte cha a ch Slave v bit R/W c nhn, SI c gn = 1 v
Trang 68
I2STAT c xc lp. Thanh ghi ny c th c nhn gi tr th hin tnh trng ca knh

truyn.
Hnh 34 nh dng ch Slave nhn

I.15.3.4 Ch Slave truyn.
ch ny, bit R/W c gi tr 1. Phn cng s t ng nhn dng a ch ca chnh
n. Khi a ch ny c pht hin, mt ngt s c yu cu. Nu vi x l yu cu vo ch
Master th phi ch cho n khi knh truyn rnh. V nu c ch trng ti b mt i th giao
tip I2C lp tc chuyn thnh ch Slave.
Hnh 35 nh dng ch Slave truyn

Trang 69
I.15.4 Kt ni vt l
Hnh 36 Cu hnh bus I2C

Bng 37 I2C PIN
Pin
SDA0,1,2
SCL0,1,2
Type
Input/Ouput
Input/Ouput

Description
I2C serial Data
I2C serial Clock
Trang 70
I.15.5 S khi ca I2C
Hnh 37 S khi I2C

Trang 71
I.15.5.1 B lc ng vo v iu chnh ng ra.

Nhng tn hiu ng vo c ng b vi xung ni b, v cc gai tn hiu ngn hn
3 xung ng h s c loi b.
Ng ra cho I2C cng c thit k c bit p ng c t ca I2C.
I.15.5.2 Thanh ghi a ch I2ADDR
Thanh ghi ny s cha 7 bit a ch v c dng trong trng hp thit b l Slave
(truyn hay nhn). Bit cui cng (LSB) c dng nhn dng li gi a ch chung (0x00).
I.15.5.3 B so snh.
B so snh s pht hin v yu cu ngt khi 7 bits a ch Slave trng vi a ch Slave
ca chnh n (7 bits cao trong thanh ghi I2ADR). B so snh cng pht hin trng hp byte
nhn u tin l li gi a ch tng qut (0x00). Khi c yu cu ngt, cc bit trng thi cng
c gn gi tr.
I.15.5.4 Thanh ghi dch I2DAT.
Thanh ghi 8 bits ny cha mt byte d liu cn truyn hay va nhn c. D liu
trong I2DAT lun dch t phi sang tri (bit MSB c dch u tin). Thanh ghi I2DAT lun
cha gi tr byte cui cng xut hin trn knh truyn.
I.15.5.5 Xung ng b.
Hnh 38 Xung clock ng b

Trang 72
I.15.5.6 B to xung tun t

B to xung ny hot ng khi thit b ng vai tr Master, v c tt khi thit b
ng vai tr Slave. Tn s v t l xung tch cc c th lp trnh thng qua vic gn gi tr cho
2 thanh ghi l I2CSCLL v I2CSCLH.
I.15.5.7 iu khin v nh thi.
B iu khin/ nh thi c chc nng to ra xung dch thanh ghi I2DAT, kch khi
b so snh, to ra hay pht hin tn hiu START/ STOP, nhn v truyn bit ACK, iu khin
ch Master hay Slave, pht hin nhng iu kin yu cu ngt v theo di tnh trng ca
knh truyn I2C.
I.15.5.8 Thanh ghi iu khin I2CONSET v I2CONCLR
Cc thanh ghi ny cha nhng bit m gi tr ca chng quyt nh chc nng ca cc
khi I2C, bt u, khi to hay kt thc vic truyn tn hiu tun t. Cc thanh ghi ny cng
quyt nh tc truyn, pht hin a ch v tn hin ACK.
Hnh 39 a ch thanh ghi I2C
Generic
Description
Access Reset
Name
value
0x00
I2Cn Register Name &

Address
I2C0CONSET - 0xE001 C000
I2CONSE
I2C Control Set Register.When a one is R/W
written to a bit of this register, the
I2C1CONSET - 0xE005 C000
corresponding bit in the I2C control
I2C2CONSET - 0xE008 0000
register is set. Writing a zero has no

effect on the corresponding bit in the
I2C control register.
I2STAT
I2C
Status
Register.During
I2C RO
0xF8
I2C0STAT - 0xE001 C004
operation, this register provides detailed
I2C1STAT - 0xE005 C004
status codes that allow software to
I2C2STAT - 0xE008 0004
determine the next action needed.

I2DAT
I2C Data Register.During master or R/W

slave transmit
mode, data to be

0x00
I2C0DAT - 0xE001 C008

I2C1DAT - 0xE005 C008
Trang 73
I2C2DAT - 0xE008 0008
transmitted is written to this register.

During master or slave receive mode,
data that has been received may be read
from this register.
I2ADR
I2C Slave Address Register.Contains
I2C0ADR - 0xE001 C00C
the 7 bit slave address for operation of
I2C1ADR - 0xE005 C00C
the I2C interface in slave mode, and is
I2C2ADR - 0xE008 000C
not used in master mode. The least

significant bit determines whether a
slave responds to the general call
address.
I2SCLH
I2SCLL
SCH Duty Cycle Register High Half R/W
0x04
I2C0SCLH - 0xE001 C010
Word.Determines the high time of the
I2C1SCLH - 0xE005 C010
I2C clock
I2C2SCLH - 0xE008 0010
SCL Duty Cycle Register Low Half R/W
0x04
I2C0SCLL - 0xE001 C014
Word.Determines the low time of the
I2C1SCLL - 0xE005 C014
I2C clock. I2nSCLL and I2nSCLH
I2C2SCLL - 0xE008 0014
together determine the clock frequency

generated by an I2C master and certain
times used in slave mode.
NA
I2C0CONCLR - 0xE001 C018
I2CONCL
I2C Control Clear Register.When a one WO
is written to a bit of this register, the
I2C1CONCLR - 0xE005 C018
corresponding bit in the I2C control
I2C2CONCLR - 0xE008 0018
register is cleared. Writing a zero has no

effect on the corresponding bit in the
I2C control register.

Trang 74
I.15.6.1 I2C Control Set Register (I2C[0/1/2]CONSET: 0xE001 C000, 0xE005

C000, 0xE008 0000)
I2CCONSET l thanh ghi iu khin cc bit ca thanh ghi I2CON nh bng di y.
Bng 38 M t cc bit ca thanh ghi I2CCONSET
Bit
Symbol
1:0 2
3
4
5
6
7
Description
Reserved. User software should not write ones to reserved bits. The value
Assert acknowledge flag.
I2C interrupt flag.
STOP flag.
START flag.
I2C interface enable.
AA
SI
STO
STA
I2EN
-
Reset
Value
NA
0
0
0
0
0
-
I.15.6.2 I2C Control Clear Register (I2C[0/1/2]CONCLR: 0xE001 C018, 0xE005

C018, 0xE008 0018)
I2CCONCLR l thanh ghi iu khin cc bit ca thanh ghi I2CON nh bng di y.
Bng 39 M t cc bit ca thanh ghi I2CCONCLR
Bit
Symbol
1:0 2
3
4
AA
SIC
-
5
6
7
STAC
I2ENC
-
Description
Assert acknowledge Clear bit
I2C interrupt Clear bit.
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
START flag Clear bit.
I2C interface Disable bit.
Reset
Value
NA
0
0
0
0
0
-
I.15.6.3 I2C Status Register (I2C[0/1/2]STAT - 0xE001 C004, 0xE005 C004,

0xE008 0004)
Mi thanh ghi I2CSTAT phn nh trng thi tng ng ca I2C.
I.15.6.4 I2C Data Register (I2C[0/1/2]DAT - 0xE001 C008, 0xE005 C008, 0xE008
0008)
Trang 75
I2CDAT c nhim v cha cc d liu c truyn hoc cc d liu va nhn c.

CPU cng c th c v ghi vo thanh ghi ny. D liu trong I2CDAT lun lun chuyn t
phi sang tri: bit u tin c truyn i l MSB (bit 7), v sau khi mt byte c nhn,
bit u tin ca d liu nhn c t ti MSB ca I2CDAT.
I.15.6.5
I2C Slave Address Register (I2C[0/1/2]ADR - 0xE001 C00C,
0xE005 C00C, 0xE008 000C)
I2CADR ch c thit lp ch Slave, ch master thanh ghi ny khng c
hiu lc.
I.15.6.6
I2C SCL High Duty Cycle Register (I2C[0/1/2]SCLH - 0xE001
C010, 0xE0015 C010, 0xE008 0010)
Tnh cho SCL la chn khong thi gian HIGH
I.15.6.7
I2C SCL Low Duty Cycle Register (I2C[0/1/2]SCLL - 0xE001 C014,
0xE0015 C014, 0xE008 0014)
Tnh cho SCL la chn khong thi gian LOW
I.15.6.8
La chn c tc d liu I2C v duty cyclethch hp
Phn mm phi set gi tr ca I2SCLH v I2SCLL la chn tc d liu v duty

cycle thch hp.

Trang 76
I.16.
TIMER
I.16.1 Gii thiu

C 2 chc nng chnh : ta c th dng lm ng h chy thi gian, c th m s s kin
(bn trong hay bn ngoi). Sau mi khong thi gian c quy nh trc hay sau 1 s s kin th
timer s sinh ra 1 interrupt (chng trnh s nhy n a ch cha hm interrupt v thc thi hm )
LPC2378 h tr 4 b timer 0,1,2,3 , tt c u 32 bit
I.16.2 Hot ng ca TIMER
Thanh ghi TC : l thanh ghi m (thi gian hay s kin). C sau thi gian hay s kin th thanh
ghi TC s tng ln. Tng n khi bng gi tr trong thanh ghi MRn (n = 0-3) th s sinh ra 1 interrupt.
Interrupt ny c th reset TC, stop timer ... (Ty vo chng ta thit lp gi tr l bao nhiu cho thanh
ghi TnMCR).
I.16.3.1 Interrupt Register (T[0/1/2/3]IR - 0xE000 4000, 0xE000 8000, 0xE007 0000,
0xE007 4000)
TnIR gm 4 bit interrupt. Khi mt interrupt c to ra th cc bit ca TnIR c set
mc cao, nu khng l mc thp.
I.16.3.2 Timer Control Register (T[0/1/2/3]CR - 0xE000 4004, 0xE000 8004,
0xE007 0004, 0xE007 4004)
TCR c s dng kim sot cc hot ng ca Timer / Counter.
I.16.3.3 Count Control Register (T[0/1/2/3]CTCR - 0xE000 4070, 0xE000 8070,
0xE007 0070, 0xE007 4070)
TnCTCR c s dng la chn gia ch Timer v Counter, v trong ch
Counter chn chn v cnh m.
I.16.3.4 Timer Counter registers (T0TC - T3TC, 0xE000 4008, 0xE000 8008,
0xE007 0008, 0xE007 4008)
TnTC s tng ln khi c kch hot m.
I.16.3.5 Prescale register (T0PR - T3PR, 0xE000 400C, 0xE000 800C, 0xE007
000C, 0xE007 400C)
TnPR quy nh c th gi tr ti a ca Prescale Counter

Trang 77
I.16.3.6 Prescale Counter register (T0PC - T3PC, 0xE000 4010, 0xE000 8010,
0xE007 0010, 0xE007 4010)
TnPC kim sot phn chia PCLK bi mt s gi tr khng i trc khi n c p
dng cho Timer Counter. iu ny cho php kim sot phn gii ca b m thi gian so
vi thi gian ti a trc khi trn b m thi gian.
I.16.3.7
Match Registers (MR0 - MR3)
MRn lin tc so snh gi tr vi Timer Counter : khi hai gi tr bng nhau th cc hot
ng s t kch hot. Hot ng c th l to ra mt interrupt, reset Timer Counter, ng b
m v c iu khin bi thanh ghi MCR.
I.16.3.8 Match Control Register (T[0/1/2/3]MCR - 0xE000 4014, 0xE000 8014,
0xE007 0014, 0xE007 4014)
MCR c s dng kim sot nhng g hot ng c thc hin khi mt MRn
bng gi tr Timer Counter.
I.16.3.9
Capture Registers (CR0 - CR3)
Mi Capture ng k c kt hp vi mt thit b chn v c th c load gi tr

Timer Counter khi mt vn no xy ra trn chn . Cc thit lp trong thanh ghi
Capture Control Register s xc nh chc nng s c kch hot, v liu c capture no tch
cc cnh ln/cnh xung ca chn hay khng.
I.16.3.10 Capture Control Register (T[0/1/2/3]CCR - 0xE000 4028, 0xE000 8028,
0xE007 0028, 0xE007 4028)
TnCCR c s dng kim sot xem mt trong bn thanh ghi Capture ng thi
np vi gi tr vo Timer Counter khi Capture gi xy ra, v c mt interrupt cng c to
ra.
I.16.3.11 External Match Register (T[0/1/2/3]EMR - 0xE000 403C, 0xE000 803C,
0xE007 003C, 0xE007 403C)
TnEMR cung cp c kim sot v tnh trng ca cc chn trong EM
I.16.4 V d hoat ng ca Timer

Trang 78
Hnh 40 Chu k ca mt timer vi PR=2, MRx=6 v interrupt, reset c kch hot
Hnh 41 Chu k ca mt timer vi PR=2, MRx=6 v interrupt, stop c kch hot

I.16.5 Kin trc
Nhn vo hnh bn di ta c th thy 1 cch tng qut hot ng ca timer:
u tin clock PCLK a vo Prescale Counter (thanh ghi ny s iu khin vic chia clock
PCLK) c th l mi PCLK vo th thanh ghi Prescale Counter s tng ln 1, n tng ln n khi no
bng gi tr trong thanh ghi Precale Register th thanh ghi TC s tng ln 1. Thanh ghi TC c tng ln
nh th cho n khi no bng vi gi tr trong thanh ghi MRn th s sinh ra 1 interrupt.
Ngoi ra th cn c thanh ghi TCR ( iu khin c cho timer chy hay khng)
V cc thanh ghi Capter Register load gi tr thanh ghi TC vo khi cn thit.

Trang 79
Hnh 42 S khi ca Timer

Trang 80
II. CCH S DNG BOARD MCB2300

II.16.1 Gii thiu board thc tp MCB 2300
Board th nghim MCB2300 cho php to ra v chy nhng chng trnh trn h thit b
LPC23xx ca NXP. Board gm c 2 giao din serial, load, u vo analog, 2 giao din CAN, mn
hnh LCD, USB, Ethernet, v 8 n LED, tt c l s khi u pht trin cc ARM tip theo. Board
th nghim c cc phin bn khc nhau l MCB2360, MCB2370, MCB 2387 v MCB 2388.
Board MCB 2360 thng dng vi vi iu khin NXP LPC2368.
Board MCB 2370 s dng vi iu khin NXP LPC2378 trong c mt gi kch thc ln
hn v s lng pin hn so vi NXP LPC2368 hoc LPC2387. Board MCB 2387 v 2388 c thm
USB "A" v kt ni mini-USB h tr USB-OTG.
II.16.2 Kit th nghim MCB2300
Bn trong mt b kit th nghim MCB 2300 bao gm
Board th nghim MCB 2300.
Hng dn nhanh Vision IDE.
Bn gii thiu tng quan v cng c pht trin ca ARM.
Mt CD-ROM cha:
o Bn
dng
th
chng
trnh
RealView
MDK-ARM
Microcontroller
Development Kit.
o Mt s chng trnh v d chy trn board MCB2300.
o File hng dn s dng ca board MCB2300.
Chng
trnh
chy
trn
board
MCB2300
th
tm
thy
KEIL\ARM\RV30\BOARDS\KEIL\MCB2300 trn CD-ROM. Tt c cc v d ny u c

th dch v chy trn bn dng th.

Trang 81
II.16.3 c im chnh ca MCB2300.board

LPC2300 MCUs
58KB On-chip RAM (for MCB2370)
98KB On-chip RAM (for MCB2388)
512KB On-chip FLASH
C hai cng giao tip serial.
C hai cng giao tip CAN.
Cng Ethernet.
LCD hin th.
LF Amplifier.
iu khin in p tng t cho cng vo
ADC.
Giao din JTAG np v chy debug.
Hnh 43 Board MCB 2370

II.16.4 Chun b v phn cng.
s dng board MCB2300, chng ta cn chun b:
Board th nghim MCB2300.
My tnh chun IBM cn trng:
2 cng USB : 1 cng cung cp ngun in v mt cng dng
1 cng COM RS-232 nu s dng cch np bng ISP thng qua cng giao tip
download/debug.
serial.
Trang 82
B giao tip JTAG : bao gm Adapter JTAG v 2 dy cp ni USB.

Trong TH cn s dng tin ch Flash Magic Utility mt dy cp serial, 1 u c/1 u
ci, ngn hn 3m.
II.16.5 Chun b v phn mm.
H iu hnh Microsoft Windows.
Phn mm Keil Vision
Phn mm RealView MDK-ARM Evaluation Tools.
Cc v d vit cho MCB2300 c km theo cc b MDK-ARM, DB-ARM v Keil ARM
Evalution Toolkits.
II.16.6 Ci t board th nghim MCB2300.
Sau khi chun b y cc yu cu v phn cng v phn mm, chng ta c th tin
hnh cc bc sau y ci t v sn sng th nghim trn board MCB2300.
II.16.6.1 Ci t board.
Board MCB2300 dng ngun in t cng USB.
Hnh 44 Board MCB2300 vi cng USB

Board MCB2300 kt ni trc tip n phn mm Keil Vision Debugger bng adapter Keil
ULINK USB-JTAG, khng cn ci t thm bt c phn mm no trn board.

Trang 83
II.16.6.2
Cc thnh phn quan trng trn board MCB2300.
Hnh 45 Board MCB2300 vi ch thch trn hnh

II.16.6.3
Kt ni vi U-LINK.
Hnh 46 Board MCB2300 vi kt ni ULink

Bc 1: kt ni U-LINK vi PC thng qua cable USB.
Bc 2: kt ni U-LINK n cng JTAG nm trn board MCB2300.
Bc 3: cp ngun cho board MCB2300 bng cabke USB.
Bc 4: thit lp mc xung JTAG cho adapter U-LINK.
Cho hot ng board MCB2300.

Trang 84
Trong phn mm Vision, thit lp b Debug trong hp thoi Project\Options for

Target\Debug.
Chn Use: ULINK ARM Debugger trong danh sch th xung.
Click ln nt Setting m hp thoi ARM Target Driver Setup.
Danh sch th xung Max JTAG Clock dng ch nh xung JTAG cao nht
c dng giao tip vi board th nghim. Nn chn gi tr 200 kHz board
MCB2300 hot ng tt nht.
ULINK2 JTAG c thm chn RTCK (Return Clock). Nu s dng adapter ULINK2, chng ta
c th thit lp Max JTAG Clock l 200 kHz hoc RTCK.
Hnh 47 Setup ARM

II.16.6.4
Kt ni thng qua giao tip Serial
Bc 1, thit lp jumper trn board MCB2300
J9 v J10 : ON.
J13 : OFF.
Bc 2, cp ngun cho board MCB2300 bng cabke USB.

Bc 3, Kt ni board MCB2300 vo my tnh qua cng COM t cng COM0 trn board.
Bc 4, Xc nhn kt ni bng tin ch Flash Magic.
Chy Flash Magic v thit lp thng s nh sau:

Trang 85
Xc nhn cng COM bng lnh ISP Read Device Signature.
Ca s sau y s hin th thng s kt ni.

Trang 86
II.16.7 Thit lp jumper trn board MCB2300.

Cc jumper trn board MCB2300, y cng l thng s mc nh trong TH kt ni board thng
qua ULINK2.
Jumper
State Description
J1 - USB (D-)
ON
Connects USB Line D- to the USB connector.
J2 - USB (D+)
ON
Connects USB Line D+ to the USB connector.
J3 - AOUT
ON
Connects AOUT via LF amplifier to the loudspeaker.
J4 -
--
Not used
J5 - UMODE
ON
Allows soft-connect of the USB device by issuing a software restart via

P0.14
J6 - AD0.0
ON
Connects POT1 potentiometer to AIN0 for analog input demonstration.
J8 - INT0
ON
Enable INT0 Push Button.
J9 - RST
ON
Enables Reset via COM0.
J10 - ISP
OFF
Disables In-System Programming via COM0.
J11 - LED
ON
Enables Port2.0 - Port2.7 LEDs.
J13 - ETM
ON
Enables the Embedded Trace Macrocell (so that the USB soft-connect and
the LED's can be used)

Trang 87
PH LC
IU KHIN LED
Trn board MCB2300 gm c 8 con led nh, t P2.0 n P2.7. s dng ta ch vic set cc chn
l chn output. iu ny c th c thc hin thng qua hm LED_Init.
/* Function that initializes LEDs
*/
void LED_Init(void) {
PINSEL10 = 0;
FIO2DIR
/* Disable ETM interface, enable LEDs */
= 0x000000FF;
/* P2.0..7 defined as Outputs
*/
FIO2MASK = 0x00000000;
}
Ngoi ra iu khin cng nh xut gi tr nht nh ra LED ta dng hm bt - LED_On, tt LED_Off v xut - LED_Out.
/* Function that turns on requested LED
*/
void LED_On (unsigned int num) {

FIO2SET = (1 << num);
}
/* Function that turns off requested LED
*/
void LED_Off (unsigned int num) {

FIO2CLR = (1 << num);
}
/* Function that outputs value to LEDs
*/
void LED_Out(unsigned int value) {

FIO2CLR = 0xFF;
/* Turn off all LEDs
FIO2SET = (value & 0xFF);
*/
/* Turn on requested LEDs
*/
}
Trang 88
IU KHIN LCD
Trn board MCB2300 c mt LCD 16x2 (16 ct v 2 hng) v bin tr dng chnh tng
phn. Vic s dng LCD ny s kh n gin nu nh ta c cc hm b tr t th vin LCD.h v
LCD_4bit.c vi cc hm tng ng vi chc nng nht nh nh sau:
Thit lp LCD controller
void lcd_init
(void);
Xa mn hnh LCD
void lcd_clear
(void);
Xut k t ra LCD
void lcd_putchar (char c);
Thit lp v tr ca cursor trn LCD, column v line tng ng vi s ct v hng ca LCD.
void set_cursor
(unsigned char column, unsigned char line);
Xut chui bt k ra LCD.

void lcd_print
(unsigned char const *string);

Trang 89
KT LUN
Ti liu tham kho
[1] Trang WEB www.nxp.com
[2] Trang WEB www.keil.com
[3] User manual LPC23xx
[4] a cd LPC_3_2007
[5] Tng quan vi x l LPC2378. Hng dn s dng board MCB2300 ng Vit Hng,
Trn Trung Tn.
Kt lun
Cng vic lm c:
Nghin cu kin trc v tp lnh ARM7
Nghin cu v s dng board MCB2300
Nghin cu 1 s chc nng c bn ca LPC2378
Interrupt
Ethernet
Timer
CAN
USB
UART
SPI
I2C
Chng trnh demo:
Chy led
ng h hin th LCD

Trang 90

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I HC QUC GIA THNH PH H CH MINH

TRNG I HC BCH KHOA

TNG QUAN VI X L LPC2300

Ging vin hng dn

Nguyn Quc Tun

Sinh vin thc hin

TP. HCM, 12/2013

Phc Lc Hnh ............................................................................................................................................ IV

TNG QUAN V VI X L LPC2300 ........................................................................................... 3

M t chung v LPC2300 .................................................................................................... 3

a Ch B Nh Trong LPC2300 ...................................................................................... 10

I.4.1 T chc b nh v a ch ca cc thit b ngoi vi........................................................... 10

Khi iu Khin H Thng. .............................................................................................. 23

I.5.1 Gii thiu ......................................................................................................................... 23

M un Tng Tc B Nh (Memory Acceleration Module - MAM). ............................. 29

Khi iu Khin Vect Interrupt (Vectored Interrupt Controller - VIC). .................... 29

I.7.2 Gii thiu. ........................................................................................................................ 29

Cc Thit Lp Chn Cho LPC2300 .................................................................................. 34

Tng Quan Chc Nng Cng Input/Ouput Vi X L LPC2300(GPIO) ......................... 35

I.9.1 c im chung ............................................................................................................... 35

Kin trc ...................................................................................................................... 40

Gi trong Etherrnet ....................................................................................................... 41

M t chc nng cc chn............................................................................................. 41

a ch thanh ghi .......................................................................................................... 42

Kin trc ...................................................................................................................... 44

Thanh ghi iu khin CAN ........................................................................................... 46

I.12. USB .................................................................................................................................... 48

Kin trc ...................................................................................................................... 48

a ch thanh ghi .......................................................................................................... 49

I.13. UART ................................................................................................................................. 50

Gii thiu ..................................................................................................................... 50

Kin trc ...................................................................................................................... 50

a ch thanh ghi .......................................................................................................... 53

I.14. SPI ...................................................................................................................................... 59

Truyn d liu trong SPI .............................................................................................. 59

a ch thanh ghi .......................................................................................................... 60

Kin trc ...................................................................................................................... 65

I.15. I2C ...................................................................................................................................... 66

Gii thiu ..................................................................................................................... 66

Nguyn l hot ng ca I2C ....................................................................................... 66

Cc ch hot ng ca I2C ...................................................................................... 66

S khi ca I2C ....................................................................................................... 71

a ch thanh ghi .......................................................................................................... 73

I.16. TIMER ............................................................................................................................... 77

Gii thiu ..................................................................................................................... 77

Hot ng ca TIMER ................................................................................................. 77

a ch thanh ghi .......................................................................................................... 77

V d hoat ng ca Timer ........................................................................................... 78

Kin trc ...................................................................................................................... 79

II. CCH S DNG BOARD MCB2300 ............................................................................................ 81

Hnh 1. S khi LPC2361/62 .......................................................................................................... 5

Hnh 41 Chu k ca mt timer vi PR=2, MRx=6 v interrupt, stop c kch hot....................... 79

Bng 1 c im tng qut LPC2300 .................................................................................................. 4

Nhm Sinh vin thc hin

KHOA HC & K THUT MY TNH

Trong s nghip cng nghip ha v hin i ha hin nay, khoa hc v

KHOA HC & K THUT MY TNH

I. TNG QUAN V VI X L LPC2300

KHOA HC & K THUT MY TNH

KHOA HC & K THUT MY TNH

Hnh 1. S khi LPC2361/62

KHOA HC & K THUT MY TNH

Hnh 2 S khi LPC2364/65/66/67/68