DSD Programs VHDL Verilog

DIGITAL SYSTEM DESIGN
LAB PROGRAMS
(VHDL/VERILOG WITH TEST BENCH)
Half adder
entity ha is
Port ( a,b : in STD_LOGIC;
sum,carry : out STD_LOGIC);
end ha;
architecture Behavioral of ha is
begin
sum <= a xor b;
carry <= a and b;
end Behavioral;
Full Adder ( using 2 half adders)

entity fa is
Port ( a,b,c : in STD_LOGIC;
s,cout : out STD_LOGIC);
end fa;
architecture Behavioral of fa is
component ha
Port(a,b : in std_logic;
sum,carry : out std_logic);
end component;
component or_gate
Port(a,b : in std_logic;
z : out std_logic);
end component;
signal s1,c1,c2:STD_LOGIC;
begin
u1:ha port map (a,b,s1,c1);
u2:ha port map (c,s1,s,c2);
u3:or_gate port map (c1,c2,cout);
end Behavioral;
ENTITY fa_test_bench IS -- TEST BENCH
END fa_test_bench;
ARCHITECTURE behavior OF fa_test_bench IS
COMPONENT fa_bhe
PORT(a,b,c : IN std_logic;
s,cout : OUT std_logic);
END COMPONENT;
signal a,b,c,s,cout : std_logic := '0';
BEGIN
uut: fa_bhe PORT MAP (a,b,c,s,cout);
stim_proc: process
begin
a <='0';b<='0';c<='0'; wait for 10ns;
a <='0';b<='0';c<='1'; wait for 10ns;

a <='0';b<='1';c<='0'; wait for 10ns;
a <='0';b<='1';c<='1'; wait for 10ns;
a <='1';b<='0';c<='0'; wait for 10ns;
a <='1';b<='0';c<='1'; wait for 10ns;
a <='1';b<='1';c<='0'; wait for 10ns;
a <='1';b<='1';c<='1'; wait for 10ns;
end process;
END;
Parallel Adder
entity pa is
Port ( fa,fb : in STD_LOGIC_VECTOR (3 downto 0);
fcin : in STD_LOGIC;
fsum : out STD_LOGIC_VECTOR (4 downto 0)
fcout : out STD_LOGIC);
end pa;
architecture Behavioral of pa is
component fa
Port(a,b,cin : in std_logic;
s,cout : out std_logic);
end component;
signal ft:std_logic_vector(3 downto 1);
begin
u1:fa Port map (fa(0),fb(0),fcin,fsum(0),ft(1));
u2:fa Port map (fa(1),fb(1),ft(1),fsum(1),ft(2));
u3:fa Port map (fa(2),fb(2),ft(2),fsum(2),ft(3));
u4:fa Port map (fa(3),fb(3),ft(3),fsum(3), fcout);
end Behavioral;
ENTITY pa_tb IS
-- test bench
END pa_tb;
ARCHITECTURE behavior OF pa_tb IS
COMPONENT pa
PORT(fa,fb : IN std_logic_vector(3 downto 0);
fcin : IN std_logic;
fsum : OUT std_logic_vector(4 downto 0)
END COMPONENT;
signal fa,fb : std_logic_vector(3 downto 0) := (others => '0');
signal fcin : std_logic := '0';
signal fsum : std_logic_vector(4 downto 0);
BEGIN
uut: pa PORT MAP (fa,fb,fcin,fsum);
stim_proc: process
begin
fa<="0000" ; fb<="0000" ; fcin<='0'; wait for 20ns;

end process;
END;
Jk flip-flop
entity jk is
Port ( j,k,clk,rst : in STD_LOGIC;
q,qb : out STD_LOGIC);
end jk;
architecture Behavioral of jk is
signal state:std_logic;
begin
process (clk)
begin
if rst = '1' then state <='0';
elsif rising_edge(clk) then
case std_logic_vector'(j,k) is
when "11" => state<=not state;
when "10" => state<='1';
when "01" => state<='0';
when others => state<=state;
end case;
end if;
end process;
q<=state;
qb<=not state;
end Behavioral;
4-bit Ripple Carry Counter
module ripple_carry_counter(q, clk, reset); // main module of ripple carry counter

output [3:0] q;
input clk, reset;
T_FF tff0(q[0],clk, reset);
T_FF tff1(q[1],q[0], reset);
Endmodule
module T_FF(q, clk, reset); // T- flip flop

output q;
input clk, reset;
wire d;
D_FF dff0(q, d, clk, reset);
not n1(d, q);
Endmodule
module D_FF(q, d, clk, reset); // D- flip flop
output q;
input d, clk, reset;
reg q;
always @(posedge reset or negedge clk)
if (reset)
q <= 1'b0;
else
q <= d;
endmodule
module stimulus; // Test bench
reg clk;
reg reset;
wire[3:0] q;
ripple_carry_counter r1(q, clk, reset);
initial
clk = 1'b0; //set clk to 0
always
#5 clk = ~clk;
initial
begin
reset = 1'b1;
#15 reset = 1'b0;
#180 reset = 1'b1;
#10 reset = 1'b0;
#20 $finish; //terminate the simulation
end
initial
$monitor($time, " Output q = %d", q);
Endmodule
Four bit Full Adder (structural)

module FA(sum,cout,a,b,cin);// full adder
output sum,cout;
input a,b,cin;
wire s1,c1,c2;
xor x1(s1,a,b);
and a1(c1,a,b);
xor x2(sum,s1,cin);
and a2(c2,s1,cin);
or o1(cout,c2,c1);
endmodule
module FA_4(sum,cout,a,b,cin);// 4 bit full adder
output [3:0] sum;
output cout;
input [3:0] a,b;
input cin;
wire c1,c2,c3;
FA f1(sum[0],c1,a[0],b[0],cin);
FA f2(sum[1],c2,a[1],b[1],c1);
FA f3(sum[2],c3,a[2],b[2],c2);
FA f4(sum[3],cout,a[3],b[3],c3);
Endmodule
module PAtestbench;// test bench
reg [3:0] a,b;
reg cin;
wire [3:0]sum;
wire cout;
PA f1(sum,cout,a,b,cin);
initial
begin
a=4'b0000;b=4'b0000;cin=1'b0;
#20 a=4'b0000; b=4'b0000; cin=1'b0;
#20 a=4'b0001; b=4'b0001; cin=1'b0;
#20 a=4'b0010; b=4'b0010; cin=1'b0;
#20 a=4'b0011; b=4'b0011; cin=1'b0;
#20 a=4'b0100; b=4'b0100; cin=1'b0;
#20 a=4'b0101; b=4'b0101; cin=1'b0;
#20 a=4'b0110; b=4'b0110; cin=1'b0;

#20 a=4'b0111; b=4'b0111; cin=1'b0;
end
initial
$monitor($time," output sum=%b\n",sum);
Endmodule
Multiplexers
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
output out;
input i0, i1, i2, i3;
input s1, s0;
reg out;
always @(s1 or s0 or i0 or i1 or i2 or i3)
begin
case ({s1, s0})
2'b00: out = i0;
2'b01: out = i1;
2'b10: out = i2;
2'b11: out = i3;
default: out = 1'bx;
endcase
end
endmodule
4:1 mux using basic gates
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);

output out;
input s1, s0;
// four to 1 mux
wire s1n, s0n;

wire y0, y1, y2, y3;
not (s1n, s1);
not (s0n, s0);
and (y0, i0, s1n, s0n);
and (y1, i1, s1n, s0);
and (y2, i2, s1, s0n);
and (y3, i3, s1, s0);
or (out, y0, y1, y2, y3);
endmodule
module stimulus;
//test bench
reg IN0, IN1, IN2, IN3;
reg S1, S0;
wire OUTPUT;
mux4_to_1 mymux(OUTPUT, IN0, IN1, IN2, IN3, S1, S0);
initial
begin
IN0 = 1; IN1 = 0; IN2 = 1; IN3 = 0;
#1 $display("IN0= %b, IN1= %b, IN2= %b, IN3= %b\n",IN0,IN1,IN2,IN3);
S1 = 0; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
S1 = 0; S0 = 1;
S1 = 1; S0 = 0;
S1 = 1; S0 = 1;
end
endmodule
4:1 mux using conditional operator
module multiplexer4_to_1 (out, i0, i1, i2, i3, s1, s0);
output out;
input s1, s0;
assign out = s1 ? ( s0 ? i3 : i2) : (s0 ? i1 : i0) ;
endmodule
4-bit Full Adder with Carry Lookahead

module fulladd4(sum, c_out, a, b, c_in);
output [3:0] sum;
output c_out;
input [3:0] a,b;
input c_in;
wire p0,g0, p1,g1, p2,g2, p3,g3;
wire c4, c3, c2, c1;
assign p0 = a[0] ^ b[0],
p1 = a[1] ^ b[1],
p2 = a[2] ^ b[2],
p3 = a[3] ^ b[3];
assign g0 = a[0] & b[0],
g1 = a[1] & b[1],
g2 = a[2] & b[2],
g3 = a[3] & b[3];
assign c1 = g0 | (p0 & c_in),
c2 = g1 | (p1 & g0) | (p1 & p0 & c_in),
c3 = g2 | (p2 & g1) | (p2 & p1 & g0) | (p2 & p1 & p0 & c_in),
c4 = g3 | (p3 & g2) | (p3 & p2 & g1) | (p3 & p2 & p1 & g0) |
(p3 & p2 & p1 & p0 & c_in);
assign sum[0] = p0 ^ c_in,
sum[1] = p1 ^ c1,
sum[2] = p2 ^ c2,
sum[3] = p3 ^ c3;
assign c_out = c4;
endmodule
SR Latch
module SR_latch(Q, Qbar, Sbar, Rbar);
output Q, Qbar;
input Sbar, Rbar;
nand n1(Q, Sbar, Qbar);
nand n2(Qbar, Rbar, Q);
endmodule
module Top;
// test bench
wire q, qbar;
reg set, reset;
SR_latch m1(q, qbar, ~set, ~reset);
initial
begin
$monitor($time, " set = %b, reset= %b, q= %b\n",set,reset,q);
set = 0; reset = 0;
#5 reset = 1;
#5 reset = 0;
#5 set = 1;
end
endmodule
4-bit Counter
module counter(Q , clock, clear);
output [3:0] Q;
input clock, clear;
reg [3:0] Q;
always @( posedge clear or negedge clock)
begin
if (clear)
Q <= 4'd0;
else
Q <= Q + 1;
end
endmodule
8:3 Encoder
module verenc(en, din, dout);
input en;
input [7:0] din;
output [3:0] dout;
reg [2:0]dout;
always @ (en,din)
begin
if (en==1)
dout=3'b000;
else
begin
case(din)
8'b00000001:dout=3'b001;
8'b00000010:dout=3'b010;
8'b00000100:dout=3'b011;
8'b00001000:dout=3'b100;
8'b00010000:dout=3'b101;
8'b00100000:dout=3'b110;
8'b01000000:dout=3'b111;
8'b10000000:dout=3'b001;
endcase
end
endmodule
module testenc_v();
reg en;
reg [7:0] din;
// test bench
wire [2:0] dout;

verenc uut (
.en(en),
.din(din),
.dout(dout)
);
initial begin
en = 0;
din = 0;
#100;
en = 0;
din = 8'b00000001;
#10;
en = 0;
din = 8'b00000010;
#10;
en = 0;
din = 8'b00000100;
#10;
en = 0;
din = 8'b00001000;
#10;
en = 0;
din = 8'b00010000;
#10;
end
endmodule
library ieee;
use ieee.std_logic_1164.all;
entity fastrer is
port( x,y,z:in std_logic;
sum,carry:out std_logic);
end fastrer;
architecture a_arch of fastrer is
component ha is
port( a,b:in std_logic;
s,c:out std_logic);
end component;
component aa is
port( s,l:in std_logic;
g:out std_logic);
end component;
signal t1,t2,t3:std_logic;
begin
u1:ha port map(x,y,t1,t2);
u2:ha port map(t1,z,sum,t3);
u3:aa port map(t2,t3,carry);
end a_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity srsm is
Port ( s,r,clk,rst : in STD_LOGIC;
z: out STD_LOGIC);
end srsm;
architecture Behavioral of srsm is
type state_type is (s0,s1);
signal state:state_type;
begin
process(s,r,clk,rst)
begin
if rst='1' then state<=s0;
elsif clk'event and clk='1'then
case state is
when s0=>if s='0' and r='0' then state<=s0;end
if s='0' and r='1' then state<=s0;end
when s1=>if s='0' and r='0' then state<=s1;end
end case;
end if;
end process;
process(state)
begin
case state is
when s0=>z<='0';
when s1=>z<='1';
end case;
end process;
end Behavioral;
library IEEE;
entity srsmtest is
end srsmtest;
architecture Behavioral of srsmtest is
signal s,r,clk,rst,z,state:std_logic;
component srsm
Port ( s,r,clk,rst: in STD_LOGIC;
z: out STD_LOGIC);
end component;
begin
u1:srsm port map(s,r,clk,rst,z);
process
begin
rst<='1'; wait for 10 ns;
rst<='0'; wait for 40 ns;
end process;
process
begin
clk<='0'; wait for 10 ns;
end process;
process
begin
if;
if;
if;
if;
if;
if;
s<='0';r<='0'; wait for 20 ns;

s<='0';r<='1'; wait for 20 ns;
s<='1';r<='0'; wait for 20 ns;
end process;
end Behavioral;
library IEEE;
entity tff is
Port ( t,clk,rst:in STD_LOGIC;
q,qb:out STD_LOGIC);
end tff;
architecture tff_arch of tff is
begin
process(clk,rst,t)
begin
if rst='1' then state<='0';
elsif clk'event and clk='1' then
if t='1' then state <= not state;
else state <= state;
end if;
end if;
end process;
q <= state;
qb <= not state;
end tff_arch;
library IEEE;
entity tfftest is
end tfftest;
architecture tfftest_arch of tfftest is
component tff
Port ( t,clk,rst:in STD_LOGIC;
end component;
signal t,clk,rst,q,qb:std_logic;
begin
u1:tff port map(t,clk,rst,q,qb);
process
begin
end process;
process
begin
t<='0';wait for 50 ns;
t<='1';wait for 50 ns;
end process;
process
begin
rst<='1';wait for 5 ns;
rst<='0';wait for 100 ns;
end process;
end tfftest_arch;
--Example of a state machine--Sequence Detector detecting "110"
--Model3-Binary encoding of states
--Example of a state machine--Sequence Detector detecting "110"
--Model3-Binary encoding of states
library IEEE;
entity seqdet3 is
port(a,clk,rst:in std_logic;
b:out std_logic);
end seqdet3;
architecture seqdet3_arch of seqdet3 is
type state_type is array(1 downto 0) of bit;
constant s0:state_type:="00";
signal ps,nxs: state_type;
begin
process(clk,rst)
begin
if rst='1' then
ps<= s0;
ps<=nxs;
end if;
end process;
process(ps)
begin
case ps is
when s0=> if a='0' then
nxs<=s0;
else nxs<=s1;
end if;
nxs<=s0;
else nxs<=s2;
end if;
nxs<=s3;
else nxs<=s2;
end if;
nxs<=s0;
else nxs<=s1;
end if;
end case;
end process;
process (ps)
begin
case ps is
when s0 => b
when s1 => b
when s2 => b
when s3 => b
end case;
end process;
<='0';
<='0';
<='0';
<='1';
end seqdet3_arch;
--Model2----One-hot encoding
library IEEE;
entity seqdetector is
port(a,clk,rst:in std_logic;
b:out std_logic);
end seqdetector;
architecture seqdetector_arch of seqdetector is
type states is (s0,s1,s2,s3);
signal ps,nxs: states;
begin
process(clk,rst)
begin
if rst='1' then
ps<=s0;
ps<=nxs;
end if;
---end if;
end process;
process(ps)
begin
case ps is
nxs<=s0;
else nxs<=s1;
end if;
nxs<=s0;
else nxs<=s2;
end if;
nxs<=s3;
else nxs<=s2;
end if;
nxs<=s0;
else nxs<=s1;
end if;
end case;
end process;
process (ps)
begin
case ps is
when s0 => b <='0';
when s1 => b <='0';
when s2 => b <='0';
when s3 => b <='1';
end case;
end process;
end seqdetector_arch;
library IEEE;
use IEEE.std_logic_1164.all;
entity paralleladder is
port (a,b: in std_logic_vector(3 downto 0);
cin: in std_logic;
s: out std_logic_vector(3 downto 0);
cout:out std_logic);
end paralleladder;
architecture paralleladder_arch of paralleladder is
component fulladder
port (x,y,z: in std_logic;
sum,carry: out std_logic);
end component;
signal c:std_logic_vector(3 downto 1);
begin
u1:fulladder port map(a(0),b(0),cin,s(0),c(1));
u2:fulladder port map(a(1),b(1),c(1),s(1),c(2));
u3:fulladder port map(a(2),b(2),c(2),s(2),c(3));
u4:fulladder port map(a(3),b(3),c(3),s(3),cout);
end paralleladder_arch;
library IEEE;
entity paralleladdertest is
end paralleladdertest;
architecture paralleladdertest_arch of paralleladdertest is
component paralleladder
cin: in std_logic;
end component;
signal a,b:std_logic_vector(3 downto 0);
signal cin:std_logic;
signal s:std_logic_vector(3 downto 0);

signal cout:std_logic;
begin
u1:paralleladder port map(a,b,cin,s,cout);
process
begin
a<="0000";b<="0000";cin<='0';wait for 10 ns;
a<="0001";b<="0001";cin<='0';wait for 10 ns;
a<="0010";b<="0010";cin<='0';wait for 10 ns;
a<="0011";b<="0011";cin<='0';wait for 10 ns;
a<="0100";b<="0100";cin<='0';wait for 10 ns;
a<="0101";b<="0101";cin<='0';wait for 10 ns;
a<="0110";b<="0110";cin<='1';wait for 10 ns;
a<="0111";b<="0111";cin<='0';wait for 10 ns;
a<="1000";b<="1000";cin<='0';wait for 10 ns;
a<="1001";b<="1001";cin<='1';wait for 10 ns;
a<="1010";b<="1010";cin<='0';wait for 10 ns;
a<="1011";b<="1011";cin<='0';wait for 10 ns;
a<="1100";b<="1100";cin<='1';wait for 10 ns;
a<="1101";b<="1101";cin<='0';wait for 10 ns;
a<="1110";b<="1110";cin<='0';wait for 10 ns;
a<="1111";b<="1111";cin<='1';wait for 10 ns;
end process;
end paralleladdertest_arch;
library IEEE;
entity paralleladdertest is
end paralleladdertest;
architecture paralleladdertest_arch of paralleladdertest is
component paralleladder
cin: in std_logic;
end component;
signal a,b:std_logic_vector(3 downto 0);
signal cin:std_logic;
signal s:std_logic_vector(3 downto 0);
signal cout:std_logic;
begin
u1:paralleladder port map(a,b,cin,s,cout);
process
begin
a<="0000";b<="0000";cin<='0';wait for 10 ns;
a<="0001";b<="0001";cin<='0';wait for 10 ns;
a<="0010";b<="0010";cin<='0';wait for 10 ns;
a<="0011";b<="0011";cin<='0';wait for 10 ns;
a<="0100";b<="0100";cin<='0';wait for 10 ns;
a<="0101";b<="0101";cin<='0';wait for 10 ns;
a<="0110";b<="0110";cin<='1';wait for 10 ns;
a<="0111";b<="0111";cin<='0';wait for 10 ns;
a<="1000";b<="1000";cin<='0';wait for 10 ns;
a<="1001";b<="1001";cin<='1';wait for 10 ns;
a<="1010";b<="1010";cin<='0';wait
a<="1011";b<="1011";cin<='0';wait
a<="1100";b<="1100";cin<='1';wait
a<="1101";b<="1101";cin<='0';wait
a<="1110";b<="1110";cin<='0';wait
a<="1111";b<="1111";cin<='1';wait
for
for
for
for
for
for
10
10
10
10
10
10
ns;
ns;
ns;
ns;
ns;
ns;
end process;
end paralleladdertest_arch;
library IEEE;
entity jkff is
Port ( j,k,clk,rst:in STD_LOGIC;
end jkff;
architecture jkff_arch of jkff is
begin
process(clk,rst,j,k)
begin
if rst='1' then state<='0';
case std_logic_vector'(j,k) is
when "11" =>state <= not state;
when "10" =>state <= '1';
when "01" =>state <= '0';
when others=>null;
end case;
end if;
end process;
q <= state;
qb <= not state;
end jkff_arch;
library IEEE;
entity alu1 is
Port (A,B,opcode:in STD_LOGIC_vector(3 downto 0);
en:in STD_LOGIC;
F:out STD_LOGIC_vector(7 downto 0));
end alu1;
architecture beh of alu1 is
begin
process(A,B,en,opcode)
begin
if en='0' then F<="ZZZZZZZZ";
else
case opcode is
when "0000"=>F(4 downto 0)<='0'&A+B;
F(7 downto 5)<=(others=>'0');
when "0001"=>F(3 downto 0)<=A-B;
F(7 downto 4)<=(others=>'0');
when "0010"=>F<=A*B;
when "0011"=>F(3 downto
F(7 downto
F(7 downto
F(7 downto
F(7 downto
F(7 downto
F(7 downto
F(7 downto
F(7 downto
when others=>F(7 downto
end case;
end if;
end process;
end beh;
0)<=not A;
4)<=(others=>'0');
0)<=not B;
4)<=(others=>'0');
0)<=A and B;
4)<=(others=>'0');
0)<=A or B;
4)<=(others=>'0');
0)<=A nand B;
4)<=(others=>'0');
0)<=A nor B;
4)<=(others=>'0');
0)<=A xor B;
4)<=(others=>'0');
0)<=not(A xor B);
4)<=(others=>'0');
0)<=(others=>'X');

DSD Programs VHDL Verilog

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DSD Programs VHDL Verilog

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DIGITAL SYSTEM DESIGN

Full Adder ( using 2 half adders)

a <='0';b<='0';c<='1'; wait for 10ns;

fa<="0001" ; fb<="0110" ; fcin<='0'; wait for 20ns;

4-bit Ripple Carry Counter

module ripple_carry_counter(q, clk, reset); // main module of ripple carry counter

module T_FF(q, clk, reset); // T- flip flop

Four bit Full Adder (structural)

#20 a=4'b0110; b=4'b0110; cin=1'b0;

module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);

wire s1n, s0n;

4-bit Full Adder with Carry Lookahead

wire [2:0] dout;

s<='0';r<='0'; wait for 20 ns;

signal s:std_logic_vector(3 downto 0);

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