Carbon Nanotubes for VLSI: Interconnect and Transistor Applications

Y. Awano1,2), S. Sato2,3), M. Nihei2,3), T. Sakai2,4), Y. Ohno5) and T. Mizutani5) 1) Keio University, 2)MIRAI-Selete, 3)Fujitsu Laboratories Ltd., 4) Toshiba Corp., 5) Nagoya University

ABSTRACT
We report the present status of Carbon Nanotube (CNT) CVD material technologies and their applications for via interconnects and FETs for VLSI. We succeeded in growing multi-walled CNTs (MWNTs) with the highest shell density (as high as 1013/cm2) and in fabricating via interconnects with high robustness against a high current density. We also report a Si-process compatible technique to control carrier polarity of Single-walled CNT (SWNT) FETs by utilizing fixed charges introduced by the gate oxide. Highperformance p- and n-type CNT-FETs and CMOS inverters with stability in air have been realized..

INTRODUCTION
A carbon nanotube (CNT), which is made by rolling up a sheet of graphite or graphene into a cylinder, exhibits not only unique atomic arrangements but also interesting physical properties, including current carrying ability, long ballistic transport length, high thermal conductivity, and high mechanical strength [1]. These remarkable properties make CNTs one of the most important Emerging Research Materials (ERM) for both back-end and front-end Emerging Research Devices (ERDs) of LSIs for the next decade. In 2008, ERM and ERD working groups of International Technology Roadmap for Semiconductors (ITRS) recommended carbon-based nanoelectronics as promising Beyond CMOS technologies with targeting of commercial demonstration in the 5-10 year horizon [2]. Their advantages are not only they can provide a technology platform enabling a new Beyond CMOS information processing paradigm, such as spintronics, but also they potentially can have an impact on scaled CMOS device and circuits by providing an alternate FET channel and an alternate metal wiring. Both MWNTs and SWNTs are potentially viable candidates for LSI interconnects, while both SWNTs and double-walled CNTs (DWNTs) are potentially viable candidates for CMOS channels [3]. We already reported selective synthesis of SWNTs, DWNTs and MWNTs from sizecontrolled catalytic nano-particles by adjusting the dilution ratio of source gas for low-temperature CVD [4]. CNTs are also expected as management candidates for assembly and package applications to enable reliable electrical and thermal interconnects [5]. The timeframe of assembly and package applications seems to be earlier than those of interconnect and FET applications. In this paper, we discuss CNT technologies for future LSIs, in particular, CNT via interconnects and CNT-FETs [3].

process of CNT vias. We report the deposition of size-controlled catalyst nanoparticles using a custom-designed particle deposition system, low temperature growth of MWNTs (510 -365) using such catalyst nanoparticles [6]. By optimizing catalyst and thermal CVD conditions, we successfully obtained a site density of 1.4 x1012cm-2 at 450 [7]. High-density CNT growth can also be obtained by plasma CVD. By optimizing plasma pretreatments of catalytic metal thin layer, the density reaches 2 x1012cm-2[8], which means a shell (or wall) density of 1013cm-2. We proposed a single damascene process to integrate CNT vias with Cu interconnects [9], which is mostly compatible with conventional Cu interconnects. We measured the electrical properties of CNT via with a CNT density of 3x1011 cm-2 and demonstrated the high electromigration tolerance of 4x107A/cm2 per via, i.e., 1.7x108A/cm2 per CNT [10].

CNT FETS FOR FUTURE CMOS CIRCUITS:

FABRICATION AND CONTROL OF CONDUCTION PROPERTY
The s-SWNTs are promising candidate for the channel material of CMOS devices because of their two advantages over the other semiconductor materials: the high carrier mobility P and 1-D thin body. The reported P of s-SWNTs are larger than those of graphene nanoribbons with almost the same band gap energy [11]. The second advantage of s-SWNTs, the ultra-thin 1-D structure, can suppress the short channel effect (SCE) in ultra-short channel devices in terms of electrostatics. Since the source and drain contacts of a CNT-FET consist of metalsemiconductor junctions, the CNFET can be considered as a type of SB FETs. For CMOS applications, the control of the conduction property of CNFETs is an important issue, especially, regarding stability in air, device performance, and process compatibility to Si LSIs. We introduce a new technique to control carrier polarity of CNT-FETs by utilizing fixed charges introduced at the interface between the gate insulator and substrate [12]. We report electrical characteristics of fabricated top-gate CNT-FETs in air at room temperature. The conduction types of the HfO2-gate and Al2O3gate CNT-FETs were n-type and p-type FETs, respectively [12]. We reported the CMOS inverters using a single SWNT with a maximum voltage gain of 26 and good air stability [13].

REFERENCES
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] R. Saito, et al., Physical Properties of Carbon Nanotubes. London, U.K.: Imperial College Press, Apr., 2000. J. Hutchby, ITRS-ERD, http://www.itrs.net/Links/ 2008Summer/ Presentations.html. Y. Awano, et al., Proc. of the IEEE, 98, 12, pp.2016 (2010) D. Kondo, et al., Nanotechnology, vol. 19, 435601 (2008). For example, I. Soga, et al., IEEE ISRFT, pp. 221 (2009) S. Sato, et al., IEEE IITC, pp. 230.232 (2006) A. Kawabata, et al., Nanotube 2010, 283.(2010) Y. Yamazaki. et al., Diamond 2010, O20 (2010) M. Nihei, et al., SSDM 2006 , pp. 140 (2006) M. Sato, et al., JJAP, 49, 10, pp. 105102 (2010). A. Betti, et al. IEEE IEDM 2010, 728 (2010) N. Moriyama, et al., Nanotechnology, 21,165201 (2010) N. Moriyama, et al. Appl. Phys. Exp. 3, 105102 (2010)

CNT VIA INTERCONNECTS:

FABRICATION AND ELECTRICAL PROPERTIES
A continuing shrinkage in the dimensions of LSIs is causing increase in the current density of the Cu interconnects, which leads to electromigration problem, and also increase in the resistivity of the interconnects, which is due to the width dependent scatterings (grain boundary and sidewall scatterings). CNTs are one of the promising candidate technologies to solve these issues because of their excellent properties. In order to realize the CNT interconnects, however, there are several issues to be addressed, for example, a high density and low temperature CVD process, a novel fabrication

978-1-4244-8492-8/11/$26.00 2011 IEEE

Acknowledgements: The work on via interconnects was mainly completed

as part of the MIRAI Project supported by NEDO. The work on FETs was supported in part by the Promotion of Science and Strategic Information and Communications R&D Promotion Programme of MIC, Industrial Technology Research Grant Program in 2008 from NEDO, Grant-in-Aid for Scientific Research on Priority Areas of MEXT, and Development of Nanoelectronic logy of NEDO. Device Technology

( 2010 IEEE ( 2010 IEEE

Fig. 1

hematic view of CNT via interconnects i terconnects in Schematic

Fig. 6 Carrier mobilities semiconductors vs. band gap

of

s-SWNTs

and

conventional

( 2010 IEEE ( 2010 IEEE

Fig. 7

Schematic structure of CNFET

Figs. 2 A SEM images of high-density MWNTs grown at 450 by (a) thermal hermal CVD [7] and (b) plasma CVD [8]

* *

( 2010 IEEE

Figs. 8 Model of abrupt energy band bending near source contact caused by positive fixed charges introduced at interface between HfO2 and SiO2 [3]

Fig. 3 CNT via processes (Single damascene) [9]

Normarized resistance
1.5 5.010 A/cm 1.0 Sub. Temp. 105C C in vaccum vacuum
6 2

100hrs

Cu

CNT/SOG via
SiOC(k=2.6)

0.5

Cu

100nm

0 0

20 40 60 80 100 120

Figs. 4 TEM image of CNT via and the robustness against a high current density

slit void

( 2010 IEEE

Figs. 5 Cross-sectional TEM image of CNT via after the reliability test of 5x106A/cm2 per via at 250 [10]

Figs. 9 (a) IDVDS and (b) IDVGS characteristics of n-type topgate CNFET with HfO2 gate insulator. (c) IDVDS and (d) IDVGS characteristics of p-type top-gate CNFET with Al2O3 gate insulator. [3]