Beruflich Dokumente
Kultur Dokumente
Ashish Bhatia(Y5827121)
Anuragg Sindhu(Y5106)
(
)
Theory
Preprocessing
Pre processing
Generate(pi,gi)from(Ai,Bi)
pi =A
= Ai xor Bi
gi =Ai and Bi
Theory
Carrylookaheadnetwork
Carry look ahead network
Generate(Pij,Gij)from(Gi,Pi)and(Gj,Pj)
Pi:j =P
= Pi:k+1 andP
and Pk:j
Gi:j =Gi:k+1 or(Pi:k+1and Gk:j )
Theory
Postprocessing
Post processing
Sumi =pi xor Carryi1
Ci =G
= Gi:0or(C
or (Cin and Pi:0)
Ill
Illustration
i
B3=1A3=1
B2=1A2=0
B1=0A1=1
B0=0A0=1
g3=1p
p3=0
g2=0p
p2=1
g1=0p
p1=1
g0=0p
p0=1
Pre processing
Preprocessing
pi =Ai xor Bi
gi =Ai and
d Bi
Cin=0
B3=1A3=1
B2=1A2=0
B1=0A1=1
B0=0A0=1
g3=1p
p3=0
g2=0p
p2=1
g1=0p
p1=1
g0=0p
p0=1
G3:2=1
P3:2=0
G2:1=0
P2:1=1
G1:0=0
P1:0=1
Cin=0
G0=C0=0
B3=1A3=1
B2=1A2=0
B1=0A1=1
B0=0A0=1
g3=1p
p3=0
g2=0p
p2=1
g1=0p
p1=1
g0=0p
p0=1
G3:2=1
P3:2=0
G2:1=0
P2:1=1
G1:0=0
P1:0=1
G2 =C2=0
G1 =C1=0
G3:0=1
P3:0
3:0 =0
Cin=0
G0=C0=0
B3=1A3=1
B2=1A2=0
B1=0A1=1
B0=0A0=1
g3=1p
p3=0
g2=0p
p2=1
g1=0p
p1=1
g0=0p
p0=1
G3:2=1
P3:2=0
G2:1=0
P2:1=1
G1:0=0
P1:0=1
G2 =C2=0
G1 =C1=0
G3:0=1
P3:0
3:0 =0
G3 =C3=1
Cin=0
G0=C0=0
Cin=0
p3=0
p2=1
p1=1
p0=1
Postprocessing
G0=C0=0
Si =pi xorCi1
G2 =C2=0
G1 =C1=0
S3=0
S2=1
G3 =C3=1
Cout
out =1
S1=1
S0=1
B3=1A3=1
B2=1A2=0
B1=0A1=1
B0=0A0=1
g3=1p
p3=0
g2=0p
p2=1
g1=0p
p1=1
g0=0p
p0=1
G3:2=1
P3:2=0
G2:1=0
P2:1=1
G1:0=0
P1:0=1
G0=C0=0
Cin=0
A=1011
B=1100
Cin =0
SS=0111
0111
Ccout =1
G3:0=1
P3:0
3:0 =0
G2 =C2=0
G1 =C1=0
G3 =C3=1
Cout
out =1
S3=0
S2=1
S1=1
S0=1
Specifications
Maxfrequency
Max frequency =374.94MHz
374.94 MHz
Area=440mX300m=0.132mm^2
Power = 460 uW
Power=460uW
Power Consumption
PowerConsumption
Avg Power=(1.224*10^12)*fmax =
0 46 mW
0.46mW
Implementation Details
ImplementationDetails
Designedschematicof8bitKSA(Fulladder)
es g ed sc e at c o 8 b t S ( u adde )
Technology=AMS0.35m(4metallayer)
518MOSFETs(=259CMOS)
CadenceVirtuosoSchematicEditor
Spectre (simulator)
Designedcompletelayout
CadenceVirtuosoLayoutEditor
SuccessfulDRCandLVStoverifydesign
f l
d
if d i
Synthesis XilinxSpartan3FPGA
Schematic
Layout
DRC Report
DRCReport
LVS Report
LVSReport
Synthesis Report
SynthesisReport
Advantages
High
HighSpeed
Speed
LowandregularFanout
Regularstructure
l
easymappingtoFPGA
i
G
fabric
Main Challenges
MainChallenges
LayoutDesign
Layout Design
DRCconstraints
LVSconstraints
S
i
Conclusion
We
Wedesignedandimplemented8bitKogge
designed and implemented 8 bit Kogge
StoneTreeAdderthatoperatesat375
MHz(fmax)andcompletelayouttakesanarea
) and complete layout takes an area
of440X300um^2
24
References
Swaroop
SwaroopGhosh,PatrickNdai,KaushikRoy.
Ghosh Patrick Ndai Kaushik Roy "A
A
NovelLowOverheadFaultTolerantKogge
Stone Adder Using Adaptive Clocking".DATE
StoneAdderUsingAdaptiveClocking
DATE
2008.
J.Rabaey,
J Rabaey "Digital
DigitalIntegratedCircuits:ADesign
Integrated Circuits: A Design
Perspective",PrenticeHall,1996.