Central Processing Unit (Cpu)

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CENTRAL PROCESSING UNIT (CPU)

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The solution algorithm consists of series of steps These steps are broken into smaller steps 1 steps = 1 machine instruction Each instruction is executed by carrying out a sequence of rudimentary/basic operations These operations anda how they are generated is one of the main topic of this course
FUNDAMENTAL CONCEPT
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The instructions are loaded in the sequential locations in main memory Instructions are fetch from successive memory locations PC (program counter) keeps track address of the next memory location containing next instruction (PC= PC +1)
THREE STEPS OF EXECUTION 1 INSTRUCTION

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1. Fetch the contents of memory location pointed by PC, then loaded into IR (instruction register) IR [[ PC ]] 2 . Increment PC : PC PC +1 3 . Carry out the action by the instruction in the IR If the instruction more the 1 word, step 1 and 2 must be repeated as necessary
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SINGLE BUS ORGANIZATION
OPERATION FUNCTIONS
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Fetch content of memory location and load into a CPU register (M R) Store data from CPU register into memory location (R M) Transfer from 1 register to another register (R R) Perform arithmetic & logic operation and store the result in CPU register How each function is implemented in detail ?
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Fetching a word from Memory

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Specify the address of memory location containing the instruction or operand, sent from CPU MAR memory CPU send Read control signal After completing the operation, memory send the WMFC (wait for Memory Function Completed) signal to CPU, it means instruction/operand (requested) is available in the MDR
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Sequence of Read operation

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Assumed memory address is in R1 and data from memory to be loaded into R2 1. MAR [R1] 2. Read 3. Wait for MFC signal 4. R2 [MDR] This type of data transfer is asynchronous transfer (combination of read request and MFC signal)
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Storing a Word in Memory

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Address is loaded into MAR Data (to be written) is loaded into MDR Write signal is issued After completion of the operation, the memory will send the MFC signal
Sequence of Write operation

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Assumed data to be stored is in R2 and memory address is in R1 1. MAR [R1] 2. MDR [R2], Write 3. Wait for MFC
Register Transfer
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To control the gate for input the data into Ri is used control signal Ri in To control the gate for output the data to the bus is used control signal Ri out To transfer contents of R1 to R4 : R1 out is set to 1 output to the bus R4 in is set to 1 load from the bus into R4
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Arithmetic & Logic operation

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To add two numbers :

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First operand is hold on register Y Second operand is gated into the bus
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The result is store temporarily in reg Z Example : Add the contents of R1 to R2 and store the result in R3
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Signal control to ADD 2 numbers

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Step Action 1. R1out, Yin 2. R2out, Add, Zin 3. Zout, R3in The signal whose name are given, is set to 1 All other signals are inactive
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Execution a Complete Instruction

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The actions : 1. Fetch the instruction 2. Executions :

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Fetch operand(s) Perform the operations (Move, Add, etc.) Store the result to register or memory
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Sequence control for instruction ADD LOC, R1

1.
2. 3. 4. 5. 6. 7.
Pcout, MARin, Read, Clear Y, Set_carry_in_to ALU, Add, Zin Zout, PCin, Wait_for_MFC MDRout, IRin Address_field_of_IRout, MARin, Read R1out, Yin, Wait_for_MFC MDRout, Add, Zin Zout, R1in, End.
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DOUBLE BUS ORGANIZATION (1)
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Register output connect to bus A, register input connect to bus B Two buses connected through bus tie G, normally open, to close use control signal Genable When bus tie G disable, two buses disconnected Do not need register Z, because output from reg Z can be placed on bus B, no possible conflict with the data on bus A
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Ex : the operation R3 <- [R1] + [R2] can be perform as follows : 1. R1out, Genable, Yin 2. R2out, Add, ALUout, R3in The operation R2 <- [R1] + [R2] can be perform as follows : 1. R2out, Genable, Yin 2. R1out, Add, ALUout, R2in
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Branching
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Branching : replacing contents of PC by branch address Branch address = update PC + offset X Offset X is given in the address field of the branch instruction 2 type of branching :
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Unconditional Conditional
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Sequence control : Branch Unconditional

1.
2. 3. 4. 5. 6.
Pcout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin Zout, PCin, Wait_for_MFC MDRout, IRin PCout, Yin Address_field_of_IRout, ADD, Zin Zout, PCin, End.
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CONDITION CODE
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Condition code flag is represent by a bit in the status register of the processor, to know the result of the last computing operation , there are : N (negative) : set to 1 if the result is negative, otherwise is 0 Z (zero) : set to 1 if the result is 0, otherwise is 0 V (overflow) : set to 1 of overflow occurs C (carry) : set to 1 if there are carry out result
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STATUS REGISTER
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Conditional Brach : Branch on Negative

Pcout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin Zout, PCin, Wait_for_MFC 2. 3. MDRout, IRin PCout, Yin, If N then End. 4. Address_field_of_IRout, ADD, Zin 5. 6. Zout, PCin, End. Step 4 : N is cheked, if N= 0 then End, if N=1, do step 5 and 6
1.
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Generating control signal to execute instructions

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2 categories : A) Hardwired B) Microprogrammed Control
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Hardwired Control
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The main part are decoder/encoder, simpy a combinational circuit to generate signal control, depending on the state of all its input :
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Contents of control counter contents of instruction register Contents of condition code and other status flags
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Hardwired Control
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Hardwired (cont.)
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For any instruction loaded into IR, one of the output lines INS1 to INSm is set to 1 All input signal to encoder block will be combined to generate individual control signal as Yin, PCout etc.
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Encoder
Zin = T1 + T6.ADD + T5.BR + ..
End = T7.ADD + T6.BR + (T6.N + T4.N).BRN + ..
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Microprogrammed Control
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Control signal are generated by a program similar to machine language program Each control signal is represent by individual bit stored in programmed memory/control store Control unit generate control signal by reading sequentially control word from control store using PC
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Basic Organization of Microprogrammed Control Unit
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Example of Microinstruction in programmed memory
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Central Processing Unit (Cpu)

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Central Processing Unit (Cpu)

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Generated by Foxit PDF Creator Foxit Software http://www.foxitsoftware.com For evaluation only.

CENTRAL PROCESSING UNIT (CPU)

THREE STEPS OF EXECUTION 1 INSTRUCTION

SINGLE BUS ORGANIZATION

Fetching a word from Memory

Sequence of Read operation

Storing a Word in Memory

Sequence of Write operation

Arithmetic & Logic operation

To add two numbers :

Signal control to ADD 2 numbers

Execution a Complete Instruction

The actions : 1. Fetch the instruction 2. Executions :

Sequence control for instruction ADD LOC, R1

DOUBLE BUS ORGANIZATION (1)

DOUBLE BUS ORGANIZATION (2)

DOUBLE BUS ORGANIZATION (3)

Sequence control : Branch Unconditional

Conditional Brach : Branch on Negative

Generating control signal to execute instructions

2 categories : A) Hardwired B) Microprogrammed Control

Zin = T1 + T6.ADD + T5.BR + ..

End = T7.ADD + T6.BR + (T6.N + T4.N).BRN + ..

Basic Organization of Microprogrammed Control Unit

Example of Microinstruction in programmed memory

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