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Adder library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.

all; entity adder8bit is port ( number1, number2 :in std_logic_vector(7 downto 0); result : out std_logic_vector(7 downto 0) ); end adder8bit; architecture a_adder8bit of adder8bit is begin result<=number1 + number2; end a_adder8bit; And3inputs library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity and3inputs is port ( din1, din2, din3: in std_logic_vector(7 downto 0); dout: out std_logic_vector(7 downto 0) ); end and3inputs; architecture a_and3inputs of and3inputs is begin dout<= din1 and din2 and din3; end a_and3inputs; Arithmetic library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity arithmetic4 is port ( nummer1, nummer2: in std_logic_vector(7 downto 0); mode: in std_logic_vector(1 downto 0); result: out std_logic_vector(7 downto 0) ); end arithmetic4; architecture a_arithmetic4 of arithmetic4 is begin programm: process(nummer1, nummer2, mode) begin case mode is when "00" => result<=nummer1 + nummer2; when "01" => result<=nummer1 - nummer2;

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when "10" => result<=nummer1 and nummer2; when "11" => result<=nummer1 or nummer2; when others => null; end case; end process; end a_arithmetic4; BCD Counter up-down library ieee; use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; entity bcd_counter_updown is port ( clk,reset,cntup, cntdown: in std_logic; ovf, ovr: out std_logic; bcdout: out std_logic_vector(3 downto 0) ); end bcd_counter_updown; architecture abcd_counter_updown of bcd_counter_updown is signal ccnt: std_logic_vector(3 downto 0); begin process(clk,reset) begin if reset='1' then ccnt<="0000"; elsif (rising_edge(clk)) and (cntup='1') then if ccnt="1001" then ccnt<="0000"; ovf<='1'; else ccnt<=ccnt+1; ovf<='0'; end if; elsif (rising_edge(clk)) and (cntdown='1') then if ccnt="0000" then ccnt<="1001"; ovr<='1'; else ccnt<=ccnt-1; ovr<='0'; end if; end if; end process; bcdout<=ccnt; end abcd_counter_updown; BCD counter library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity bcdcounter is port ( clk: in std_logic; mode: in std_logic;

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bcd_counter: out std_logic_vector(3 downto 0); ovf: out std_logic ); end bcdcounter; architecture a_bcdcounter of bcdcounter is signal icounter: std_logic_vector(3 downto 0); begin process(clk, mode) begin if rising_edge(clk) and (mode='1') then if (icounter="1001") then icounter <= "0000"; ovf <= '1'; else icounter <= icounter+1; ovf <= '0'; end if; end if; end process; bcd_counter <= icounter; end a_bcdcounter; Countdown library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity countdown is port ( clk: in std_logic; mode: in std_logic; output: out std_logic_vector(2 downto 0) ); end countdown; architecture a_countdown of countdown is signal icounter: std_logic_vector(2 downto 0); begin process(clk, mode) begin if rising_edge(clk) then if (mode='1') then icounter <= icounter-1; else icounter <= icounter; end if; end if; end process; output <= icounter; end a_countdown; Counter4modes library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity counter4mode is port (

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clk: in std_logic; mode: in std_logic_vector(1 downto 0); load: in std_logic_vector(2 downto 0); ovf, ovr: out std_logic; output: out std_logic_vector(2 downto 0) ); end counter4mode; architecture a_counter4mode of counter4mode is signal icounter: std_logic_vector(2 downto 0); begin process(clk, mode) begin if rising_edge(clk) then if (mode="01") then if (icounter="111") then icounter <= "000"; ovf <= '1'; else icounter <= icounter+1; ovf <= '0'; end if; elsif (mode="10") then if (icounter="000") then icounter <= "111"; ovr <= '1'; else icounter <= icounter-1; ovr <= '0'; end if; elsif (mode="11") then icounter <= load; else icounter <= icounter; end if; end if; end process; output <= icounter; end a_counter4mode; Count Up library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity countup is port ( clk: in std_logic; mode: in std_logic; output: out std_logic_vector(7 downto 0) ); end countup; architecture a_countup of countup is signal icounter: std_logic_vector(7 downto 0); begin process(clk, mode) begin if rising_edge(clk) then if (mode='1') then icounter <= icounter+1; else icounter <= icounter; end if; end if;

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end process; output <= icounter; end a_countup; Count up-down library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity countupdown is port ( clk: in std_logic; mode: in std_logic_vector(1 downto 0); output: out std_logic_vector(2 downto 0) ); end countupdown; architecture a_countupdown of countupdown is signal icounter: std_logic_vector(2 downto 0); begin process(clk,mode) begin if rising_edge(clk) then if (mode="01") then icounter <= icounter+1; elsif (mode="10") then icounter <= icounter-1; else icounter <= icounter; end if; end if; end process; output <= icounter; end a_countupdown; 7segment decoder library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity decoder_7segment is port ( bcdin: in std_logic_vector(3 downto 0); segmentout: out std_logic_vector(6 downto 0) ); end decoder_7segment; architecture adecoder_7segment of decoder_7segment is begin with bcdin select segmentout<= "1000000" when "0000", "1111001" when "0001", "0100100" when "0010", "0110000" when "0011", "0011001" when "0100", "0010010" when "0101", "0000010" when "0110", "1111000" when "0111", "0000000" when "1000", "0010000" when "1001", "0001000" when "1010", "0000011" when "1011",

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"1000110" when "1100", "0100001" when "1101", "0000110" when "1110", "0001110" when "1111", "1111111" when others; end adecoder_7segment; 1Hz Generator use ieee.std_logic_1164.all; library ieee; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity gen1hz is port ( sys_clk: in std_logic; out_clk: out std_logic ); end gen1hz; architecture a_gen1hz of gen1hz is signal clk_1hz: std_logic; begin process(sys_clk) variable ccnt: integer range 0 to 25000000; begin if rising_edge(sys_clk) then if ccnt=0 then ccnt:=24999999; clk_1hz <= not clk_1hz; else ccnt:=ccnt-1; end if; end if; end process; out_clk <= clk_1hz; end a_gen1hz; Johnson counter library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity Johnsoncounter is generic(n : NATURAL :=6); port ( clk: in std_logic; reset: in std_logic; countout: out std_logic_vector(n-1 downto 0) ); end Johnsoncounter; architecture aJohnsoncounter of Johnsoncounter is begin process(clk, reset) is variable cv: std_logic_vector(n-1 downto 0); begin if reset='1' then cv:=(others=>'0'); elsif rising_edge(clk) then cv:= not cv(0) & cv(n-1 downto 1); -- function to shift right end if; countout<=cv; end process; end aJohnsoncounter;

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Pulse-width modulator library ieee; use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; entity pwmodulator is port ( clk: in std_logic; inpval: in std_logic_vector(3 downto 0); pwmout: out std_logic ); end pwmodulator; architecture a_pwmodulator of pwmodulator is signal icounter: std_logic_vector(3 downto 0); begin process(clk) begin if rising_edge(clk) then icounter<=icounter+1; if icounter>=inpval then pwmout<='0'; else pwmout<='1'; end if; end if; end process; end a_pwmodulator; Multiplexer library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mux is port ( di0, di1, di2, di3: in std_logic_vector(7 downto 0); adr: in std_logic_vector(1 downto 0); dout: out std_logic_vector(7 downto 0) ); end mux; architecture a_mux of mux is begin process(di0, di1, di2, di3, adr) begin case adr is when "00" => dout<= di0; when "01" => dout<= di1; when "10" => dout<= di2; when "11" => dout<= di3; end case; end process; -- or write like this -- muxfunction: with adr select -- dout<= -di0 when "00", -di1 when "01", -di2 when "10",

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-di3 when "11"; end a_mux; Rotate (page 79) library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity ab is generic(n: positive :=3); port ( a: in std_logic_vector(n-1 downto 0); z: out std_logic_vector(2**n-1 downto 0) ); end ab; architecture rotate of ab is constant z_out: bit_vector(2**n-1 downto 0) := (0 => '1', others => '0'); begin z <= to_stdlogicvector (z_out sll -- shift z_out by numbers defined to_integer(unsigned(a))); -- convert from unsigned(a) to integer numbers(1,2,3,...) end rotate; N bit adder library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; entity page85 is generic(n: natural :=4); port ( a, b: in std_logic_vector(n-1 downto 0); cin: in std_logic; sum: out std_logic_vector(n-1 downto 0); cout: out std_logic ); end page85; architecture unsgned of page85 is signal result: unsigned(n downto 0); signal carry: unsigned(n downto 0); constant zeros: unsigned(n-1 downto 0) := (others => '0'); begin carry <= (zeros & cin); --to convert cin from a single bit to a vector of length n+1 result <= ('0' & unsigned(a)) + ('0' & unsigned(b)) + carry; sum <= std_logic_vector(result(n-1 downto 0)); cout <= result(n); end unsgned; -- remark: if it's too complicated to convert to unsigned and then back to std_logic, -- use library ieee.std_logic_unsigned.all and ieee.std_logic_arith.all -- then we can write the program as follow: -- architecture unsgned of page85 is -- signal result: std_logic_vector(n downto 0); -- signal carry: std_logic_vector(n downto 0); -- constant zeros: std_logic_vector(n-1 downto 0) := (others => '0'); -- begin -- carry <= (zeros & cin); --to convert cin from a single bit to a vector of length n+1 -- result <= ('0' & a) + ('0' & b) + carry; -- sum <= result(n-1 downto 0); -- cout <= result(n);
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Loop library ieee; use ieee.std_logic_1164.all; entity page89 is port ( a: in std_logic_vector(0 to 3); y: out std_logic ); end page89; architecture behaviour of page89 is begin process(a) is variable even: std_logic; begin even:='0'; for i in a'range loop if a(i)='1' then even:= not even; end if; end loop; y <= even; end process; end behaviour; Shift register library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity shiftreg is port ( clk, sw_shiftl, sw_load: in bit; data: in bit_vector(7 downto 0); output: buffer bit_vector(7 downto 0) ); end shiftreg; architecture a_shiftreg of shiftreg is begin process begin wait until clk='1'; if sw_load='1' then output<= data; elsif sw_shiftl='1' then shift: for i in 0 to 6 loop output(i+1)<=output(i); end loop; output(0)<=output(7); end if; end process; end a_shiftreg;

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Shift register right library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity shiftright is port ( clk, sw_shift, sw_load: in bit; load: in bit_vector(7 downto 0); output: buffer bit_vector(7 downto 0) ); end shiftright; architecture a_shiftright of shiftright is begin process begin wait until clk='1'; if sw_load='1' then output<=load; elsif sw_shift='1' then for i in 0 to 6 loop output(i)<=output(i+1); end loop; output(7)<=output(0); end if; end process; end a_shiftright; Parallel input serial output library ieee; use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; entity parinserout is port ( datain: in std_logic_vector(7 downto 0); startinp: in std_logic; output: out std_logic; clk: in std_logic ); end parinserout; architecture behaviour of parinserout is signal data: std_logic_vector(7 downto 0); begin process(clk) begin if rising_edge(clk) then if startinp='1' then data<=datain; else data(6 downto 0)<=data(7 downto 1); data(7)<='0'; end if; end if; end process; output<=data(0); end behaviour;

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Frequency measurer library ieee; use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; entity freqmeasurer is port ( infr: in std_logic; reset, hold: in std_logic; frout: out std_logic_vector(15 downto 0) ); end freqmeasurer; architecture behaviour of freqmeasurer is signal fcount: std_logic_vector(15 downto 0); begin process(reset,hold,infr) begin if (rising_edge(infr)) and (hold='0') then fcount<=fcount+1; end if; if (reset='1') then fcount<="0000000000000000"; elsif (hold='1') then fcount<=fcount; frout<=fcount; end if; end process; end behaviour; Parallel input serial output library ieee; use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; entity parinserout is port ( datain: in std_logic_vector(7 downto 0); startinp: in std_logic; output: out std_logic; clk: in std_logic ); end parinserout; architecture behaviour of parinserout is signal data: std_logic_vector(7 downto 0); begin process(clk) begin if rising_edge(clk) then if startinp='1' then data<=datain; else data(6 downto 0)<=data(7 downto 1); data(7)<='0'; end if; end if; end process; output<=data(0); end behaviour;

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Shift register left or right library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity shiftregister is generic(n: natural :=6); port ( clk: in bit; datin, shiftleft: in bit; data: in std_logic_vector(n-1 downto 0); output: buffer std_logic_vector(n-1 downto 0) ); end shiftregister; architecture behaviour of shiftregister is begin process begin wait until clk='1'; if datin='1' then output<=data; elsif shiftleft='1' then for i in 0 to n-2 loop output(i+1)<=output(i); end loop; output(0)<=output(n-1); elsif shiftleft='0' then for i in 0 to n-2 loop output(i)<=output(i+1); end loop; output(n-1)<=output(0); end if; end process; end behaviour; Shift pulse generator for auto shift register library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity gen_shiftpulse is generic(n: natural :=6); port ( clk: in std_logic; shift: out std_logic ); end gen_shiftpulse; architecture behaviour of gen_shiftpulse is signal ishift: std_logic; begin process(clk) variable ccnt: integer range 0 to n-1; begin if rising_edge(clk) then if ccnt=0 then ccnt:=n-1; ishift<= not ishift; else ccnt:=ccnt-1; end if;

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end if; end process; shift<=ishift; end behaviour; LCD *.C Program #define LCD_CMD ( char *) 0x0003000 #define LCD_DAT ( char *) 0x0003008 //Function Prototypes int wait(int); void lcd_init(void); void lcd_write_character(char); void lcd_write_command(int, int); int main() { int sl,ind; char character; char text1[]="Hello World\0"; char text2[]="FH Jena ET/IT"; lcd_init(); ind=0; character=text1[ind]; while (character != 0) { lcd_write_character (character); ind=ind+1; character=text1[ind]; } /* write to 2. Line */ lcd_write_command(0xc0, 0x232c0); for (ind=0;ind<sizeof(text2)-1;ind++) { lcd_write_character (text2[ind]); } return 1; } void lcd_init(void) // function initializing LCD { int cntrl; *LCD_CMD=0x38; // 1. Command cntrl=wait(0x432c0); *LCD_CMD=0x38; // 2. Command cntrl=wait(0x1A40); *LCD_CMD=0x38; // 3. Command cntrl=wait(0x52080); *LCD_CMD=0x38; // 4. Command cntrl=wait(0x432c0); *LCD_CMD=0x08; // Display on cntrl=wait(0x1a40); *LCD_CMD=0x0c; cntrl=wait(0x1a40); *LCD_CMD=0x06; // Cursor control cntrl=wait(0x1a40); *LCD_CMD=0x02; // DDRAM Address = 0 cntrl=wait(0x20d00); *LCD_CMD=0x01; // Clear Display cntrl=wait(0x20d00); } void lcd_write_character (char zchn) { int ctrl; ctrl=0x22; *LCD_DAT=zchn; ctrl=wait(0x1a40);

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} void lcd_write_command(int command, int cmdwait) { int waitreturn; *LCD_CMD=command; waitreturn=wait(cmdwait); } FSM

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