EEE598 Final Report v1

EEE598: Final Project
December 5, 2013
EEE598: Fall 2013 Final Project
Munaf Hussain Shaik (ASU ID: 1202751779)

Alfonso Albason (ASU ID: 1206976273)
Submission date: 12/05/2013
Shaik, Albason
Table of Contents
1.
Introduction ................................................................................................................................................4
2.
Problem description ....................................................................................................................................4
3.
Top-level architecture .................................................................................................................................6

3.1
Filter choices ..........................................................................................................................................6
3.1.1.
High-pass filter ...............................................................................................................................6
3.1.2.
Low-pass filter ................................................................................................................................6
3.1.3.
Notch filter......................................................................................................................................8
3.2
Bi-quad design ........................................................................................................................................9
3.2.1.
LPF .................................................................................................................................................9
3.2.2.
HPF ...............................................................................................................................................10
3.2.3.
Notch filter....................................................................................................................................11
3.3
4.
Z-domain analysis ................................................................................................................................12

Subsystem design and descriptions ..........................................................................................................13
4.1
Amplifier ..............................................................................................................................................13
4.1.1.
Introduction ..................................................................................................................................13
4.1.2.
Design ...........................................................................................................................................13
4.1.3.
Schematics ....................................................................................................................................13
4.1.4.
Output waveforms spec verification ..........................................................................................14
4.2
Switch ...................................................................................................................................................15
4.2.1.
Introduction ..................................................................................................................................15
4.2.2.
Design ...........................................................................................................................................15
4.2.3.
Schematics ....................................................................................................................................15
4.2.4.
4.3
Digital blocks gates, non-overlapping clock generator .....................................................................17
4.3.1.
Introduction ..................................................................................................................................17
4.3.2.
Design ...........................................................................................................................................17
4.3.3.
Schematics ....................................................................................................................................17
4.3.4.
4.4
High-pass filter 2 kHz........................................................................................................................20
4.4.1.
Introduction ..................................................................................................................................20
4.4.2.
Schematics ....................................................................................................................................20
4.4.3.
4.5
Low-pass filter 20 kHz ......................................................................................................................24
Introduction
4.5.1.
Introduction ..................................................................................................................................24
4.5.2.
Schematics ....................................................................................................................................24
4.5.3.

Notch filter 32.99 kHz .......................................................................................................................27
4.6
4.6.1.
Introduction ..................................................................................................................................27
4.6.2.
Schematics ....................................................................................................................................27
4.6.3.
5.
System integration ....................................................................................................................................31

5.1
Schematic of full filter ..........................................................................................................................31
5.2
Results ..................................................................................................................................................31
5.2.1.
6.
Filter gain......................................................................................................................................31
Performance..............................................................................................................................................33
6.1
Operation vs. supply .............................................................................................................................33
6.2
Layout area estimate .............................................................................................................................34
7.
Conclusion ................................................................................................................................................34
8.
Appendix ..................................................................................................................................................35
8.1
Appendix A: spectre Netlist .................................................................................................................35
8.2
Appendix B: References .......................................................................................................................41
List of Figures
Figure 1: Filter Transfer function ..............................................................................................................................5
Figure 2: HPF Transfer function ...............................................................................................................................6
Figure 3: LPF Transfer function................................................................................................................................7
Figure 4: Notch filter Transfer function ....................................................................................................................8
Figure 5: Bi-quad LPF implementation (2nd order) ...................................................................................................9
Figure 6: Switched-cap implementation of LPF .....................................................................................................10
Figure 7: Bi-quad HPF implementation (2nd order) ................................................................................................10
Figure 8: Bi-quad notch filter implementation (2nd order) ......................................................................................11
Figure 9: s- to Z-domain conversion .......................................................................................................................12
Figure 10: Amplifier schematic...............................................................................................................................13
Figure 11: Amplifier test bench & Iq ......................................................................................................................13
Figure 12: Amplifier gain vs. supply ......................................................................................................................14
Shaik, Albason
Figure 13: Amplifier parameters vs. supply ............................................................................................................14
Figure 14: T-gate switch schematic ........................................................................................................................15
Figure 15: T-gate switch test bench ........................................................................................................................16
Figure 16: Switch Ron simulation - Ron = 428 Ohms ............................................................................................16
Figure 17: Non-overlapping clock generator schematic .........................................................................................17
Figure 18: Inverter schematic..................................................................................................................................18
Figure 19: NOR gate schematic ..............................................................................................................................18
Figure 20: Non-overlapping clock generation ........................................................................................................19
Figure 21: Non-overlapping clocks - zoomed .........................................................................................................19
Figure 22: HPF continuous-time (CT) implementation ..........................................................................................20
Figure 23: Non-optimized switch version of HPF ..................................................................................................21
Figure 24: HPF implementation with optimized switch usage ...............................................................................22
Figure 25: HPF gain plot .........................................................................................................................................23
Figure 26: HPF implementation with non-optimized switches ...............................................................................24
Figure 27: LPF implementation with optimized switch implementation ................................................................25
Figure 28: LPF gain plot (@ 20kHz) ......................................................................................................................26
Figure 29: Notch filter - CT implementation ..........................................................................................................27
Figure 30: Notch filter implementation with non-optimized switches....................................................................28
Figure 31: Notch filter implementation with switch optimization ..........................................................................29
Figure 32: Notch filter gain response ......................................................................................................................30
Figure 33: Filter transfer characteristics..................................................................................................................31
Figure 34: Filter transfer characteristics shown on a linear frequency axis ............................................................32
Figure 35: Filter transfer function vs. supply ..........................................................................................................33
Figure 36: Sweep showing all required parameters vs. supply ...............................................................................34
List of Tables
Table 1: Project specifications ..................................................................................................................................4
Introduction
1. Introduction
The purpose of the project is to design, simulate and verify an audio-band filter. The application for such an
audio band filter can be found in voice communication systems such as cordless phones, mobile phones, Walkietalkies etc. The major purpose of the filter is to suppress non-audio frequencies especially the carrier signal at
32.99 kHz.
The technology used for this project is tsmc35 which has transistors at a process node of 400nm. A crystal
oscillator of 3.6864 MHz is also assumed to be available. Also, it is assumed that a current reference of 5A is
available along with a reference voltage at
The filter has been implemented using standard switched-capacitor topologies and cascade based design
methodology. It has been simulated in Cadence using SpectreRF (PSS, PAC).
2. Problem description
The filter for the project has been designed according to the following specifications:
Table 1: Project specifications
Specification
Value
Units
Supply voltage
2.7 3.3
Supply current
mA
Passband
2 20
kHz
Passband ripple
+/- 2
dB
Passband gain variation
-2/3
dB
Low frequency rolloff
40
dB/dec
Carrier frequency
32.99
kHz
We have chosen to implement the filter as 3 parts: High-pass filter (@ 2kHz), Low-pass filter (@ 20kHz) and a
notch filter (@ 32.99 kHz).
Shaik, Albason
The implemented transfer function has the following AC gain characteristics:
Figure 1: Filter Transfer function
All the filters have been implemented using standard Tow-Thomas bi-quad topology. This can be implemented
using switched-capacitor implementation using 2 amplifiers per 2nd order section. This project requires 4 such
sections (at least 8 amplifiers).
Top-level architecture
3. Top-level architecture
3.1
Filter choices
3.1.1. High-pass filter

The low-pass filter at 2 kHz has been designed as a 2nd order Butterworth filter. The filter transfer function
(prototype) for maximally flat high-pass response is:
( )
The bode plots for the above transfer function is as follows:
Figure 2: HPF Transfer function
A Butterworth filter has been chosen as it gives a flat response and linear gain drop in stop band.
3.1.2. Low-pass filter

The low-pass filter at 20 kHz has been designed as a 4th order Chebyshev filter. The filter transfer function
(prototype) for a fast transition band is:
Shaik, Albason
( )
Figure 3: LPF Transfer function
A Chebyshev filter has been chosen as it gives a flat transition band. A flat transition band is important in this
case as this filter is adjacent to a notch filter at a frequency very close to the transition band.
3.1.3. Notch filter

The notch filter at 32.99 kHz has been designed as a 2th order Butterworth filter. The filter transfer function
(prototype) is:
( )
Figure 4: Notch filter Transfer function
Care has been taken in the actual design to be able to put together all the filter blocks accounting for additional
attenuation from the other stages.
Shaik, Albason
3.2
Bi-quad design
All the bi-quad based filters can be converted for switched capacitor implementation by replacing Rs with
switch-capacitor. Also, the filters can be scaled to higher frequencies from prototype operation as follows:
The value of R is assumed to be
and
, thus
3.2.1. LPF
R
R*Q
C
R
VIN
C
R
VLPF
Figure 5: Bi-quad LPF implementation (2nd order)
For the LPF,
. Thus,
CR/Q
CR
Switch-cap implementation of LPF

2
3.2.1.1.
= VCM
CR
CR
VIN
10
VLPF
Figure 6: Switched-cap implementation of LPF
The number of switches has also been optimized by re-using switches with same clock phases and terminal
connections.
3.2.2. HPF
R
R*Q
R
VIN
C
R
C
R
R
Q*R
R
VHPF
Figure 7: Bi-quad HPF implementation (2nd order)
Shaik, Albason
For the LPF,
. Thus,
3.2.3. Notch filter

R
R*Q
VIN
C
R
Q*R
R
Vnotch
Figure 8: Bi-quad notch filter implementation (2nd order)
For the LPF,
. Thus,
The notch filter and HPF have also been implemented in switched capacitor form in a similar fashion as the LPF.
11
3.3
Z-domain analysis
s to Z conversion
C = 271.71 fF
1M
C = 271.71 fF
-R
1M
12
Figure 9: s- to Z-domain conversion
Since the sampling frequency

, the system is oversampled at
is much greater than the highest frequency of interest

.
Shaik, Albason
4. Subsystem design and descriptions

4.1
Amplifier
4.1.1. Introduction
The amplifier for the current design/application has to be capable of driving a
value
resistor or a capacitor of
. A folded cascode amplifier would be a good choice because the output impedance of the
amplifier is very high and would suit this application.
4.1.2. Design
The amplifier designed for this project is a standard nMOS input folded-cascode amplifier enabled by a reference
current of
approximately
. The amplifier has a typical gain of 65 dB and GBW of about 80 MHz with a quiescent current of
.
4.1.3. Schematics
Figure 10: Amplifier schematic
Figure 11: Amplifier test bench & Iq
13
14
Subsystem design and descriptions
4.1.4. Output waveforms spec verification
Figure 12: Amplifier gain vs. supply
Figure 13: Amplifier parameters vs. supply
Shaik, Albason
4.2
Switch
4.2.1. Introduction
The switch is the most important component of a Switch-cap circuit. A transmission gate switch has been chosen
for this design as it enables use with wide input signal range.
4.2.2. Design
A transmission gate switch has been designed with an
size
. The nMOS is of size
4.2.3. Schematics
Figure 14: T-gate switch schematic
and pMOS is of
15
16
Figure 15: T-gate switch test bench
Figure 16: Switch Ron simulation - Ron = 428 Ohms
Shaik, Albason
4.3
Digital blocks gates, non-overlapping clock generator
4.3.1. Introduction
In order for the switched capacitor circuit to function properly, we require non-overlapping clocks. These nonoverlapping clock phases are generated using cross-coupled NOR gates with delay.
4.3.2. Design
The design is shown below.
4.3.3. Schematics
Figure 17: Non-overlapping clock generator schematic
17
18
Figure 18: Inverter schematic
Figure 19: NOR gate schematic
Shaik, Albason
Figure 20: Non-overlapping clock generation
Figure 21: Non-overlapping clocks - zoomed
19
20
4.4
High-pass filter 2 kHz
4.4.1. Introduction
The High-pass filter has been designed as a 2nd order Butterworth bi-quad. The design and parameter values have
been discussed above.
The output gain plot shows the gain to be
because the output is available during one clock phase. Thus,
the average value of output is half of the actual output voltage.
4.4.2. Schematics
The design makes use of standard capacitors and the MOS switches and amplifier discussed above.
4.4.2.1.
Continuous-time implementation
Figure 22: HPF continuous-time (CT) implementation
Shaik, Albason
4.4.2.2.
Switched-capacitor implementation
Figure 23: Non-optimized switch version of HPF
21
22
Figure 24: HPF implementation with optimized switch usage
Shaik, Albason
Figure 25: HPF gain plot
the average value of output is half of the actual output voltage. This is taken care of by designing the subsequent
stages accordingly.
23
24
4.5
Low-pass filter 20 kHz
4.5.1. Introduction
4.5.2. Schematics
4.5.2.1.
Figure 26: HPF implementation with non-optimized switches
Shaik, Albason
Figure 27: LPF implementation with optimized switch implementation
25
26
Figure 28: LPF gain plot (@ 20kHz)
The peak at 20kHz is intentional as the notch filter has been designed to have a wide notch bandwidth and has an
attenuation of 10 dB at 20 kHz. The notch characteristics are shown in the subsequent section.
Shaik, Albason
4.6
Notch filter 32.99 kHz
4.6.1. Introduction

The design makes use of a CDS style last gain stage as it is important to have the output available during both
clock phases.
4.6.2. Schematics
4.6.2.1.
Continuous-time implementation
Figure 29: Notch filter - CT implementation
27
28
4.6.2.2.
Figure 30: Notch filter implementation with non-optimized switches
Shaik, Albason
Figure 31: Notch filter implementation with switch optimization
29
30
Figure 32: Notch filter gain response
Shaik, Albason
5. System integration
5.1
Schematic of full filter
5.2
Results
5.2.1. Filter gain
Figure 33: Filter transfer characteristics
31
32
System integration
Figure 34: Filter transfer characteristics shown on a linear frequency axis
Shaik, Albason
6. Performance
6.1
Operation vs. supply
Figure 35: Filter transfer function vs. supply
33
34
Conclusion
Iq
Figure 36: Sweep showing all required parameters vs. supply
6.2
Layout area estimate
Sum of area of all transistors =
which is approximately 20% of total transistor area (Source, Drain,
Contacts etc.)
Complete area of transistors =
Area of Capacitors (at 5fF/m2)
(includes additional area for contacts, routing etc.)
Total Area
7. Conclusion
Thus, the complete filter has been designed and simulated according to the given specifications.
Shaik, Albason
8. Appendix
8.1
Appendix A: spectre Netlist
// Generated for: spectre

// Generated on: Nov 27 21:37:11 2013
// Design library name: EEE598_Amp
// Design cell name: filter_test
// Design view name: schematic
simulator lang=spectre
global 0 vdd!
include
"/home/eda/cadence/ic5141/tools/dfII/samples/artist/ahdlLib/quantity.spectre"
parameters Ron=1k Roff=100M Fin=3.6864M vdd=3 vcm=vdd/2
include "/home/ncsu-cdk-1.5.1/models/spectre/standalone/tsmc35P.m"
include "/home/ncsu-cdk-1.5.1/models/spectre/standalone/tsmc35N.m"
// Library name: EEE598_Amp
// Cell name: amp_101
// View name: schematic
subckt amp_101 Vinm Vinp Vout
C0 (Vout 0) capacitor c=750.00f
I0 (vdd! net0184) isource dc=5u type=dc
P11 (net075 Vbp2 vdd! vdd!) tsmc35P w=3.6u l=800n as=3.6e-12 \
ad=3.6e-12 ps=9.2u pd=9.2u m=1 region=sat
P12 (Vbn Vbp1 net075 vdd!) tsmc35P w=3.6u l=400n as=3.6e-12 ad=3.6e-12 \
ps=9.2u pd=9.2u m=1 region=sat
P13 (net0110 Vbp1 net071 vdd!) tsmc35P w=3.6u l=400n as=3.6e-12 \
P14 (net071 Vbp2 vdd! vdd!) tsmc35P w=3.6u l=800n as=3.6e-12 \
P10 (net0101 Vbp2 vdd! vdd!) tsmc35P w=30u l=400n as=3e-11 ad=3e-11 \
P8 (net093 Vbp2 vdd! vdd!) tsmc35P w=30u l=400n as=3e-11 ad=3e-11 \
P7 (Vout Vbp1 net093 vdd!) tsmc35P w=20u l=1u as=2e-11 ad=2e-11 \
P9 (net0163 Vbp1 net0101 vdd!) tsmc35P w=20u l=1u as=2e-11 ad=2e-11 \
P2 (net095 Vbp2 vdd! vdd!) tsmc35P w=3.6u l=800n as=3.6e-12 ad=3.6e-12 \
P1 (Vbp2 Vbp1 net095 vdd!) tsmc35P w=3.6u l=400n as=3.6e-12 ad=3.6e-12 \
P0 (Vbp1 Vbp1 vdd! vdd!) tsmc35P w=1.8u l=2.8u as=1.8e-12 ad=1.8e-12 \
N15 (Vbn Vbn 0 0) tsmc35N w=1.2u l=8u as=1.2e-12 ad=1.2e-12 ps=4.4u \
pd=4.4u m=1 region=sat
N16 (net0110 Vbn net0108 0) tsmc35N w=1.2u l=400n as=1.2e-12 \
N17 (net0108 net0110 0 0) tsmc35N w=1.2u l=400n as=1.2e-12 ad=1.2e-12 \
N8 (net0101 Vinp net0104 0) tsmc35N w=36.0u l=400n as=3.6e-11 \
N11 (net0113 net0163 0 0) tsmc35N w=1.2u l=1u as=1.2e-12 ad=1.2e-12 \
35
36
Appendix
N12 (net0163 Vbn net0105 0) tsmc35N w=2.4u l=400n as=2.4e-12 \
N7 (net0104 net0184 0 0) tsmc35N w=100.0000u l=400n as=1e-10 ad=1e-10 \
N13 (net0105 net0163 0 0) tsmc35N w=1.2u l=1u as=1.2e-12 ad=1.2e-12 \
N10 (Vout Vbn net0113 0) tsmc35N w=2.4u l=400n as=2.4e-12 ad=2.4e-12 \
N9 (net093 Vinm net0104 0) tsmc35N w=36.0u l=400n as=3.6e-11 \
N2 (Vbp2 net0184 0 0) tsmc35N w=1.2u l=400n as=1.2e-12 ad=1.2e-12 \
N1 (Vbp1 net0184 0 0) tsmc35N w=600n l=400n as=6e-13 ad=6e-13 ps=3.2u \
N0 (net0184 net0184 0 0) tsmc35N w=600n l=400n as=6e-13 ad=6e-13 \
ends amp_101
// End of subcircuit definition.
// Cell name: not_gate
subckt not_gate A Y
N0 (Y A 0 0) tsmc35N w=3u l=400n as=3e-12 ad=3e-12 ps=8u pd=8u m=1 \
region=sat
P0 (Y A vdd! vdd!) tsmc35P w=12.0u l=400n as=1.2e-11 ad=1.2e-11 \
ends not_gate
// Cell name: switch_mos
subckt switch_mos S1 S2 Vctrl
P0 (S2 VctrlZ S1 vdd!) tsmc35P w=10u l=400n as=1e-11 ad=1e-11 ps=22.0u \
N0 (S2 Vctrl S1 0) tsmc35N w=5u l=400n as=5e-12 ad=5e-12 ps=12.0u \
I4 (Vctrl VctrlZ) not_gate
ends switch_mos
// Cell name: notch_33k_opt
subckt notch_33k_opt Vcm Vin Vout ph1 ph2
I172 (net0102 Vcm Vout) amp_101
I32 (net142 Vcm net84) amp_101
C53 (net075 net079) capacitor c=(1/1.1)*271.27f
C73 (net0129 net075) capacitor c=271.27f
Shaik, Albason
C10 (net142 net84) capacitor c=4.5p
C8 (net169 net187) capacitor c=4.5p
I236 (Vcm net078 ph1) switch_mos
I173 (net079 Vout ph1) switch_mos
I105 (net86 net187 ph2) switch_mos
I41 (Vin net151 ph2) switch_mos
ends notch_33k_opt
// Cell name: lpf_20k_opt
subckt lpf_20k_opt Vcm Vin Vout ph1 ph2
37
38
Appendix
C22 (net29 net47) capacitor c=8p
C24 (net20 net115) capacitor c=(1/1)*271.27f
C32 (net124 Vout) capacitor c=8p
ends lpf_20k_opt
// Cell name: hpf_2k_opt
subckt hpf_2k_opt Vcm Vin Vout ph1 ph2
C34 (net27 net29) capacitor c=(1/1)*271.27f
Shaik, Albason
ends hpf_2k_opt
// Cell name: nor_gate
subckt nor_gate A Y B
N1 (Y B 0 0) tsmc35N w=3u l=400n as=3e-12 ad=3e-12 ps=8u pd=8u m=1 \
region=sat
N0 (Y A 0 0) tsmc35N w=3u l=400n as=3e-12 ad=3e-12 ps=8u pd=8u m=1 \
region=sat
P1 (net31 A vdd! vdd!) tsmc35P w=12.0u l=400n as=1.2e-11 ad=1.2e-11 \
P0 (Y B net31 vdd!) tsmc35P w=12.0u l=400n as=1.2e-11 ad=1.2e-11 \
ends nor_gate
// Cell name: non_ovl_mos
subckt non_ovl_mos CLK PH1 PH2
I8 (CLK net21 PH2) nor_gate
I9 (PH1 net24 net34) nor_gate
I17 (net029 net030) not_gate
I18 (net030 PH1) not_gate
I7 (CLK net34) not_gate
I19 (net024 PH2) not_gate
ends non_ovl_mos
// Cell name: filter_test
I5 (Vcm net020 Vout ph1 ph2) notch_33k_opt
I7 (Vcm net029 net020 ph1 ph2) lpf_20k_opt
I8 (Vcm Vin net029 ph1 ph2) hpf_2k_opt
C11 (Vout 0) capacitor c=1p
I1 (net4 ph1 ph2) non_ovl_mos
V3 (net4 0) vsource type=pulse val0=0.0 val1=vdd period=1/Fin rise=100p \
fall=100p width=0.5/Fin
V9 (Vin 0) vsource dc=vcm pacmag=1 type=dc
V2 (Vcm 0) vsource dc=vcm type=dc
V1 (vdd! 0) vsource dc=vdd type=dc
39
40
Appendix
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
checklimitdest=psf
dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status
dcOpInfo info what=oppoint where=rawfile
pss pss fund=3.6864M harms=2 errpreset=conservative tstab=10.1u
+
annotate=status
pac pac sweeptype=absolute start=100 stop=100k dec=200
+
values=[32.88k 32.99k 33k 33.11k 33.22k] maxsideband=1
+
annotate=status
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
save Vin Vout ph1 ph2 net020
saveOptions options save=all
Shaik, Albason
8.2
Appendix B: References
VLSI Analog Signal Processing Circuits Hongjiang Song
The Arts of VLSI Circuit Design Hongjiang Song
Design of Analog Filters Rolf Schaumann, Mac E. Van Valkenburg
Lecture notes for EEE598 by Dr. Hongjiang Song at ASU
Lecture notes for Analog Filter Design by Prof. David Johns and Prof. Ken Martin at University of
Toronto
41

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EEE598: Final Project

EEE598: Fall 2013 Final Project

Munaf Hussain Shaik (ASU ID: 1202751779)

Submission date: 12/05/2013

Problem description ....................................................................................................................................4

Top-level architecture .................................................................................................................................6

Filter choices ..........................................................................................................................................6

High-pass filter ...............................................................................................................................6

Low-pass filter ................................................................................................................................6

Bi-quad design ........................................................................................................................................9

Z-domain analysis ................................................................................................................................12

Output waveforms spec verification ..........................................................................................14

Output waveforms spec verification ..........................................................................................16

Digital blocks gates, non-overlapping clock generator .....................................................................17

Output waveforms spec verification ..........................................................................................19

High-pass filter 2 kHz........................................................................................................................20

Output waveforms spec verification ..........................................................................................23

Low-pass filter 20 kHz ......................................................................................................................24

Output waveforms spec verification ..........................................................................................26

Output waveforms spec verification ..........................................................................................30

System integration ....................................................................................................................................31

Schematic of full filter ..........................................................................................................................31

Operation vs. supply .............................................................................................................................33

Layout area estimate .............................................................................................................................34

Appendix A: spectre Netlist .................................................................................................................35

Appendix B: References .......................................................................................................................41

Passband gain variation

Low frequency rolloff

Figure 1: Filter Transfer function

3.1.1. High-pass filter

The bode plots for the above transfer function is as follows:

Figure 2: HPF Transfer function

3.1.2. Low-pass filter

The bode plots for the above transfer function is as follows:

Figure 3: LPF Transfer function

3.1.3. Notch filter

The bode plots for the above transfer function is as follows:

Figure 4: Notch filter Transfer function

The value of R is assumed to be

Figure 5: Bi-quad LPF implementation (2nd order)

For the LPF,

Switch-cap implementation of LPF

Figure 6: Switched-cap implementation of LPF

Figure 7: Bi-quad HPF implementation (2nd order)

3.2.3. Notch filter

Figure 8: Bi-quad notch filter implementation (2nd order)

For the LPF,

Figure 9: s- to Z-domain conversion

Since the sampling frequency

is much greater than the highest frequency of interest

4. Subsystem design and descriptions

amplifier is very high and would suit this application.

Figure 10: Amplifier schematic

Figure 11: Amplifier test bench & Iq

Subsystem design and descriptions

4.1.4. Output waveforms spec verification

Figure 12: Amplifier gain vs. supply

Figure 13: Amplifier parameters vs. supply

. The nMOS is of size

Figure 14: T-gate switch schematic

Subsystem design and descriptions

Figure 15: T-gate switch test bench

4.2.4. Output waveforms spec verification

Figure 16: Switch Ron simulation - Ron = 428 Ohms