EC2303 COMPUTER ARCHITECTURE AND ORGANIZATION

QUESTION BANK WITH ANSWER

UNIT-1 INTRODUCTION

2MARKS
1. Define Computer Architecture.
Computer Architecture Is Defined As The Functional Operation Of The Individual H/W unit In A
Computer System And The Flow Of Information Among The Control Of those units

2. State and explain the performance equation?
Suppose that the average number of basic steps needed to execute one machine instruction
is S, where each basic step is completed in one clock cycle. If the clock cycle rate is R cycles per
second, the program execution time is given by
T = (N x S) / R
This is often referred to as the basic performance equation.

3. Specify the CPU Performance Equation.
CPU Performance Decomposed into Three Components:
Clock Frequency (-)
Determined by technology and influenced by organization.
Clocks per Instruction (CPI)
Determined by ISA, microarchitecture, compiler, and program.
Instruction Count (IC)
Determined by program, compiler, and ISA.
These combined to form CPU Performance Equation
t
T
= 1 CPI IC
where Tt denotes the execution time.

4. List the instructions supported by IAS computer
Data transfer
Unconditional branch
Conditional branch
Arithmetic
Address modify

5. What is meant by IR & IBR?
Program control unit fetches two instructions simultaneously from memory. The opcode of the
first instruction is placed in the instruction register (IR) and the instruction that is not to be
executed immediately is placed in the instruction buffer register (IBR).

6. List the various register level components?
Combinational
Word gates
Multiplexers & Demultiplexers
Decoders & Encoders
Adders & Subtractors
Arithmetic & Logic Unit
Programmable Logic devices
Sequential
Registers
Shift Registers
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Counters
Programmable Logic devices

7. Define interrupt and ISR?
An interrupt is a request from an I/O device for service by the processor. The processor provides
the requested service by executing the interrupt service routine.

8. What are condition code flags?
The processors keep track of information about the results of various operations for use by
subsequent conditional branch instructions. This is accomplished by recording the required
information in individual bits, often called condition code flags.

9. Define addressing mode.
The different ways in which the location of an operand is specified in an instruction are referred to
as addressing modes.

10. What is index register?
In index mode the effective address of the operand is generated by adding a constant value to the
contents of a register. The register used may be either a special register or may be any one of a set
of general purpose registers in the processor. This register is referred to as an index register.



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16 MARKS
1. Describe in detail the different kinds of addressing modes with an example.
Addressing modes

Each instruction of a computer specifies an operation on certain data. The are various ways of
specifying address of the data to be operated on. These different ways of specifying data are
called the addressing modes. The most common addressing modes are:

Immediate addressing mode
Direct addressing mode
Indirect addressing mode
Register addressing mode
Register indirect addressing mode
Displacement addressing mode
Stack addressing mode


To specify the addressing mode of an instruction several methods are used. Most often used
are :

a) Different operands will use different addressing modes.
b) One or more bits in the instruction format can be used as mode field. The value of the mode
field determines which addressing mode is to be used.

The effective address will be either main memory address of a register. Immediate
Addressing:
This is the simplest form of addressing. Here, the operand is given in the instruction itself.
This mode is used to define a constant or set initial values of variables. The advantage of this
mode is that no memory reference other than instruction fetch is required to obtain operand.
The disadvantage is that the size of the number is limited to the size of the address field,
which most instruction sets is small compared to word length.

Direct Addressing:

In direct addressing mode, effective address of the operand is given in the address field of the
instruction. It requires one memory reference to read the operand from the given location and
provides only a limited address space. Length of the address field is usually less than the word
length.

Ex : Move P, Ro, Add Q, Ro P and Q are the address of operand. Indirect Addressing:
Indirect addressing mode, the address field of the instruction refers to the address of a word in
memory, which in turn contains the full length address of the operand. The advantage of this
mode is that for the word length of N, an address space of 2N can be addressed. He
disadvantage is that instruction execution requires two memory reference to fetch the operand
Multilevel or cascaded indirect addressing can also be used.

Register Addressing:

Register addressing mode is similar to direct addressing. The only difference is that the
address field of the instruction refers to a register rather than a memory location 3 or 4 bits are
used as address field to refer ence 8 to 16 generate purpose registers. The advantages of
register addressing are Small address field is needed in the instruction.

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Register Indirect Addressing:

This mode is similar to indirect addressing. The address field of the instruction refers to a
register. The register contains the effective address of the operand. This mode uses one
memory reference to obtain the operand. The address space is limited to the width of the
registers available to store the effective address.



Displacement Addressing:

In displacement addressing mode there are 3 types of addressing mode. They are :

1) Relative addressing
2) Base register addressing
3) Indexing addressing.

This is a combination of direct addressing and register indirect addressing. The value
contained in one address field. A is used directly and the other address refers to a register
whose contents are added to A to produce the effective address.

Stack Addressing:

Stack is a linear array of locations referred to as last-in first out queue. The stack is a reserved
block of location, appended or deleted only at the top of the stack. Stack pointer is a register
which stores the address of top of stack location. This mode of addressing is also known as
implicit addressing.

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2. Explain the various Instruction types with examples.

Types of Instruction:
1. Data Transfer
2. Data Processing
3. Program-control instruction
Data Transfer:
The data processing instruction only one memory address and can be specified
at a time multi operand instructions such as add & multiply must use CPU registers to store
some of their operands.
Data-processing instruction by data-transfer instructions that load input
operands into CPU registers or transfer results from the CPU to main memory.
Program-control instruction:
The group of instructions called program control or branch instructions
determine the sequence in which instructions are executed.
The Program Counter PC specifies the address of the next instructions to be
executed. The IAS has two unconditional branch instructions called jump or goto
instructions which load part of X into PC & next instruction to be taken from the left half or
right half of M(X).

Instruction Execution:
The IAS fetches and executes instruction is several steps that form an instructions in
several steps that form an instruction cycle.
Here two instructions arepacked into a-bit word, the IAS fetches two instructions in
each instruction cycle.
One instruction has its opcode placed in the instruction register and its address field (if
any) placed in the address register.








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3. Briefly explain the organization of ISA computer.

The Instruction Set Architecture

The 3 most common types of ISAs are:
1. Stack - The operands are implicitly on top of the stack.
2. Accumulator - One operand is implicitly the accumulator.
3. General Purpose Register (GPR) - All operands are explicitely mentioned, they are either
registers or
memory locations.

Lets look at the assembly code of

A = B + C;

in all 3 architectures:

Stack Accumulator GPR
PUSH A LOAD A LOAD R1,A
PUSH B ADD B ADD R1,B
ADD STORE C STORE R1,C
POP C - -

Not all processors can be neatly tagged into one of the above catagories. The i8086 has many instructio
ns that use implicit operands although it has a general register set. The i8051 is another example, it has
4 banks of GPRs but most instructions must have the A register as one of its operands.

What are the advantages and disadvantages of each of these approachs?

Stack

Advantages: Simple Model of expression evaluation (reverse polish). Short instructions.
Disadvantages: A stack can't be randomly accessed This makes it hard to generate eficient code. The
stack itself is accessed every operation and becomes a bottleneck.


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Accumulator

Advantages: Short instructions.
Disadvantages: The accumulator is only temporary storage so memory traffic is the highest for this
approach.
superscalar processor --can execute more than one instructions per cycle.
cycle--smallest unit of time in a processor.
parallelism--the ability to do more than one thingat once.
pipelining--overlapping parts of a large task to increase throughput without decreasing
latency
Well look at some of the decisions facing an instruction set architect, and

how those decisions were made in the design of the MIPS instruction set.

MIPS, like SPARC, PowerPC, and Alpha AXP, is a RISC (Reduced Instruction Set

Computer) ISA.

fixed instruction length

few instruction formats

load/store architecture

RISC architectures worked because they enabled pipelining. They continue to thrive because they
enable parallelism.

Instruction Length


Variable-length instructions (Intel 80x86, VAX) require multi-step fetch and decode, but
allow for a much more flexible and compact instruction set.
Fixed-length instructions allow easy fetch and decode, and simplify pipelining and
parallelism.




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Accessing the Operands


operands are generally in one of two places:
registers (32 int, 32 fp)
memory (232locations)
registers are
easy to specify
close to the processor (fast access)
the idea that we want to access registers whenever possible led to load-store architectures.
normal arithmetic instructions only access registers
only access memory with explicit loads and stores.

How Many Operands?

Most instructions have three operands (e.g., z = x + y).
Well-known ISAsspecify 0-3 (explicit) operands per instruction.
Operands can be specified implicitly or explicity.

Basic ISA Classes

Accumulator:

1 addressadd Aacc acc + mem[A]

Stack:
0 addressaddtostos+ next

General Purpose Register:

Address add A BEA(A) EA(A) + EA(B)
Address add A B CEA(A) EA(B) + EA(C)


Load/Store:

Address add Ra RbRcRa
Rb+ Rc load Ra RbRa
mem[Rb]
store Ra Rbmem[Rb] Ra
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4. With a neat block diagram explain the Accumulator based CPU.

The CPU organization proposed by von Neumann and his colleagues for the IAS
computer is the basis for subsequent designs is the basis for most subsequent designs.

It comprises a small set of registers and the circuits needed to execute a functionally
complete set of instructions. One of the CPU registers, the accumulator playing a central
role, being used to store an input or output operand in the execution of many instructions.

This shows at the register level the essential structure of a small accumulator
oriented CPU. This organization is typical of first generation computers and low cost
microcontrollers.

Assume for simplicity that instructions and have some fixed word size n bits and
their instruction can be expressed by means of register-transfer operations in our HDL.
Instructions are fetched by the program control unit PCU, whose main register is
the program counter PC. They are executed in the data processing unit DPU, which
contains an n-bit arithmetic logic unit(ALU) and two data registers AC and DR.

Most instructions perform operations of the form,
X1:=f
i
(X1,X2)
Refer page No: 141. Diagram Representation.

5. Explain in detail about CPU organization.

Datapath Design:
Capabilities & performance characteristics of principal Functional Units (FUs):
(e.g., Registers, ALU, Shifters, Logic Units, ...)
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Ways in which these components are interconnected (buses connections,
multiplexors, etc.).
How information flows between components.
Control Unit Design:
Logic and means by which such information flow is controlled.
Control and coordination of FUs operation to realize the targeted Instruction Set
Architecture to be implemented (can either be implemented using a finite state machine or
a microprogram).
Hardware description with a suitable language, possibly using Register Transfer
Notation (RTN).
For a specific program compiled to run on a specific machine A, the
following parameters are provided:
The total instruction count of the program.
The average number of cycles per instruction (average CPI).
Clock cycle of machine A
How can one measure the performance of this machine running this
program?
Intuitively the machine is said to be faster or has better performance running this
program if the total execution time is shorter.
Thus the inverse of the total measured program execution time is a possible performance
measure or metric:
PerformanceA = 1 / Execution TimeA


6. Describe about register level components.

Register level circuits are composed of word oriented devices. The key sequential
component, which gives this level of abstraction its name, is a register, a storage device for
words.
Word gates
Word gates are universal in they suffice to implement any logic circuits.Moreover,word
gate circuits can be analysed Boolean algebra.It is also used to represent scalar vector
operations by a single gate symbol.
Multiplexer
A Multiplexer is a device intended to route data from one of several sources to a
common destination,the source is specified by applying appropriate control to the
multiplexers.
If the maximum number of K input is source and each I/O dataline carries m-bits,the
multiplexer is refered to as a K input, m-bit multiplexer.Multiplexer have the intresting
property that can compute any combinatioal function and so form a type of universal
logic generator.

Decoders
o Main application Address Decoding
o -A 1-out of 2
n
or 1/2
n
decoder is a combinational circuit with n input lines x and 2
n

output lines z such that each of the 2
n
possible input combinations.
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o Encoder
o An Encoder is intented to generate the address or index of an active input line.It is
therefore the inverse of decoder.It has 2
k
input lines and k o/p lines.


Arithmetic Elements
o Simple arithmetic function ,addition and subtraction of fixed point number can be
implemented bycombinational register level components.Adders and Subtracters for
fixed point binary numbers are basic register level components from which we can
derive a variety of arithmetic circuits.
o The adders carry-in and carry-out lines allow several copies of this component to be
chained together to add numbers to arbitrary size.
o Arithmetic components is a magnitude comparator, whose function is to compare
the magnitudes of two binary numbers.

Programmable Logic Devices
A class of components called programmable logic devices or PLDs, a term applied
to ICs containing many gates or other general purpose cells whose
interconnections can be configured or Programmed to implement any desired
combinational or sequential function.

Two Techniques are used to program PLDS
i)Mask Programming
ii)Field Programming

Mask Programming

o It requires a few special steps in the IC-Manufacturing process Field Programming
o It is done by designer or end user in the field via low cost programming units.

Programmable Logic Array

o PLA is universal function generates capable of realizing a set of logic functions that
depend on some maximum number of variables. It consist of an array of AND gates
which realize a set of product terms & a set of OR gates which forms various
logical sum of the product terms.

Programmable Array Logic

o PAL circuits have an AND plane that is programmable but on OR plane with fixed
connections designed to link each output line to a fixed set.
o PAL output can realize only a two level expression containing a most 8 terms. A
PAL advantages are easy of use in some applications as well as higher speed
because output fan-out is restricted.

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