88

Chapter 8

Serial Input/Output

Asynchronous Serial Communications

Serial systems use a single line to transfer data bits one after the other. This reduces the number of
lines but slows down the rate of data transfer. The term asynchronous refers to the fact that each
device uses its own clock. The clocks must run at the same rate but do not need to be synchronized.

The asynchronous I/O subsystem for the 68HC11 is called the serial communications interface (SCI).
The SCI subsystem is used primarily for data communications. In asynchronous serial
communications, the communicating devices are remote (with a distance greater than a few meters),
for example they may communicate over a telephone line.

An asynchronous communication system (or network) must have at least one transmitter and one or
more receivers. A transmitter sends data to be read by the receivers.

Start and Stop Framing

In asynchronous serial communications, the basic unit (group of bits) of communication is the
character or data frame (normally a byte). The transmitter can send frames at any rate and whenever
it feels like it. Hence there is a need for the receiver to know when a frame starts and ends. So each
character is framed by start and stop bits. In the figure given below a constant high signal is
considered to be idle with no data being transmitted. A start bit is always zero (0) and a stop bit is
always a one (1). Also, data bits are transmitted with the LSB first. And voltage does not return to
zero between adjacent 1 bits.



89
Parity

It is used to detect single bit errors in communication. It refers to the quantity of 1 bits in a binary
number. The transmitter generates the parity and the receiver checks it. Parity bit is either a 0 or 1
depending on:

1. the type of parity selected, even or odd
2. the number of 1 bits in the data byte to be transferred

Example: (even parity convention) Assume that the transmitter wants to send the seven bit ASCII
code 0111000 with even parity. Then the transmitted bits (shown in order of transmission from left to
right) are as follows:

0 0001110 1 1
Start Data Parity Stop
Bit bits bit bit

The number of one bits in the frame excluding the start and stop bits but including the parity is even.



Some possible framing configurations

Data Speed and Baud Rate

Serial data speed is the number of bits transmitted per second (bps). Baud is the rate at which the
signal changes. If each signal element represents one bit, then the data speed and baud rate are the
same. In some cases communication requires extra signal bits that are not data. In other cases, a signal
element may encode several bits. If each signal element represents more than one bit, then the data
speed and the baud rate are not equal to each other. In SCI, each signal element encodes 1 bit.


90
Baud rate includes the start, parity and stop bits. In asynchronous serial communications terminology,
for example, 9600 baud means that serial data (including the start and stop bits) is transmitted and
received at the rate of 9600 bits per second. Since there are overheads in the frame

number of data bits
Actual data transfer speed (bps) = -------------------------------- x baud rate
number of frame bits


RS-232 Interface Standard

Most equipments communicating in asynchronous serial mode use the RS-232 standard. This standard
defines the signal levels, connectors and pin assignments, among other things. A serial port is the
serial interface connector plus all the electronics required to make the interface fully functional.

The standard defines 25 different signals, although in practice few of these are used. Most RS-232
interfaces use a mechanical connector with 25 pins known as DB-25. Since few of the 25 signals are
ever used, many serial ports also use a DB-9 connector. It only uses 9 plug pins. These are shown in
the figure below. Only 3 signals are required for a connection: transmit data, receive data and signal
ground.



The RS-232 standard also uses the categorization of the standard organizations such as ISO and
CCITT for equipments of data communications into two types: data terminal equipment (DTE) and
data communications equipment (DCE). Normally, a DTE interfaces with a DCE in order to
communicate with another DTE that is also interfaced to a DCE. A DTE is the initial source of data or
the final recipient. Examples are terminals and computers. The DCE provides the functions to
establish, to maintain and terminate a connection. It also codes and decodes signals as required.
Examples are line drivers and modems for telephone communications. According to the standard, a
DTE uses a plug and a DCE uses a socket. One can make a direct connection between a DCE and a
DTE without crossing wires. But if a DCE is connected to a DCE or a DTE is connected to a DTE
then wires 2 and 3 have to be crossed. Because the two types use their transmit (TxD) and receive
(RxD) lines differently:
DTE: TxD transmits, RxD receives
DCE: TxD receives, RxD transmits

The logic levels used for RS-232 signals differ from the usual digital circuit logic. The nominal RS-
232 data signals are +12 V for logic 0 and 12 V for logic 1. These allow signals to be transmitted
over relatively long distances. Since the RS-232 signal levels differ from normal HCMOS or TTL
levels, it is necessary to use special driver chips for signal conversion. There exists driver chips for

91
interfacing TTL levels to RS-232 levels and one such interfacing example is as follows. In this
example the use of such a chip to build a RS-232 port for a 68HC11 is shown.




DCE DTE




92
Protocols and Flow Control

A protocol is a set of rules for making connections and transferring messages. Flow control refers to
methods of stopping data transfers ad restarting them. When data is to be transferred, there have to be
agreed upon rules by both the transmitter and receiver. Some protocols used in the communications
industry are as follows:

Acknowledge/Not Acknowledge (ACK/NAK) Flow Control: The transmitter waits for the receiver to
acknowledge each block of data before the next block can be sent. Upon reception of a block of data,
the receiver checks it and send an ACK signal (or message) otherwise NAK is sent.

Cyclic Redundancy Check (CRC): Not a single parity but a longer check field is used for error
detection and correction. CRC uses a feedback mechanism to make a code word depend on the
previous history of the message. The transmitter calculates the code for the message block it sent and
adds it to the end of the block. The receiver also calculates the code based on the data it receives.

XON/XOFF Flow Control: A receiver might initiate or stop a transmitter by sending XON and XOFF
signals (messages).

BREAK Signal: used to abort a transfer in midstream or wake up a sleeping receiver. The break signal
drives the line low for longer than a frame time. Recall that each transmitted character has a t least
one bit high, the stop bit. Also, an idle line is always high.

Communication Channel Types

There are three ways to transmit data along a communication channel:

1. simplex (unidirectional)
2. half-duplex (bidirectional but only one direction is active at a given time)
3. full-duplex (bidirectional and both directions are active at a given time)




93
Asynchronous Serial Communications Interface in M68HC11 SCI

The SCI is full duplex asynchronous, serial interface used by the 68HC11 microcontroller. With
additional conversion circuits the SCI can be used to communicate with remote devices using industry
standard cables, telephone lines, or radio transmitters. The SCI subsystem uses port D pin PD1 as a
transmit line and port D pin PD0 as a receive line. These lines can be enabled or disabled by one of
the SCI control registers (SCCR2). When disabled, port D lines can be used as a general parallel I/O
line.

Transmitting a byte is a simple matter of writing bytes to a data register (SCDR). The SCI subsystem
handles the data framing requirements. It does not perform parity generation or checking
automatically. The microcontroller reads serial input by reading the data register to get each character
received. The SCI receiver automatically converts each framed serial character into a parallel byte.

The SCI system uses an internal clock tapped off the main microprocessor clock for serial transfer or
sampling of data. By configuring another control register (BAUD), a program can set the baud rate to
available integral fractions of the system frequency (E).

The receiver and transmitter are double buffered and although they operate independently, they use
the same baud rate and data format. The SCI subsystem uses one data register address ($102F) and
name (SCDR) for both registers. An instruction to write data to SCDR causes data to be sent to the
transmit data register (TDR). An instruction to read SCDR causes data to be read physically from the
receive data register (RDR). The system can send and receive 8-bit or 9-bit data, it has a variety of
interrupts and is fully programmable.


Transmit Operation: The system writes a byte to TDR, which in turn is transferred to the output shift
register. If enabled, the ninth bit as determined by transmit bit 8 (bit T8 in SCCR1) is also transferred
to the shift register. Start and stop bits are generated automatically. The setting of the baud register
determines the shift rate. This can occur while the previous data byte is being shifted out. The term
double buffering is used to refer to the fact that while the shift register is shifting out a byte, the data
buffer is storing the next byte to be transmitted. When the shift register has completed shifting out the

94
byte, the SCI system automatically transfers the contents of the TDR buffer to the shift register. It
starts to shift it out immediately. . Every time the SCI transfers data from the TDR to the output shift
register, it sets the TDRE (transmit data register empty) flag. Writing to TDR buffer clears TDRE
flag.

Receive Operation: If the reciever is awake and a data frame is received, then the data is transferred
from the receive shift register to receive data register (RDR). If configured for 9-bits, the ninth bit (bit
R8 in SCCR1) is also transferred. The setting of register BAUD determines the rate of sampling and
shifting in. A receiver driver routine may read the RDR buffer any time while the next data is being
shifted in. This is also double buffering. In this case the buffer stores the most recent received byte. It
stores the currently received byte while the next byte is shifting in. The software should read the
buffer before the next byte has shifted in completely. Otherwise, it will miss reading the next data
byte. Each time a transfer occurs from the receive shift register to RDR, then RDRF (receive data
ready flag) is set. Reading the RDR buffer resets RDRF.

SCI Related Registers and Their Programming




95
Receive Errors

Overrun Error Flag (OR) : Overrun occurs when a newly received character has been shifted
completely into the receiver before the microprocessor software has read the receive data register. An
occurrence of this error sets OR flag and any data currently in the shift register will be lost.


Noise Error Flag (NF): The receiver uses a sampling clock that has a frequency of 16 times the baud
frequency. Once the receiver has established the bit boundaries, it samples the bits during the eighth,
ninth and tenth cycles of the sampling clock. The system sets flag NF if these samples are not
identical.
Deleted: flog
96


SCI Software

Using and programming the SCI can be broken into three parts:
1. Configuration procedure,
2. Transmit procedure for each byte,
3. Receive procedure for each byte.

1. Configuration procedure:
Select the baud rate. Write to the BAUD register (SCP0-1, SCR0-2),
Select the word length and wake up. Write to the SCCR1 register (M, WAKE),
Enable interrupts, transmit, receive and wake up as required. Write to the SCCR2 register
(TIE,TCIE,RIE,ILIE,TE,RE,RWU)

2. Transmit procedure for each byte:
Poll the SCSR register or respond to the interrupt (read SCSR),
If applicable (M=1), write to T8 in the SCCR1 register,
If TDRE==1, write to the SCDR register.

3. Receive procedure for each byte:
Poll the SCSR register or respond to the interrupt (read SCSR),
If RDRF==1, then read SCDR register,
Option: If there is an error (OR|NF|FE==1), handle the error,
If applicable (M=1), read R8 in the SCCR1 register.





97
Example: 68HC11 needs to communicate over a serial line at 9600 bits per second, using 1 start bit, 1
stop bit, and even parity. Eight-bit characters will be transmitted, including the parity bit. Assume that
the system needs to transmit character string of arbitrary length. To transmit one string, the main
program places the characters into an array and then places $00 immediately after the last character
($00 should not be transmitted). The main program then initiates transmission by writing the first
character to the SCDR and placing the address of the second character in memory location
MEM_PTR. Write an ISR that will cause the remaining characters to be transmitted (It can access
and/or modify MEM_PTR). Use only interrupt driven I/O.

Solution:

Initially SCCR2 should contain 10001000.

XMT_ISR LDX #REGBASE
LDY MEM_PTR
LDAA SCSR,X ; clear TDRE flag
LDAA 0,Y ; get char from array
BEQ DONE ; if char==$00, exit
STAA SCDR,X ; else transmit that char
INY
STY MEM_PTR
DONE RTI