TIBPAL 16L8-15C, TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8-15C TIBPAL 16L8-20M, TIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL

16R8-20M HIGH-PERFORMANCE IMPACT PAL CIRCUITS

SRPS019A FEBRUARY 1984 REVISED APRIL 2000

D D D D D

High-Performance Operation: Propagation Delay C Suffix . . . 15 ns Max M Suffix . . . 20 ns Max Functionally Equivalent, but Faster Than PAL16L8A, PAL16R4A, PAL16R6A, and PAL16R8A Power-Up Clear on Registered Devices (All Register Outputs Are Set High, but Voltage Levels at the Output Pins Go Low) Package Options Include Both Plastic and Ceramic Chip Carriers in Addition to Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability
I INPUTS 10 8 8 8 3-STATE O OUTPUTS 2 0 0 0 REGISTERED Q OUTPUTS 0 4 (3-state buffers) 6 (3-state buffers) 8 (3-state buffers) I/O PORTS 6 4 2 0

TIBPAL16L8 C SUFFIX . . . J OR N PACKAGE M SUFFIX . . . J OR W PACKAGE (TOP VIEW)

I I I I I I I I I GND

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

VCC O I/O I/O I/O I/O I/O I/O O I

DEVICE PAL16L8 PAL16R4 PAL16R6 PAL16R8

TIBPAL16L8 C SUFFIX . . . FN PACKAGE M SUFFIX . . . FK PACKAGE (TOP VIEW)

I I I VCC
3 2 4 5 6 7 8

description
These programmable array logic devices feature high speed and functional equivalency when compared with currently available devices. These IMPACT circuits combine the latest Advanced Low-Power Schottky technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic. Their easy programmability allows for quick design of custom functions and typically results in a more compact circuit board. In addition, chip carriers are available for further reduction in board space. The TIBPAL16 C series is characterized from 0C to 75C. The TIBPAL16 M series is characterized for operation over the full military temperature range of 55C to 125C.

I I I I I

1 20 19 18 17 16 15

O I/O I/O I/O I/O I/O

14 9 10 11 12 13

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. These devices are covered by U.S. Patent 4,410,987. IMPACT is a trademark of Texas Instruments. PAL is a registered trademark of Advanced Micro Devices Inc.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 2000, Texas Instruments Incorporated

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I GND I O I/O

SRPS019A FEBRUARY 1984 REVISED APRIL 2000

TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8-15C TIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16R8-20M HIGH-PERFORMANCE IMPACT PAL CIRCUITS
TIBPAL16R4 C SUFFIX . . . J OR N PACKAGE M SUFFIX . . . J OR W PACKAGE (TOP VIEW) TIBPAL16R4 C SUFFIX . . . FN PACKAGE M SUFFIX . . . FK PACKAGE (TOP VIEW)

I I CLK VCC
3 2 4 5 6 7 8

10

11

TIBPAL16R6 C SUFFIX . . . J OR N PACKAGE M SUFFIX . . . J OR W PACKAGE (TOP VIEW)

TIBPAL16R6 C SUFFIX . . . FN PACKAGE M SUFFIX . . . FK PACKAGE (TOP VIEW)

I I CLK VCC

I GND

CLK I I I I I I I I GND

1 2 3 4 5 6 7 8 9

20 19 18 17 16 15 14 13 12

VCC I/O I/O Q Q Q Q I/O I/O OE

I I I I I

1 20 19 18 17 16 15

I/O I/O Q Q Q Q I/O

17 16 15

14 9 10 11 12 13

10

11

TIBPAL16R8 C SUFFIX . . . J OR N PACKAGE M SUFFIX . . . J OR W PACKAGE (TOP VIEW)

TIBPAL16R8 C SUFFIX . . . FN PACKAGE M SUFFIX . . . FK PACKAGE (TOP VIEW)

10

11

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I GND

CLK I I I I I I I I GND

1 2 3 4 5 6 7 8 9

20 19 18 17 16 15 14 13 12

VCC Q Q Q Q Q Q Q Q OE

I I CLK VCC

I GND

CLK I I I I I I I I GND

1 2 3 4 5 6 7 8 9

20 19 18 17 16 15 14 13 12

VCC I/O Q Q Q Q Q Q I/O OE

I I I I I

3 2 4 5 6 7 8

1 20 19 18

OE I/O I/O Q Q Q Q Q
1 20 19 18 17 16 15

14 9 10 11 12 13

I I I I I

3 2 4 5 6 7 8

Q Q Q Q Q Q

14 9 10 11 12 13

OE Q Q

OE I/O Q

TIBPAL 16L8-15C, TIBPAL 16R4-15C TIBPAL 16L8-20M, TIBPAL 16R4-20M HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS019A FEBRUARY 1984 REVISED APRIL 2000

functional block diagrams (positive logic)

TIBPAL16L8 & 32 64 7 7 16 7 7 6 16 7 7 7 7 6 EN 1 O O I/O I/O I/O I/O I/O I/O

10

16

TIBPAL16R4 OE CLK & 32 64 8 8 8 16 8 4 4 16 7 7 7 7 4 4 denotes fused inputs EN 1 I/O I/O I/O I/O Q 1 EN 2 C1 I=1 2 1D Q Q Q

16

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SRPS019A FEBRUARY 1984 REVISED APRIL 2000

TIBPAL 16R6-15C, TIBPAL 16R8-15C TIBPAL 16R6-20M, TIBPAL 16R8-20M HIGH-PERFORMANCE IMPACT PAL CIRCUITS
functional block diagrams (positive logic)
TIBPAL16R6 OE CLK & 32 64 8 8 8 16 8 6 8 2 16 8 EN 1 Q Q Q 1 EN 2 C1 I=1 2 1D Q Q Q

16

7 7 2 6

I/O I/O

TIBPAL16R8 OE CLK & 32 64 8 8 8 16 8 8 8 16 8 8 8 Q Q Q Q Q 1 EN 2 C1 I=1 2 1D Q Q Q

16 I 8

8 denotes fused inputs

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TIBPAL 16L8-15C TIBPAL 16L8-20M HIGH-PERFORMANCE IMPACT PAL CIRCUITS

SRPS019A FEBRUARY 1984 REVISED APRIL 2000

logic diagram (positive logic)

I 1 Increment 0 4 8 12 16 20 24 28 31

First Fuse Numbers

0 32 64 96 128 160 192 224

19

256 288 320 352 384 416 448 480 512 544 576 608 640 672 704 736 768 800 832 864 896 928 960 992 1024 1056 1088 1120 1152 1184 1216 1248 1280 1312 1344 1376 1408 1440 1472 1504 1536 1568 1600 1632 1664 1696 1728 1760 1792 1824 1856 1888 1920 1952 1984 2016

18

I/O

17

I/O

16

I/O

15

I/O

14

I/O

13

I/O

12

11

Fuse number = First fuse number + Increment

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SRPS019A FEBRUARY 1984 REVISED APRIL 2000

TIBPAL 16R4-15C TIBPAL 16R4-20M HIGH-PERFORMANCE IMPACT PAL CIRCUITS

logic diagram (positive logic)
CLK 1 Increment 0 4 8 12 16 20 24 28 31

First Fuse Numbers

0 32 64 96 128 160 192 224

19

I/O

256 288 320 352 384 416 448 480 512 544 576 608 640 672 704 736 768 800 832 864 896 928 960 992 1024 1056 1088 1120 1152 1184 1216 1248 1280 1312 1344 1376 1408 1440 1472 1504 1536 1568 1600 1632 1664 1696 1728 1760 1792 1824 1856 1888 1920 1952 1984 2016

18

I/O

I=1 1D C1

17

I=1 1D C1

16

I=1 1D C1

15

I=1 1D C1

14

13

I/O

12

I/O

11

OE

Fuse number = First fuse number + Increment

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TIBPAL 16R6-15C TIBPAL 16R6-20M HIGH-PERFORMANCE IMPACT PAL CIRCUITS

SRPS019A FEBRUARY 1984 REVISED APRIL 2000

logic diagram (positive logic)

CLK 1 Increment 0 4 8 12 16 20 24 28 31

First Fuse Numbers

0 32 64 96 128 160 192 224

19

I/O

256 288 320 352 384 416 448 480 512 544 576 608 640 672 704 736 768 800 832 864 896 928 960 992 1024 1056 1088 1120 1152 1184 1216 1248 1280 1312 1344 1376 1408 1440 1472 1504 1536 1568 1600 1632 1664 1696 1728 1760 1792 1824 1856 1888 1920 1952 1984 2016

I=1 1D C1

18

I=1 1D C1

17

I=1 1D C1

16

I=1 1D C1

15

I=1 1D C1

14

I=1 1D C1

13

12

I/O

11

OE

Fuse number = First fuse number + Increment

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SRPS019A FEBRUARY 1984 REVISED APRIL 2000

TIBPAL 16R8-15C TIBPAL 16R8-20M HIGH-PERFORMANCE IMPACT PAL CIRCUITS

logic diagram (positive logic)
CLK 1 Increment 0 4 8 12 16 20 24 28 31 First Fuse Numbers
0 32 64 96 128 160 192 224

I=1 1D C1

19

256 288 320 352 384 416 448 480 512 544 576 608 640 672 704 736 768 800 832 864 896 928 960 992 1024 1056 1088 1120 1152 1184 1216 1248 1280 1312 1344 1376 1408 1440 1472 1504 1536 1568 1600 1632 1664 1696 1728 1760 1792 1824 1856 1888 1920 1952 1984 2016

I=1 1D C1

18

I=1 1D C1

17

I=1 1D C1

16

I=1 1D C1

15

I=1 1D C1

14

I=1 1D C1

13

I=1 1D C1

12

11 OE

Fuse number = First fuse number + Increment

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TIBPAL 16L8-15C, TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8-15C HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS019A FEBRUARY 1984 REVISED APRIL 2000

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 75C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
NOTE 1: These ratings apply, except for programming pins, during a programming cycle.

recommended operating conditions

MIN VCC VIH VIL IOH IOL fclock tw tsu th Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Clock frequency duration clock (see Note 2) Pulse duration, Setup time, input or feedback before clock Hold time, input or feedback after clock High Low 0 8 9 15 0 4.75 2 NOM 5 MAX 5.25 5.5 0.8 3.2 24 50 UNIT V V V mA mA MHz ns ns ns

TA Operating free-air temperature 0 25 75 C NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, fclock. The minimum pulse durations specified are for clock high or low only, but not for both simultaneously.

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TIBPAL 16L8-15C, TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8-15C HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS019A FEBRUARY 1984 REVISED APRIL 2000

electrical characteristics over recommended operating free-air temperature range

PARAMETER VIK VOH VOL IOZH IOZL II IIH IIL IO Outputs I/O ports Outputs I/O ports VCC = 4.75 V, VCC = 4.75 V, VCC = 4.75 V, VCC = 5 5.25 25 V V, VCC = 5 5.25 25 V V, VCC = 5.25 V, VCC = 5.25 V, VCC = 5.25 V, VCC = 5.25 V, TEST CONDITIONS II = 18 mA IOH = 3.2 mA IOL = 24 mA VO = 2.7 27V VO = 0.4 04V VI = 5.5 V VI = 2.7 V VI = 0.4 V VO = 2.25 V 30 MIN 2.4 TYP 3.3 0.35 0.5 20 100 20 250 0.1 20 0.2 125 MAX 1.5 UNIT V V V A A mA A mA mA

ICC VCC = 5.25 V, VI = 0, Outputs open 140 180 mA All typical values are at VCC = 5 V, TA = 25C. The output conditions have been chosen to produce a current that closely approximates one-half of the short-circuit output current, IOS.

switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER fmax tpd tpd ten tdis ten tdis FROM (INPUT) I, I/O CLK OE OE I, I/O I, I/O TO (OUTPUT) O, I/O Q Q Q O, I/O O, I/O R1 = 500 , R2 = 500 , S Fi See Figure 3 TEST CONDITIONS MIN 50 10 8 8 7 10 10 15 12 12 10 15 15 TYP MAX UNIT MHz ns ns ns ns ns ns

All typical values are at VCC = 5 V, TA = 25C.

10

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TIBPAL 16L8-20M, TIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16R8-20M HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS019A FEBRUARY 1984 REVISED APRIL 2000

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55C to 125C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
NOTE 1: These ratings apply, except for programming pins, during a programming cycle.

recommended operating conditions

MIN VCC VIH VIL IOH IOL fclock tw tsu th Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Clock frequency duration clock (see Note 2) Pulse duration, Setup time, input or feedback before clock Hold time, input or feedback after clock High Low 0 10 11 20 0 4.5 2 NOM 5 MAX 5.5 5.5 0.8 2 12 41.6 UNIT V V V mA mA MHz ns ns ns

TA Operating free-air temperature 55 25 125 C NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, fclock. The minimum pulse durations specified are for clock high or low only, but not for both simultaneously.

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11

TIBPAL 16L8-20M, TIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16R8-20M HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS019A FEBRUARY 1984 REVISED APRIL 2000

electrical characteristics over recommended operating free-air temperature range

PARAMETER VIK VOH VOL IOZH IOZL II Outputs I/O ports Outputs I/O ports Pin 1, 11 All others Pin 1, 11 IIH I/O ports All others IIL IOS ICC I/O ports All others VCC = 5 5.5 5V V, VCC = 5.5 V, VCC = 5.5 V, VI = 0 0.4 4V VO = 0.5 V VI = 0, 30 Outputs open 140 VCC = 5.5 V, VI = 2.7 V VCC = 4.5 V, VCC = 4.5 V, VCC = 4.5 V, VCC = 5 5.5 5V V, VCC = 5 5.5 5V V, VCC = 5 5.5 5V V, TEST CONDITIONS II = 18 mA IOH = 2 mA IOL = 12 mA VO = 2.7 27V VO = 0.4 04V VI = 5 5.5 5V MIN 2.4 TYP 3.2 0.25 0.4 20 100 20 250 0.2 0.1 50 100 20 0.25 0.2 250 190 mA mA mA A MAX 1.5 UNIT V V V A A mA

All typical values are at VCC = 5 V, TA = 25C. Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set VO at 0.5 V to avoid test-equipment degradation.

switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER fmax tpd tpd ten tdis ten tdis FROM (INPUT) I, I/O CLK OE OE I, I/O I, I/O TO (OUTPUT) O, I/O Q Q Q O, I/O O, I/O R1 = 390 , R2 = 750 , S Fi See Figure 4 TEST CONDITIONS MIN 41.6 10 8 8 7 10 10 20 15 15 15 20 20 TYP MAX UNIT MHz ns ns ns ns ns ns

All typical values are at VCC = 5 V, TA = 25C.

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TIBPAL 16L8-15C, TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8-15C TIBPAL 16L8-20M, TIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16R8-20M HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS019A FEBRUARY 1984 REVISED APRIL 2000

programming information
Texas Instruments programmable logic devices can be programmed using widely available software and inexpensive device programmers. Complete programming specifications, algorithms, and the latest information on hardware, software, and firmware are available upon request. Information on programmers capable of programming Texas Instruments programmable logic also is available, upon request, from the nearest TI field sales office or local authorized TI distributor, by calling Texas Instruments at +1 (972) 6445580, or by visiting the TI Semiconductor Home Page at www.ti.com/sc.

preload procedure for registered outputs (see Figure 1 and Note 3)

The output registers can be preloaded to any desired state during device testing. This permits any state to be tested without having to step through the entire state-machine sequence. Each register is preloaded individually by following the steps given below. Step 1. Step 2. Step 3. Step 4. With VCC at 5 V and Pin 1 at VIL, raise Pin 11 to VIHH. Apply either VIL or VIH to the output corresponding to the register to be preloaded. Pulse Pin 1, clocking in preload data. Remove output voltage, then lower Pin 11 to VIL. Preload can be verified by observing the voltage level at the output pin.
VIHH Pin 11 tsu td Pin 1 tw VIH VIL td VIL

VIH Registered I/O Input VIL NOTE 3: td = tsu = th = 100 ns to 1000 ns VIHH = 10.25 V to 10.75 V Output

VOH VOL

Figure 1. Preload Waveforms

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13

SRPS019A FEBRUARY 1984 REVISED APRIL 2000

TIBPAL 16L8-15C, TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8-15C TIBPAL 16L8-20M, TIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16R8-20M HIGH-PERFORMANCE IMPACT PAL CIRCUITS
power-up reset (see Figure 2)
Following power up, all registers are set high. This feature provides extra flexibility to the system designer and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is important that the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable input and feedback setup times are met.
VCC 4V tpd (600 ns TYP, 1000 ns MAX) Active-Low Registered Output VOH 1.5 V VOL tsu VIH CLK 1.5 V tw This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data. This is the setup time for input or feedback. 1.5 V VIL 5V

Figure 2. Power-Up Reset Waveforms

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TIBPAL 16L8-15C, TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8-15C HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS019A FEBRUARY 1984 REVISED APRIL 2000

PARAMETER MEASUREMENT INFORMATION

7V

S1 R1 From Output Under Test CL (see Note A) R2 Test Point

LOAD CIRCUIT FOR 3-STATE OUTPUTS

Timing Input tsu Data Input 1.3 V

3.5 V 1.3 V 0.3 V th 3.5 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES

High-Level Pulse

3.5 V 1.3 V tw 1.3 V 0.3 V

Low-Level Pulse

3.5 V 1.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS PULSE DURATIONS

3.5 V Input tpd In-Phase Output tpd Out-of-Phase Output (see Note D) 1.3 V 1.3 V 1.3 V 1.3 V 0.3 V tpd VOH 1.3 V VOL tpd VOH 1.3 V VOL

Output Control (low-level enabling) ten

3.5 V 1.3 V 1.3 V 0.3 V tdis 3.5 V VOL + 0.3 V VOL ten tdis VOH 1.3 V VOH 0.3 V 0 V

Waveform 1 S1 Closed (see Note B)

1.3 V

Waveform 2 S1 Open (see Note B)

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses have the following characteristics: PRR 1 MHz, tr = tf 2 ns, duty cycle = 50% D. When measuring propagation delay times of 3-state outputs from low to high, switch S1 is closed. When measuring propagation delay times of 3-state outputs from high to low, switch S1 is open. E. Equivalent loads may be used for testing.

Figure 3. Load Circuit and Voltage Waveforms

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TIBPAL 16L8-20M, TIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16R8-20M HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS019A FEBRUARY 1984 REVISED APRIL 2000

PARAMETER MEASUREMENT INFORMATION

5V

S1 R1 From Output Under Test CL (see Note A) R2 Test Point

LOAD CIRCUIT FOR 3-STATE OUTPUTS

Timing Input tsu Data Input 1.5 V

3V 1.5 V 0 th 3V 1.5 V 0 VOLTAGE WAVEFORMS SETUP AND HOLD TIMES

High-Level Pulse

3V 1.5 V tw 1.5 V 0

Low-Level Pulse

3V 1.5 V 1.5 V 0 VOLTAGE WAVEFORMS PULSE DURATIONS

3V Input tpd In-Phase Output tpd Out-of-Phase Output (see Note D) 1.5 V 1.5 V 1.5 V 1.5 V 0 tpd VOH 1.5 V VOL tpd VOH 1.5 V VOL

Output Control (low-level enabling) ten

3V 1.5 V 1.5 V 0 tdis 3.3 V VOL + 0.5 V VOL ten tdis VOH 1.5 V VOH 0.5 V 0 V

Waveform 1 S1 Closed (see Note B)

1.5 V

Waveform 2 S1 Open (see Note B)

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses have the following characteristics: PRR 10 MHz, tr = tf 2 ns, duty cycle = 50% D. When measuring propagation delay times of 3-state outputs, switch S1 is closed. E. Equivalent loads may be used for testing.

Figure 4. Load Circuit and Voltage Waveforms

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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TIs standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customers applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TIs publication of information regarding any third partys products or services does not constitute TIs approval, warranty or endorsement thereof.

Copyright 2000, Texas Instruments Incorporated