IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO.

8, AUGUST 2003

481

Transactions Brief___________________________________________________________________
Absolute-Value Circuit Using Junction Field-Effect Transistors
Alexandru A. Ciubotaru

AbstractA novel configuration for an absolute-value circuit (full-wave rectifier with zero threshold) using two matched junction field-effect transistors is proposed and experimentally demonstrated. The zero-threshold rectification is accompanied by a scaling of the input signal by a theoret2, and is achieved by mathematically exploiting the nonical factor of 1 linear characteristics of the transistors. The circuit operates with complementary input signals and requires a dc bias voltage for the transistor gates. Negative or positive output voltages can be obtained by using either - or p-channel devices. Index TermsCircuit functions, JFET analog integrated circuits, JFETs, nonlinear circuits, rectifiers.

Fig. 1.

Proposed absolute-value circuit.

I. INTRODUCTION Absolute-value circuits (sometimes known as full-wave rectifiers) are widely used in analog electronics in applications such as ac measurements, function fitting, providing inputs to single-quadrant devices, triangular-wave frequency doubling, error measurements, average envelope detection, and clock recovery [1][3]. For these and other analog signal processing circuits there is a continuous reduction in supply voltage and power consumption, driven primarily by portability requirements. The ever-shrinking headroom available to the active devices causes important mutations in the circuit topology, such as the absence of Darlington pairs, cascodes, and even emitter followers [4]. Thus, it becomes increasingly difficult to avoid the degradation of performance due to these topological changes, and new circuit configurations capable of high performance with low supply voltages must be invented. Although there exists a wide variety of absolute-value circuits, most of the proposed topologies to date are either not suitable for operation in low supply voltage environments (on the order of 1 V), or are not very accurate. Examples of circuits in the former category can be found in [5][14], where relatively large supply voltages are required typically because of complementary devices, current mirrors, or the need to accommodate logic signals for switches; an example in the latter category is [15], where relatively inaccurate transfer characteristics are accepted as approximations for the absolute-value function. There are also other implementations of the absolute-value function using current-mode circuits [16][19]. Although one of the circuits proposed in [16] does have the potential of operating with low supply voltages, the schematic is relatively complicated and requires three operational amplifiers. The CMOS circuits described in [17][19] are comparatively simple but require a current input, and a transconductor must be used in case the input is a voltage; moreover, a current mirror (which further limits the minimum acceptable supply voltage) must be used for true absolute-value operation.

This brief presents a simple and novel absolute-value circuit which uses two matched symmetrical junction field-effect transistors (JFETs) to eliminate the disadvantages associated with low supply voltages. The zero-threshold rectification takes place indirectly at the transistor level, as a mathematical consequence of the JFET nonlinearities. In this way, the circuit works with low supply voltages that accommodate only two complementary input voltages without any headroom for additional circuitry, being very attractive for use in portable systems. The present circuit also uses a dc bias voltage for the gates of the JFETs, which is very easy to generate and requires only a small bias current. If n-channel devices are used, the output of the circuit is a negative voltage; a positive output is generated for p-channel devices. p The theoretical scaling factor between input and output is 1= 2, and is not a function of the JFET parameters (notably the drain saturation current and the pinch-off voltage). The circuit is somewhat related to several other nonlinear JFET circuits that use complementary input voltages [20][24], and can easily be realized in monolithic form or be integrated in more complex systems. II. PRINCIPLE OF OPERATION The proposed circuit is shown in Fig. 1, where Q1 and Q2 are identical and symmetrical n-channel JFETs (the drain and source of a symmetrical JFET can be interchanged without affecting the characteristics of the transistor). For an input voltage vIN > 0 and assuming a sufficiently large load resistance RL such that iL  iD1 ; iD2 (i.e., iD 1  = iD2 ); Q1 operates in saturation and Q2 operates in the triode region (vice versa for vIN negative). These operating conditions are not evident at this point, but will be confirmed by computing vOUT and the transistor voltages using the appropriate saturation- and triode-region expressions for the drain currents. Thus, if the dc bias voltage is set equal to the JFET pinch-off voltage VP , currents iD1 and iD2 can be written as [25]

D1 = IDSS D2 = IDSS

0 GS1 P GS2 DS2 2 10 0P0 P

1
v V v v V V

(1)
vDS2 V

(2)

Manuscript received May 7, 2002. This paper was recommended by Associate Editor L. Trajkovic The author is with the Maxim Integrated Products, Melbourne Design Center, Melbourne, FL 32934 USA (e-mail: alexc@mxim.com). Digital Object Identifier 10.1109/TCSII.2003.813587

where vGS1 = VP 0vOUT ; vGS2 = VP +vIN and vDS2 = vOUT +vIN . After a few manipulations that are not shown, from iD1  = iD2 and using (1) and (2), it follows that
vIN

02

vOUT

 =0

(3)

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 8, AUGUST 2003

Fig. 2. Circuit for accurately generating the dc bias voltage in Fig. 1.

which yields vOUT  = 6 1= 2 jvIN j. The positive solution is not valid because it turns off Q1 (vGS1 < VP ; iDS1 = 0); the correct solution is then
vOUT

1 jv j:  = 0p IN 2

(4)
Fig. 3. Measured dc transfer characteristic (v against v ) of circuit of Fig. 1, for R 10 k
(symbols); line was obtained by nonlinear fitting, = 0:643 v . v

With the output voltage given by (4) it is easy to verify the initial assumption that Q1 and Q2 operate in saturation and in the triode region, respectively. Thus, inequality vDS1 > (vGS1 0 VP ), which is the necessary and sufficient condition for the operation of Q1 in saturation, reduces to vIN > 0, which is true; in the same way, condition vDS2 < (vGS2 0 VP ) ensures the operation of Q2 in the triode region and is true because it also reduces to vIN > 0. If vIN < 0, due to the symmetry of the transistors and the complementary input signals which revert polarity, the same expression (4) is obtained for vOUT ; thus, the circuit of Fig. 1 is an absolute-value circuit with negative output, whose gain is independent of the transistor parameters. The circuit operates correctly as long as the JFET breakdown voltages are not exceeded and the transistor junctions (gatesource and gatedrain) are not in strong forward bias. In mathematical form, these pconditions p can be expressed as jvIN j < min VGSon + jVP j; 2= 2 + 1 VBR , where VGSon is the threshold voltage of the gate-source or gate-drain junction (typically 0.6 V for silicon devices) and VBR is the JFET breakdown voltage. It is easy to show that if p-channel JFETs are used in Fig. 1 instead of n-channel devices, then the absolute-value circuit has positive output, the same input voltage range, and vOUT is
vOUT

= j j

Fig. 4. Circuit for simulating the high-frequency response of absolute-value circuit.

1 jv j:  =p IN 2

(5)

One approach for generating the dc bias voltage in Fig. 1 is illustrated in Fig. 2, where the JFET matches Q1 and Q2 , and a low-power operational amplifier can be used in portable applications for low-power dissipation. The operational amplifier can be relatively rudimentary because it does not have to drive any load and needs to provide only a dc voltage for the JFET gates, but must have low input offset voltage and drift. If the bias current I0 is sufficiently small (e.g., I0 = 0:001IDSS [26]), then the operational amplifier output voltage is practically equal to the pinch-off voltage VP of the JFETs in Fig. 1, and will track this value over temperature and fabrication process. In this way, the temperature drift of the JFET pinch-off voltage (which can be as large as 2 mV/ C [27]) or of the JFET drain saturation current IDSS will have no effect on the circuits output voltage, which will still be given by (4). III. EXPERIMENTAL RESULTS AND DISCUSSION In order to validate the proposed technique for obtaining the absolute value of a signal, the circuit of Fig. 1 was constructed using an NPDS402 n-channel dual JFET [28]. The measured parameters of the JFETs were IDSS = 2 mA and VP = 00:94 V. The gate bias of the circuit was externally generated and set to 0.94 V (VP ).

The measured dc transfer characteristic of the absolute-value circuit (vOUT against vIN ; RL = 10 k
) is shown in Fig. 3, and was obtained using 121 equally spaced vIN values in the range [01:2 V, 1.2 V]. Using the nonlinear fitting feature available in a software package [29], a function of the form K jvIN j with K as a variable was fitted to the curve of Fig. 3. The value returned by the fitting package was p K = 00:643, in good agreement with 00.707 (or 01= 2) predicted by (4). The fitting rms error was 1.29%, a very small number which indicates that the characteristic of the circuit is well approximated by an ideal absolute-value function, the rms error being calculated as
"rms

121

i=1

[K jvINi j 0 vOUTi ]2 =

121 1

2 vOUT i

2 100%

(6)

where vINi are the input voltages and vOUTi are the measured output voltages. Thus, the circuit works well even with very small signals, has virtually no threshold, and the output voltage of the circuit is accurately predicted by (4). It is also of interest to investigate the operation of the proposed absolute-value circuit at high frequencies. Due to a combination of high frequency and nonlinear effects, the dynamic operation is best illustrated by simulation, using a high-speed setup such as the one shown in Fig. 4, where the JFET capacitive parasitics are shown explicitly (CGS = CGD for symmetrical JFETs). Also explicitly shown in Fig. 4

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 8, AUGUST 2003

483

Fig. 5.

High-frequency response of absolute-value circuit.

are series resistances RS (primarily accounting for the signal sources, RS = 25

in this case), and the load capacitance CL . It is interesting to note that, for VP ideally decoupled (short to ground at ac frequencies), the total capacitance seen by the output node is approximately (CL + 2CDS + CGS + CGD), and it is this capacitance that is primarily responsible for the degradation of the high-frequency response. Using sinusoidal complementary inputs 6vIN of amplitude 0.7 V, and catalog values for the capacitances of the NPDS402 devices (CGS = CGD = 11 pF, CDS = 6 pF [28]), the output voltage of the circuit at different frequencies is shown in Fig. 5. With no intentional output capacitance CL , the high-frequency response of the circuit starts degrading at input frequencies around 1 MHz, and becomes clearly distorted at 10 MHz. An interesting effect, p however, is that the average value of the output (VAVG  = 0VIN 2=) is not affected by the input frequency or the transistor capacitances. Fig. 5 also shows the response of the circuit for an intentional CL = 220 pF, which suggests its potential use as an average-value detector at high frequencies. The dynamic response illustrated in Fig. 5 (without an external capacitance CL ) is expected to extend to much higher frequencies in a monolithic circuit, where, depending on the process technology, the parasitic device capacitances can be reduced to a fraction of a pF. The output resistance RL (allowed to assume the negligibly large value of 10 k
in the simulation shown in Fig. 5) also plays a role in the high-frequency operation of the circuit, and can be reduced to moderate values for improving the dynamic response; this improvement, however, comes at the price of reducing the low-frequency accuracy, and computer simulation and optimization must be used for determining the best tradeoff. IV. CONCLUSION A simple and novel absolute-value circuit has been presented and experimentally demonstrated. The circuit uses two matched junction field-effect transistors, and produces negative or positive output voltages according to the type (n- or p-channel) of the transistors. The transfer characteristic of the circuit is a good approximation of the p absolute-value function and has an embedded scaling factor of 1= 2.

ACKNOWLEDGMENT The contribution of two anonymous reviewers toward improving the quality of the original manuscript is gratefully acknowledged.

REFERENCES
[1] Nonlinear Circuits Handbook, D. H. Sheingold, Ed., Analog Devices, Inc., Norwood, MA, 1976, p. 23. [2] K. K. Clarke and D. T. Hess, Communication Circuits: Analysis and Design. Melbourne, FL: Krieger, 1994, p. 478. [3] J. D. Gibson, Principles of Digital and Analog Communications. New York: Macmillan, 1989, p. 199. [4] A. Matsuzawa, Low-voltage and low-power circuit design for mixed analog/digital systems in portable equipment, IEEE J. Solid-State Circuits, vol. 29, pp. 470480, Apr. 1994. [5] W. E. Hearn and D. J. Rondeau, Precision Absolute Value Amplifier for a Precision Voltmeter, U.S. Patent 4 518 877, May 21, 1985. [6] C. R. Keate, High-speed analog multiplier-aAbsolute value detector, U.S. Patent 4 833 639, May 23, 1989. [7] R. A. Neidorff, Absolute value differential amplifier, U.S. Patent 4 899 064, Feb. 6, 1990. [8] B. Abdi, Voltage to Absolute value current converter, U.S. Patent 4 906 915, Mar. 6, 1990. [9] Z. Wang, Full-wave precision rectification that is performed in current domain and very suitable for CMOS implementation, IEEE Trans. Circuits Syst. , vol. 39, pp. 456462, June 1992. [10] G. Shou, S. Takatori, and M. Yamamoto, Absolute value circuit, U.S. Patent 5 394 107, Feb. 28, 1995. [11] P. D. Walker and M. M. Green, CMOS half-wave and full-wave precision voltage rectification circuits, in Proc. 38th Midwest Symp. Circuits Syst., vol. 2, Rio de Janeiro, Brazil, Aug. 1316, 1995, pp. 901904. [12] S. Yamamoto, Absolute value circuit capable of providing full-wave rectification with less distortion, U.S. Patent 5 703 518, Dec. 30, 1997. [13] C. Kuratli and Q. Huang, A fully integrated self-calibrating transmitter/receiver IC for an ultrasound presence detector microsystem, IEEE J. Solid-State Circuits, vol. 33, pp. 832841, June 1998. [14] W. Surakampontorn, K. Anuntahirunrat, and V. Riewruja, Sinusoidal frequency doubler and full-wave rectifier using translinear current conveyor, Electron. Lett., vol. 34, pp. 20772079, Oct. 29, 1998. [15] K. Kimura, Some circuit design techniques for bipolar and MOS pseudologarithmic rectifiers operable on low supply voltage, IEEE Trans. Circuits Syst., vol. 39, pp. 771777, Sept. 1992.

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[16] F. J. Lidgey, K. Hayatleh, and C. Toumazou, New current-mode precision rectifiers, in Proc. IEEE Int. Symp. Circuits Syst., vol. 2, Chicago, IL, May 36, 1993, pp. 13221325. [17] C.-C. Chang and S.-I. Liu, Current-mode full-wave rectifier and vector summation circuit, Electron. Lett., vol. 36, pp. 15991600, Sept. 14, 2000. [18] J. Ramrez-Angulo et al., Very low-voltage class AB CMOS and bipolar precision current rectifiers, in Electron. Lett., vol. 35, Oct. 28, 1999, pp. 19041905. , Very low-voltage class AB CMOS precision voltage and cur[19] rent rectifiers, in Proc. IEEE Int. Symp. Circuits Syst., vol. 3, Geneva, Switzerland, May 2831, 2000, pp. 58. [20] A. A. Ciubotaru, Square-law circuit using junction field-effect transistors, Electron. Lett., vol. 33, pp. 544545, Mar. 1997. , Four-quadrant multiplier using junction field-effect transistors, [21] Electron. Lett., 17, 1997. , Cube-law circuit using junction field-effect transistors, Elec[22] tron. Lett., vol. 34, pp. 11751176, June 1998. , 4th power-law circuits using junction field-effect transistors, [23] Electron. Lett., vol. 35, pp. 469471, Mar. 1999. , Fifth power-law circuits using junction field-effect transistors, [24] Electron. Lett., vol. 36, pp. 14421443, Aug. 2000. [25] A. S. Sedra and K. C. Smith, Microelectronic Circuits. New York: Holt, Rinehart, Winston, 1987, pp. 268269. [26] Field Effect Transistors in Theory and Practice, Motorola, Inc., Phoenix, AZ, Application Note AN211A, 1993. [27] L. J. Sevin Jr, Field-Effect Transistors. New York: McGraw-Hill, 1965, p. 35. [28] Discrete Semiconductor ProductsDiode, Bipolar Transistor, and JFET Products Databook, National Semiconductor Corp., Santa Clara, CA, 1996. National Semiconductor Corp.. [29] Mathematica, Wolfram Research, Inc., Champaign, IL, 1993. Wolfram Research, Inc., Version 2.2.

A Neural Network for Constrained Optimization With Application to CDMA Communication Systems
R. Fantacci, M. Forti, M. Marini, D. Tarchi, and G. Vannuccini
AbstractThis brief proposes a neural network for the solution in real time of a class of quadratic optimization problems with equality and inequality constraints arising in code-division multiple access (CDMA) communication systems. The network, which is derived via a nonobvious modification of the circuit for nonlinear programming introduced by Kennedy and Chua, is shown to be globally asymptotically stable, and as such is able to compute the global optimal solution in real time, without the risk of spurious responses. Computer simulations are presented to verify the neural network optimization capabilities and speed, and the performance in the application to CDMA communication systems. Index TermsCode-division multiple access (CDMA) communication systems, constrained optimization problems, neural networks.

essentially degraded by the multiple-access interference (MAI) caused by the presence of simultaneous users. Hence, methods for MAI attenuation are of fundamental importance [1][4]. Also, MAI is rapidly time varying, due to the time variation of both the number of transmitting users and channel propagation conditions (i.e., transmission multipath and fading) [3], [4]. A basic approach to mitigate MAI effects in CDMA systems is blind adaptive interference suppression [2], which relies on the use within the receiver of an adaptive filter for MAI attenuation. From a mathematical viewpoint, the adaptive filter proposed in [2] is designed via the optimization of the mean energy at the filter output, subject to suitable constraints. Such an optimization problem is convex (see [2, Sec. II]), and the commonly employed algorithms for solving the problem are those based on the stochastic gradient descendent rule [1], [3]. However, as it was pointed out in [3], the main drawback of these sequential algorithms is that their convergence is too slow with respect to the time variations of MAI. This in turn impairs their practical applicability to actual wireless CDMA communication systems. One could also apply other methods [5] for solving convex optimization problems, such as interior point algorithms. However, it is expected that those algorithms are too complex to implement on mobile user terminals, due to the stringent limitations on the hardware. In this brief, we theoretically investigate the possible use of a neural network approach to solve the constrained optimization problem arising in blind adaptive interference suppression. The goal is to exploit the real time optimization capabilities of neural networks in order to significantly improve the optimization speed with respect to existing sequential algorithms. To achieve the previous goal, a special neural network is introduced, which derives from a nonobvious modification of the neural network for nonlinear programming proposed by Kennedy and Chua in [6]. The proposed neural network is realizable as a relatively simple analog circuit [6], and can be implemented in principle on mobile user terminals in CDMA systems. More specifically, the optimization problem at hand involves both inequality and equality constraints. We recall that the neural network in [6] was conceived for optimization in the presence of inequality constraints, only. Though an equality constraint can be mathematically brought back to a pair of simultaneous inequalities, there are technical problems for the implementation. In fact, this would require the use of two inverted diodes, which could not work properly in practice [7]. An original technique is thus proposed in this paper to exactly satisfy the required equality constraints, which is based on projecting the gradient of the energy function onto the space where the equality constraints are satisfied. This leads to the definition of a new class of neural dynamical systems which has potential applications also to solve other optimization problems. We refer the reader to [8] and [9], and their references, for other applications in the telecommunications field where the use of neural networks has already proven effective. II. OPTIMIZATION PROBLEM FORMULATION The theory of blind interference suppression has been developed in [2], see also [1]. From a mathematical point of view, the optimal adaptive filter coefficients in a blind CDMA receiver are obtained via the minimization of the mean energy at the filter output. If the mean is evaluated over a window of bits of length L, in the generic ith bit it is required to minimize the function [2]
1
L

I. INTRODUCTION One of the most promising techniques for simultaneous transmission of multiple users in wireless communication systems, is code-division multiple access (CDMA) [1]. The performance of a CDMA system is
Manuscript received June 6, 2001; revised September 19, 2002. This paper was recommended by Associate Editor P. Kennedy. R. Fantacci, M. Marini, D. Tarchi, and G. Vannuccini are with the Dipartimento di Elettronica e Telecomunicazioni, Universit di Firenze, Firenze 50139 Italy. M. Forti is with the Dipartimento di Ingegneria dellInformazione, Universit di Siena, 53100 Siena, Italy. Digital Object Identifier 10.1109/TCSII.2003.814805

L01 j =0

E (x)

h[0
y i

j ]; x

+s

i2

(1)

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